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riscv32: added a generic linker script for the riscv32 platform

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Added a linker script that shall be common to most riscv SOCs.
Linker script also accounts for execution in place in ROM, when
CONFIG_XIP is set.

Nonetheless, riscv32 SOCs (like pulpino) requiring a different
system layout can still define their own linker script.

Change-Id: I3ad670446d439772c29a8204e307ac79643dc650
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This commit is contained in:
Jean-Paul Etienne 2017-02-01 02:25:26 +01:00
commit 47e2f4e3d7
7 changed files with 76 additions and 58 deletions
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3
arch/riscv32/Makefile
View file

@ -14,3 +14,6 @@ soc-aflags ?= $(soc-cflags)
KBUILD_CFLAGS += $(soc-cflags)
KBUILD_CXXFLAGS += $(soc-cxxflags)
KBUILD_AFLAGS += $(soc-aflags)
soc_ld_include := -I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/
EXTRA_LINKER_CMD_OPT += $(soc_ld_include)

3
arch/riscv32/core/prep_c.c
View file

@ -31,6 +31,9 @@
void _PrepC(void)
{
_bss_zero();
#ifdef CONFIG_XIP
_data_copy();
#endif
_Cstart();
CODE_UNREACHABLE;
}

10
arch/riscv32/soc/riscv32-qemu/Kconfig.defconfig
View file

@ -20,19 +20,19 @@ config NUM_IRQS
int
default 32
config VECTOR_BASE_ADDR
config RISCV_ROM_BASE_ADDR
hex
default 0x00001000
config VECTOR_SIZE
config RISCV_ROM_SIZE
hex
default 0x1000
default 0x100000
config RAM_BASE_ADDR
config RISCV_RAM_BASE_ADDR
hex
default 0x80000000
config RAM_SIZE_MB
config RISCV_RAM_SIZE_MB
int
default 32

2
arch/riscv32/soc/riscv32-qemu/linker.ld
View file

@ -8,4 +8,4 @@
* @brief Linker script for riscv32-qemu
*/
#include <arch/riscv32/riscv32-qemu/linker.ld>
#include <arch/riscv32/common/linker.ld>

11
arch/riscv32/soc/riscv32-qemu/soc.h
View file

@ -11,6 +11,8 @@
#ifndef __RISCV32_QEMU_SOC_H_
#define __RISCV32_QEMU_SOC_H_
#include <misc/util.h>
/* CSR Registers */
#define RISCV_QEMU_MSTATUS mstatus /* Machine Status Register */
@ -56,18 +58,17 @@
#define RISCV_MTIME_BASE 0x40000000
#define RISCV_MTIMECMP_BASE 0x40000008
/* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
#define RISCV_RAM_SIZE MB(CONFIG_RISCV_RAM_SIZE_MB)
#ifndef _ASMLANGUAGE
#include <irq.h>
#include <misc/util.h>
#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
void soc_interrupt_init(void);
#endif
/* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE CONFIG_RAM_BASE_ADDR
#define RISCV_RAM_SIZE MB(CONFIG_RAM_SIZE_MB)
#endif /* !_ASMLANGUAGE */
#endif /* __RISCV32_QEMU_SOC_H_ */

2
boards/riscv32/qemu_riscv32/Makefile.board
View file

@ -2,7 +2,7 @@
EMU_PLATFORM = qemu
QEMU_CPU_TYPE_riscv32 = riscv32
QEMU_FLAGS_riscv32 = -machine sifive -nographic -m $(CONFIG_RAM_SIZE_MB)
QEMU_FLAGS_riscv32 = -machine sifive -nographic -m $(CONFIG_RISCV_RAM_SIZE_MB)
QEMU_riscv32 = qemu-system-riscv32
DEBUG_SCRIPT = qemu.sh

103
include/arch/riscv32/riscv32-qemu/linker.ld → include/arch/riscv32/common/linker.ld
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,93 +8,68 @@
* @file
* @brief Linker command/script file
*
* Linker script for the riscv32-qemu platform
* Generic Linker script for the riscv32 platform
*/
#define _LINKER
#define _ASMLANGUAGE
#include <soc.h>
#include <autoconf.h>
#include <sections.h>
#include <linker-defs.h>
#include <linker-tool.h>
#ifdef CONFIG_XIP
#define ROMABLE_REGION ROM
#else
#define ROMABLE_REGION RAM
#endif
#define RAMABLE_REGION RAM
#define _VECTOR_SECTION_NAME vector
#define _EXCEPTION_SECTION_NAME exceptions
#define _RESET_SECTION_NAME reset
#define RAM_LENGTH (CONFIG_RAM_SIZE_MB * 1024 * 1024)
ENTRY(__reset)
MEMORY
{
VECTOR (rx) : ORIGIN = CONFIG_VECTOR_BASE_ADDR, LENGTH = CONFIG_VECTOR_SIZE
RAM (rwx) : ORIGIN = CONFIG_RAM_BASE_ADDR, LENGTH = RAM_LENGTH
{
ROM (rx) : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE
RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE
}
SECTIONS
{
GROUP_START(VECTOR)
GROUP_START(ROM)
_image_rom_start = .;
SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)
{
. = ALIGN(4);
KEEP(*(.vectors.*))
} GROUP_LINK_IN(VECTOR)
} GROUP_LINK_IN(ROM)
GROUP_END(VECTOR)
GROUP_END(ROM)
GROUP_START(RAM)
GROUP_START(ROMABLE_REGION)
SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
{
KEEP(*(.reset.*))
} GROUP_LINK_IN(RAM)
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)
{
KEEP(*(".exception.entry.*"))
*(".exception.other.*")
} GROUP_LINK_IN(RAM)
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{
. = ALIGN(4);
_image_text_start = .;
*(.text)
*(".text.*")
*(.gnu.linkonce.t.*)
} GROUP_LINK_IN(RAM)
_image_text_end = .;
GROUP_END(RAM)
GROUP_START(RAMABLE_REGION)
#include <linker/common-rom.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
. = ALIGN(4);
*(.rodata)
*(".rodata.*")
*(.gnu.linkonce.r.*)
} GROUP_LINK_IN(RAMABLE_REGION)
#include <linker/common-ram.ld>
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
{
. = ALIGN(4);
KEEP(*(.isr_irq*))
/* sections for IRQ0-9 */
@ -106,15 +81,50 @@ SECTIONS
/* sections for IRQ100-999 */
KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))
_image_text_start = .;
*(.text)
*(".text.*")
*(.gnu.linkonce.t.*)
} GROUP_LINK_IN(ROMABLE_REGION)
_image_text_end = .;
#include <linker/common-rom.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
. = ALIGN(4);
*(.rodata)
*(".rodata.*")
*(.gnu.linkonce.r.*)
} GROUP_LINK_IN(ROMABLE_REGION)
_image_rom_end = .;
__data_rom_start = .;
GROUP_END(ROMABLE_REGION)
GROUP_START(RAMABLE_REGION)
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
{
. = ALIGN(4);
_image_ram_start = .;
__data_ram_start = .;
*(.data)
*(".data.*")
*(.sdata .sdata.* .gnu.linkonce.s.*)
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
} GROUP_LINK_IN(RAMABLE_REGION)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
#include <linker/common-ram.ld>
__data_ram_end = .;
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
@ -132,7 +142,7 @@ SECTIONS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
__bss_end = ALIGN(4);
} GROUP_LINK_IN(RAMABLE_REGION)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
{
@ -144,6 +154,7 @@ SECTIONS
*(".noinit.*")
} GROUP_LINK_IN(RAMABLE_REGION)
_image_ram_end = .;
_end = .; /* end of image */
GROUP_END(RAMABLE_REGION)