riscv32: added a generic linker script for the riscv32 platform
Added a linker script that shall be common to most riscv SOCs. Linker script also accounts for execution in place in ROM, when CONFIG_XIP is set. Nonetheless, riscv32 SOCs (like pulpino) requiring a different system layout can still define their own linker script. Change-Id: I3ad670446d439772c29a8204e307ac79643dc650 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
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c989f0b408
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7 changed files with 76 additions and 58 deletions
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@ -14,3 +14,6 @@ soc-aflags ?= $(soc-cflags)
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KBUILD_CFLAGS += $(soc-cflags)
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KBUILD_CXXFLAGS += $(soc-cxxflags)
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KBUILD_AFLAGS += $(soc-aflags)
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soc_ld_include := -I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/
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EXTRA_LINKER_CMD_OPT += $(soc_ld_include)
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@ -31,6 +31,9 @@
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void _PrepC(void)
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{
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_bss_zero();
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#ifdef CONFIG_XIP
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_data_copy();
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#endif
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_Cstart();
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CODE_UNREACHABLE;
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}
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@ -20,19 +20,19 @@ config NUM_IRQS
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int
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default 32
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config VECTOR_BASE_ADDR
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config RISCV_ROM_BASE_ADDR
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hex
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default 0x00001000
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config VECTOR_SIZE
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config RISCV_ROM_SIZE
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hex
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default 0x1000
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default 0x100000
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config RAM_BASE_ADDR
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config RISCV_RAM_BASE_ADDR
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hex
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default 0x80000000
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config RAM_SIZE_MB
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config RISCV_RAM_SIZE_MB
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int
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default 32
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@ -8,4 +8,4 @@
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* @brief Linker script for riscv32-qemu
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*/
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#include <arch/riscv32/riscv32-qemu/linker.ld>
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#include <arch/riscv32/common/linker.ld>
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@ -11,6 +11,8 @@
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#ifndef __RISCV32_QEMU_SOC_H_
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#define __RISCV32_QEMU_SOC_H_
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#include <misc/util.h>
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/* CSR Registers */
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#define RISCV_QEMU_MSTATUS mstatus /* Machine Status Register */
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@ -56,18 +58,17 @@
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#define RISCV_MTIME_BASE 0x40000000
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#define RISCV_MTIMECMP_BASE 0x40000008
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/* lib-c hooks required RAM defined variables */
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#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
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#define RISCV_RAM_SIZE MB(CONFIG_RISCV_RAM_SIZE_MB)
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#ifndef _ASMLANGUAGE
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#include <irq.h>
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#include <misc/util.h>
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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void soc_interrupt_init(void);
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#endif
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/* lib-c hooks required RAM defined variables */
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#define RISCV_RAM_BASE CONFIG_RAM_BASE_ADDR
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#define RISCV_RAM_SIZE MB(CONFIG_RAM_SIZE_MB)
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#endif /* !_ASMLANGUAGE */
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#endif /* __RISCV32_QEMU_SOC_H_ */
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@ -2,7 +2,7 @@
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EMU_PLATFORM = qemu
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QEMU_CPU_TYPE_riscv32 = riscv32
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QEMU_FLAGS_riscv32 = -machine sifive -nographic -m $(CONFIG_RAM_SIZE_MB)
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QEMU_FLAGS_riscv32 = -machine sifive -nographic -m $(CONFIG_RISCV_RAM_SIZE_MB)
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QEMU_riscv32 = qemu-system-riscv32
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DEBUG_SCRIPT = qemu.sh
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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* Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -8,93 +8,68 @@
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the riscv32-qemu platform
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* Generic Linker script for the riscv32 platform
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*/
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#define _LINKER
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#define _ASMLANGUAGE
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#include <soc.h>
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#include <autoconf.h>
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#include <sections.h>
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#include <linker-defs.h>
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#include <linker-tool.h>
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#ifdef CONFIG_XIP
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#define ROMABLE_REGION ROM
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#else
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#define ROMABLE_REGION RAM
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#endif
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#define RAMABLE_REGION RAM
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#define _VECTOR_SECTION_NAME vector
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#define _EXCEPTION_SECTION_NAME exceptions
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#define _RESET_SECTION_NAME reset
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#define RAM_LENGTH (CONFIG_RAM_SIZE_MB * 1024 * 1024)
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ENTRY(__reset)
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MEMORY
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{
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VECTOR (rx) : ORIGIN = CONFIG_VECTOR_BASE_ADDR, LENGTH = CONFIG_VECTOR_SIZE
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RAM (rwx) : ORIGIN = CONFIG_RAM_BASE_ADDR, LENGTH = RAM_LENGTH
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{
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ROM (rx) : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE
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RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE
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}
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SECTIONS
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{
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GROUP_START(VECTOR)
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GROUP_START(ROM)
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_image_rom_start = .;
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SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)
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{
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. = ALIGN(4);
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KEEP(*(.vectors.*))
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} GROUP_LINK_IN(VECTOR)
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} GROUP_LINK_IN(ROM)
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GROUP_END(VECTOR)
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GROUP_END(ROM)
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GROUP_START(RAM)
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GROUP_START(ROMABLE_REGION)
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SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
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{
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KEEP(*(.reset.*))
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} GROUP_LINK_IN(RAM)
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} GROUP_LINK_IN(ROMABLE_REGION)
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SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)
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{
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KEEP(*(".exception.entry.*"))
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*(".exception.other.*")
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} GROUP_LINK_IN(RAM)
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} GROUP_LINK_IN(ROMABLE_REGION)
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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. = ALIGN(4);
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_image_text_start = .;
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*(.text)
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*(".text.*")
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*(.gnu.linkonce.t.*)
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} GROUP_LINK_IN(RAM)
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_image_text_end = .;
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GROUP_END(RAM)
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GROUP_START(RAMABLE_REGION)
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#include <linker/common-rom.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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*(.rodata)
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*(".rodata.*")
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*(.gnu.linkonce.r.*)
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} GROUP_LINK_IN(RAMABLE_REGION)
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#include <linker/common-ram.ld>
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SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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KEEP(*(.isr_irq*))
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/* sections for IRQ0-9 */
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@ -106,15 +81,50 @@ SECTIONS
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/* sections for IRQ100-999 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))
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_image_text_start = .;
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*(.text)
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*(".text.*")
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*(.gnu.linkonce.t.*)
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} GROUP_LINK_IN(ROMABLE_REGION)
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_image_text_end = .;
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#include <linker/common-rom.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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*(.rodata)
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*(".rodata.*")
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*(.gnu.linkonce.r.*)
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} GROUP_LINK_IN(ROMABLE_REGION)
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_image_rom_end = .;
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__data_rom_start = .;
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GROUP_END(ROMABLE_REGION)
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GROUP_START(RAMABLE_REGION)
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SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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_image_ram_start = .;
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__data_ram_start = .;
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*(.data)
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*(".data.*")
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
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} GROUP_LINK_IN(RAMABLE_REGION)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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#include <linker/common-ram.ld>
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__data_ram_end = .;
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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{
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/*
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* For performance, BSS section is assumed to be 4 byte aligned and
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@ -132,7 +142,7 @@ SECTIONS
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* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
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*/
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__bss_end = ALIGN(4);
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} GROUP_LINK_IN(RAMABLE_REGION)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
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{
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@ -144,6 +154,7 @@ SECTIONS
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*(".noinit.*")
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} GROUP_LINK_IN(RAMABLE_REGION)
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_image_ram_end = .;
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_end = .; /* end of image */
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GROUP_END(RAMABLE_REGION)
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