Apply the same modifications made to the ZynqMP's memory
regions to the cortex_r8_virtual SoC which was mainlined
while the fixes for the ZynqMP were being developed
(minus the OCM mapping, as there's no indication that this
type of memory was considered).
The cortex_r8_virtual appears to be a stripped down copy
of the old qemu_cortex_r5 codebase, therefore, the duplicated
MPU regions have the same flaws as qemu_cortex_r5 or any
actual ZynqMP-based target for that matter.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Overhaul the MPU region definitions that are being
configured when the MPU is set up:
- drop local attribute definitions in favor of those
already provided in arm_mpu_v7m.h
- actually tie the RAM region to the device tree
- set up a (potentially overlapping) R/O region for
.text and .rodata, which hasn't existed so far
- Consider XIP
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Add ethernet support for RA6M4, RA6M5.
Add soc script for generating Renesas Partition Data (RFP file).
Signed-off-by: Ta Minh Nhat <nhat-minh.ta.yn@bp.renesas.com>
Singed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
The high frequency clock was always restored before handling the
interrupts to make sure that the system clock is as expected. However,
the response time to interrupt when we were in EM2 was a between 300 and
600 us. By default, we use the low interrupt latency.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
Silicon Labs controller with integrated radio each rely on a specific
binary blob (RAIL library) for using the EFR32 radio subsystem.
This commit adds support for the Silicon Labs BGM240SA22VNA SoC.
Signed-off-by: Ephraim Westenberger <ephraim.westenberger@gmail.com>
Reorganize how gen_uicr.py is invoked.
Instead of invoking it from one of the Zephyr images we invoke it from
a new special Zephyr image called uicr.
This uicr Zephyr image is flashed in the same way as normal Zephyr
images so special handling in the runner is no longer necessary.
Also, we simplify gen_uicr.py by moving parsing of Kconfig/DT from
gen_uicr.py to CMake.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Set the VERSION field to 2.0 in gen_uicr.py to indicate the version of
the format the script produces blobs for. This is required for forwards
compatibility with newer versions of IronSide SE.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Added support for retrieving the regulatory domain information from
the siwx91x driver. Since the SDK does not provide a GET API for
region details, the driver now stores the country code and reuse
the configuration `sli_si91x_set_region_ap_request_t` to get the
channel information. This stored data is returned when a GET
operation is requested.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
Moved the `siwx91x_map_country_code_to_region()` function
from the Wi-Fi driver source file to nwp.c.
This change prepares the codebase for upcoming enhancements
related to the regulatory domain GET operation.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
When GPIOF4 and GPIOF5 are not used as USB alternate function,
the default 15K pull-down should be disabled.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Use the region name token to describe the location of sections.
Because for some linkers (e.g. llvm lld) region_name and "region_name"
are not the same.
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
For better organization, split the Kconfig files into one per each CPU.
Also, there was a bug where MFD was made to depend on flexcomm being
enabled, when really it probably meant to just default y if flexcomm is
enabled.
Leave Kconfig.soc in one file for the SOC.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This update ensures that TRDC settings are correctly applied
when user space is enabled. By default, the M33 core operates
in privileged mode.
However, when user threads are scheduled, the system transitions
to unprivileged mode. The TRDC configuration is adjusted to support
this behavior, maintaining secure and functional access control
for both privileged and unprivileged execution contexts.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
RP2350 has 48 GPIOs, where only the first 30 are broken out to pins on
RP2350A (same as RP2040) and the remaining 18 are only usable on RP2350B.
This change makes the soc pinctrl driver support GPIOs above 31, where
previously it was impossible to configure GPIOs 32 through 47.
Tested on RP2350B, confirming that GPIO44 can be correctly configured for
PWM.
Signed-off-by: Peter Marheine <peter@taricorp.net>
Adding sys_poweroff to WBA family. It switches to standby
(non-retention) mode. It can be woken up by any wakeup source.
Signed-off-by: Ivan Wagner <ivan.wagner@tecinvent.ch>
- Not all MSPM0L series socs seem to have MPU. After a glance at the TI
website for features, only MSPM0L222x class socs seem to have MPU.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
- Code optimization for platforms which don't use subscription feature
in the temperature service.
- Test adaptation to code changes
Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
Add initial support for the ROC-RK3588-PC AArch64 board.
It features a quad-core Cortex-A55 CPU based on the ARMv8.2 architecture.
This commit also enables SMP, allowing all four cores to run the
synchronization sample.
Signed-off-by: Guowei Li <15035660024@163.com>
Enable cache management by default on Cortex-M7 of the STM32H7x
series. Remove cache management enablement from the ST STM32H7B3I-DK
development board.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add CONFIG_STM32_BACKUP_SRAM_INIT_PRIORITY for configuring the
initialization priority of the STM32 Backup SRAM driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Clock ctimer if being used for PWM. Otherwise, it not only doesn't work
but makes the chip unable to be communicated to by the debugger.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The RTC counter that is used in Power Mode 3 to track
System time could overflow for large timeouts.
Add code to catch wakeup events due to this overflow and re-enter
Power Mode 3.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Confirmed by section 3.7.2 in the datasheet (version 29 July 2025) and
running a sample piece of code exercising smuad, smladx and
other DSP intrinsics.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
PPR was using 1 kHz system clock frequency instead of default 31250 Hz
used on other cores with GRTC. Low frequency impacts system clock
accuracy. There is no reason to use different frequency for PPR.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The definition of the EM3 energy mode is that software switches
off the LFRCO and LFXO before entering deep sleep. On Series 2,
oscillators are clocked on-demand based on peripheral requests
from hardware. Requesting EM3 will result in EM2 if any active
peripheral uses one of the oscillators, and requesting EM2
will result in EM3 if no peripherals use the oscillators.
In version 2025.6 of the HAL, this was reflected in the API
of the power manager by making EM3 an alias of EM2. Reflect
this in Zephyr by removing the separate EM3 power state.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
When the target has only a single CPU, this function cannot ever
succeed. Skip all of the drama and just return -EINVAL. This makes GCC 14
happy as it doesn't get confused about possible out of bounds access of the
soc_cpus_active array.
Signed-off-by: Keith Packard <keithp@keithp.com>
