To address the "warning: orphan section", added
.llext_heap, .llext_ext_heap, and .llext_metadata_heap
sections to the #ifndef CONFIG_USERSPACE noinit section
in the linker script, wrapped in #ifdef CONFIG_LLEXT.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
SweRV S4xx SoCs has an external interrupt controller by design.
The corresponding driver is enabled via CONFIG_SWERV_PIC.
However, it is not fully supported in the whisper simulator.
Accessing the controller's MMIO space will result in access
fault when PMP is enabled with catchall entry. To workaround
this, we simply skip building the driver so there will be no
invalid memory access at boot. For this to work correctly,
we need to implement some basic arch_irq_*() function to
utilize the internal interrupt controller so we can still
boot and test. For non-PMP boards, we still have the driver
enabled so it is built in CI to avoid breakage.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit removes the unused mcr_regs.h header from the power.c file
in the MAX32 SoC directory.
The header is not required for current power management implementation.
Furthermore, since some MAX32 SoC variants do not include this specific
register definition, removing it prevents potential build failures and
improves cross-SoC compatibility within the series.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
If Zephyr is booted from U-Boot, ENET clock has been initialized by
U-Boot and it works, but if Zephyr is booted by using SPSDK runner,
ENET clock is not initialized and ENET will not work, so adding ENET
clock initialization in Zephyr to fix this issue.
Fixes: #106398
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The ulp_shm DTS node at 0x3bf0 overlapped with the last
16 bytes of the ulp_ram region (0x0..0x3c00) on both
ESP32-C5 and ESP32-C6.
Move ulp_shm to 0x3c00, right after ulp_ram, and shift
lp_rtc from 0x3c00 to 0x3c10 (shrinking it by 16 bytes
from 0xf8 to 0xe8) to make room. All other regions
(retainedmem, ipc_shm, mbox0) keep their addresses.
Update LP core linker scripts to stop subtracting
shared mem size from the ram segment length, since
ulp_shm is now outside the coprocessor reservation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Mark .noinit as NOLOAD to prevent LLEXT heaps included in
snippets-noinit.ld from being marked as PROGBITS.
Fixes#105858
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
NXP FlexSPI NOR flash nodes were missing the soc-nv-flash child
node expected by Zephyr's flash map API.
Without this child node, DT_MTD_FROM_FIXED_PARTITION resolved to
the FlexSPI memory controller instead of the flash device. Since
the controller has api = NULL, MCUboot could hit a NULL pointer
dereference during boot on Zephyr 4.4.
Fix this by updating the DTS structure to match the soc-nv-flash
convention used by the flash map infrastructure.
Changes:
- add a soc-nv-flash child under each nxp,imx-flexspi-nor node
- move erase-block-size, write-block-size, and partitions into it
- add ranges to flash controller nodes for address translation
- update zephyr,flash to point to the soc-nv-flash child
- add zephyr,flash-controller chosen for the flash driver node
- remove soc-nv-flash.yaml from nxp,imx-flexspi-nor.yaml
- use zephyr,flash-controller in flash CMake XIP decisions
- update FlexSPI XIP Kconfig logic to walk to the grandparent
This keeps the controller and flash device roles separate and
restores correct flash map resolution for MCUboot and XIP logic.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Since RM1170 Rev. 5 the RC400 gate control bits are marked reserved.
Remove the call to CLOCK_OSC_GateOscRc400M since the headers need
updating to remove it completely as done with the RT1180.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
- xt-clang seems to generate some memory access patterns which
result in the simulator accessing incorrect memory or messing
with cached TLB entries when spinlock validation is enabled.
- This is the same issue that was fixed for ace40 in commit
b98fc2740a (fixes#100885). Apply the same workaround to
ace30/ptl/sim and ace30/wcl/sim.
Signed-off-by: Jjateen Gundesha <jjateen97@gmail.com>
Replace SOC_SERIES_CH32V00X with SOC_SERIES_QINGKE_V2C to maintain
consistent naming across SOC series.
Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
- Add shared_memory to custom mpu regions for Infineon pse84 soc series
- This resolves a bug in the wdt_basic_api test running on the m55 core
for both the kit_pse84_eval and kit_pse84_ai platform
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
These Kconfigs were showing up in my build for a completely different
vendor. These are meant to be hidden Kconfigs meaning they do not have
descriptor strings next to their type.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
SoC, DTS, and board files should live in directories named after the
vendor prefix so rename all occurrences of synaptics/ to syna/.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The real RAM size from DT is correct but the power manager API expect to
receive either 192/256/320 KB value, so we need to round it up to the
next boundary to avoid powering down the top M4 SRAM bank.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
POWER_ClearWakeupStatus for RTC was called on the PM3 exit path,
clearing the status before the application could query the wakeup source
via NXP_GET_WAKEUP_SIGNAL_STATUS().
Move the clear to the PM3 entry path, just before re-arming the wakeup
source. This matches the existing GPIO wakeup status handling which
already clears on entry.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
The system clock frequency was not initialized, causing the
`Cy_SysLib_Delay` family of PDL functions to delay for an incorrect amount
of time.
This was fixed for the M55 in #101015, but the fix was not applied to the
M33.
Fixes#106232.
Signed-off-by: Jonathan Keller <jonathan.keller@infineon.com>
Wire the Kinetis LMEM-capable SoCs into the generic cache
management path by selecting the LMEM driver, enabling the
available instruction and system-bus cache capabilities, and
defaulting these parts to CACHE_MANAGEMENT with the external
cache backend.
Keep MCUX eDMA descriptors in the default SRAM placement on
SYSMPU-based Kinetis parts. Their SRAM region remains outside
the cached LMEM area, so they do not use the generic
NOCACHE_MEMORY path.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Update the UICR generator image to correctly track outputs and
dependencies as these depend on the options provided. This fixes
an issue where the UICR generation step was always rebuilt when
secondary PERIPHCONF was disabled, since secondary_periphconf.hex
was specified as an output but never produced. It also fixes
missing outputs/dependencies for mpcconf.hex/secondary_mpcconf.hex.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Add Kconfig and soc.yml entries for the BL706C00Q2I, which is the
base BL706 in QFN48 package without internal flash or PSRAM.
Signed-off-by: William Markezana <william.markezana@gmail.com>
In driver file flash_stm32wba_fm.c, rename ble_ctrl_work_q
to ble_ctle_work_q and make ble_ctle_work_q non-static
in SoC code
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
NRF_RTC and its numbered variants (NRF_RTC0, NRF_RTC1, NRF_RTC2,
NRF_RTC130, NRF_RTC131) are not defined on RTC-less SoCs such as
the nRF54L and nRF54H series. Wrapping the CHECK_DT_REG calls in
#ifdef guards prevents a build error when a devicetree node (e.g.
an external I2C RTC) happens to use one of these node labels.
Fixes#101686
Signed-off-by: Mohit Talwar <talwarmohit2005@gmail.com>
Add sleep hold flag to allow setting groups of pins to
automatically hold pad value during low power states (light/deep sleep).
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add hardware pad function, configurable in DTS, which holds the pin
state when transitioning to a low power state (light/deep sleep).
Once set in DTS, PM interface will automatically handle holding
the pin state before transitioning it into a low power state.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Guard the STM32WBAX power driver `mpu_state` variable with
CONFIG_ARM_MPU.
With this change, CONFIG_PM=y and CONFIG_ARM_MPU=n now build
correctly on STM32WBA.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Include file for mapping DFP macros to follow a common
macro name across multiple SoC for sercom uart g1 driver
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Add initial support for nuvoton numaker m335x SoC series
including basic init and device tree source include.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add support for configuring the High-Speed Low-Voltage (HSLV) mode
in the GPIO port manager based on the DT configuration. This
enhancement allows for improved performance at lower voltages.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
This adds the soc files for the Synaptics SR100 SoC.
Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This adds support for Cadence SweRV S420 SoC which is similar
to S400 but with support for 2 threads.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use `IRQ_CONNECT` to register the ROM-implemented `Peripheral_Handler`
for `Peripheral_IRQn` on rtl87x2g and rtl8752h SoCs.
This bridges the hardware-specific Level 1 interrupt routing from the
ROM into Zephyr's standard IRQ system, making sure that the
sub-interrupts under `Peripheral_IRQn` are properly enabled and functional.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
GDB crashes with a segfault when loading ELF files built
for Espressif SoCs. Starting with GDB 13 (commit
5abbfa982215), finish_block_internal() calls
SECT_OFF_TEXT(m_objfile) which requires sect_index_text to
be initialized. This index is only set when a section
named exactly ".text" exists in the ELF. Without it, the
index stays at -1 and GDB segfaults (upstream PR 25678).
Espressif linker scripts named the flash-mapped code
output section ".flash.text" instead of ".text", so the
final ELF had no ".text" section. Other Xtensa vendors
(Intel ADSP, Cadence) use ".text" as their output section
name and collect .iram0.text as input into it, avoiding
the problem.
Fix this by renaming the ".flash.text" output section to
".text" across all Espressif SoC linker scripts. The
section name is internal to the linker script; the runtime
loader uses linker-generated symbols (_image_irom_start,
etc.), not section names. This change is transparent to
the boot path, flash image generation, and MMU mapping.
Affected SoCs: ESP32, ESP32-S2, ESP32-S3, ESP32-C2,
ESP32-C3, ESP32-C5, ESP32-C6, ESP32-H2.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Define the HCI node in the SoC series' dtsi.
- Adjust main thread stack sizes and buffer counts required for
Bluetooth operation.
- Enable meta-irq to configure the bee-bt-controller thread as a
meta-irq thread.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Implement the custom stack guard using the Andes StackSafe hardware
stack protection. It triggers an exception on stack overflow when the
stack pointer exceeds the configured limit.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Qemu includes support for the OpenRISC 1000 CPU architecture. This patch
adds a Zephyr SoC definition which enables usage of this feature.
The SoC definition closely mirrors the Qemu MIPS Malta SoC definition.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
Compiling for NVL/NVL-S reports:
warning: implicit declaration of function 'intel_adsp_clock_soft_off_exit'
Because the ace4 version of adsp_power.h is missing the declaration of
intel_adsp_clock_soft_off_exit().
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Use new Kconfig preprocessor helper to compute CONFIG_NUM_IRQS during build
instead of hardcoding it based on product Reference Manual
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Make the build to fail when CONFIG_TRUSTED_NONSECURE is enabled and
the DT files do not provide the non-secure memory address ranges.
The test only checks pinctrl node which should be enough to ensure
other the right peripherals address range is applied.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
