The fifth HSEM (#define is equal to 4 due to zero-indexing) is used on
STM32H7 to synchronize the two cores. Update the comment above the SEMID
define to reflect this alternate usage. Also remove the associated define
CFG_HW_ENTRY_STOP_MODE_MASK_SEMID, which is unused.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Reorder the HSEM semaphore ID definitions to be sorted by ascending value.
The dummy defines are also changed to be sorted in the same order. The
definitions for STM32MP1 are already in an order that follows this order
so they don't need to be changed.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add MPS4 pinctrl support by referring to
`mps4/common/partition/platform_base_address.h`
from TF-M's main branch.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Add initial support for the MPS4 Corstone-320 platform, including board
and SoC definitions. This platform features a Cortex-M85 CPU with an
Ethos-U85 NPU and runs in simulation using the FVP_Corstone_SSE-320
Fixed Virtual Platform.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Adds skeleton dtsi for u5f9 for u5g9 to inherit from
Moves the peripheral nodes into dtsi's that actually has the peripheral
and includes them for SoC's higher in the series where applicable.
signed-off-by: Harris Tomy <harristomy@gmail.com>
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Add select for GEN_HANDLERS to use the more efficient
generated interrupt handlers.
Add select for HIFI3, which are the SIMD related registers.
Signed-off-by: Mike J. Chen <mjchen@google.com>
This patch makes cosmetic changes to cavs/power.c by updating comments to
Doxygen style, fixing typos.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch makes cosmetic changes to ace/power.c by updating comments to
Doxygen style, fixing typos, and removing an extraneous character for
improved readability and consistency.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch enhances the power management capabilities of the Intel ADSP
by ensuring that power gating states are appropriately managed based on
core activity. It prevents the primary core from entering power gating
if secondary cores are active and re-enables power gating when all
secondary cores are off, using pm_policy_state_lock_get and
pm_policy_state_lock_put functions.
The Sound Open Firmware (SOF) project currently uses a custom power
management policy to achieve these effects. With this patch, the default
power management policy can be utilized, allowing the option to disable
the custom policy while maintaining system reliability and performance
across different core states.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Renamed two functions and a macro to use more generic names,
removing chip-specific identifiers.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Move register definitions from chip_chipregs.h into espi_it8xxx2.c to
make the driver more adaptable to different SoCs.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This patch add i.MX 943 soc support.
The i.MX 943 applications processors integrate up to four Arm Cortex-A55
cores and supports functional safety with built-in 2x Arm Cortex -M33 and
-M7 cores which can be configured as a safety island. Optimizing
performance and power efficiency for Industrial, IoT and automotive
devices, i.MX 943 processors are built with NXP’s innovative Energy Flex
architecture.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Avoid the individual `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` for each
board instead to referencing the dt value.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Commit `2844850` inadvertently omitted
`SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_160MHZ`. This commit restores
the missing flag to ensure proper SOC clock setup.
Additionally, `SL_SI91X_CUSTOM_FEAT_LIMIT_PACKETS_PER_STA` is now enabled
as the default setting, aligning with the driver Kconfig.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
When building with clang and CONFIG_LTO, clang warns:
soc/nuvoton/npcx/common/pinctrl_soc.h:141:4: error: field flags within
'struct npcx_pinctrl' is less aligned than 'struct (unnamed struct at
soc/nuvoton/npcx/common/./pinctrl_soc.h:128:2)' and is usually due to
'struct npcx_pinctrl' being packed, which can lead to unaligned accesses
[-Werror,-Wunaligned-access]
} flags;
^
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
This commit reflects a difference between FE310-G000 and FE310-G002 SoCs,
since only the latter supports PMP. The result of that is the split of the
HiFive1 board into two separate targets, since the HWMv2 right now assumes
that board revisions share the same SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Use flash_k4 driver for internal flash instead of ROM API driver. One
benefit is the flash program phrase size decreases from 128 Bytes to 16
Bytes. 16 Byte phrases enables this SOC to leverage the Zephyr NVS
subsystem, and the MCUboot swap mode.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Conflicts:
west.yml
This fixes a regression introduced in c31640239c where all regions
except Flash and RAM where left unmapped. Before introducing region
0 that prevents speculative access to the entire memory space, we
were relying on the architectural background map to access them.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This is a fix for issue #90426 .
Marking __kinetis_flash_config with __used attribute prevents
unwanted deletion when compiling with LTO.
Signed-off-by: Matthieu Speder <mspeder@users.sourceforge.net>
- Adds a flash runner configuration for mimxrt1052 and mimxrt1062,
used for sysbuild multi-image projects, mainly for MCU-boot.
- Avoid unwanted multiple erases and resets.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
On RW, normal configuration has all clock generators gated in PM2.
Only the LPOSC is available for main clock source since it is a low
power clock.
Many of the peripherals on the chip are still "on" and do need a
main clock source in order to be effective as wakeup sources
to the chip as intended. So we should make this switch for PM2
specifically in order to achieve desired wakeup capabilities.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
PMU related functions need to be located in IRAM when sleep
process is triggered, as cache is disabled past a certain point
in the execution of the sleep process.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
add uhc related items to dts.
add clock initialization
add BM4 if CONFIG_USB_UHC_NXP_KHCI is enabled
add pin mux
update board related CMakeLists.txt
update sdk-ng CMake to include NXP controller drivers
update west.yml to contain the hal_nxp pr
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
espi: add espi peripheral channel HOST_CMD driver for rts5912
Unlike other chips using IO port 0x800-0x8ff, we utilize shared memory to
transfer host command parameters. The AP firmware must have corresponding
settings for this configuration.
Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
Due to erratum ERR011573, speculative accesses might be performed
to normal memory unmapped in the MPU. This can be avoided by using
MPU region 0 to cover all unmapped memory and make this region
execute-never and inaccessible.
Fixes#89852
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
1. Add it51526bw SoC variant to it51xxx SoC series.
2. Create the .dtsi file with adjusted flash size for 512Kb (default = 1M).
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The ROM bootloader has the option to boot from external QSPI flash on
the FlexSPI instead of internal flash. Adds
CONFIG_NXP_FLEXSPI_BOOT_HEADER to include the FlexSPI boot ROM header
in the image.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Add Set_WP function to set SPI flash WP line to low
Add Get_WP function to obtain status of the SPI flash WP line
Signed-off-by: Benson Huang <benson7633769@gmail.com>
Add code for sama7g5 Generic Clock, Main Clock, Main System Bus Clock,
Peripheral Clock, Programmable Clock and PLL Clock.
Signed-off-by: Tony Han <tony.han@microchip.com>
To simplify usage add dependecy to MAX32_ON_ENTER_CPU_IDLE_HOOK
If CONFIG_PM not defined set to to y as current,
If CONFIG_PM defined not set it
If user set CONFIG_PM not need to disable
MAX32_ON_ENTER_CPU_IDLE_HOOK anymore
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
