Commit graph

5973 commits

Author SHA1 Message Date
Mathieu Choplain
86c5135982 soc: st: stm32: hsem: update description for fifth HSEM
The fifth HSEM (#define is equal to 4 due to zero-indexing) is used on
STM32H7 to synchronize the two cores. Update the comment above the SEMID
define to reflect this alternate usage. Also remove the associated define
CFG_HW_ENTRY_STOP_MODE_MASK_SEMID, which is unused.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-10 12:08:35 +02:00
Mathieu Choplain
97e2dd28b3 soc: st: stm32: hsem: sort hardware semaphore IDs by value
Reorder the HSEM semaphore ID definitions to be sorted by ascending value.
The dummy defines are also changed to be sorted in the same order. The
definitions for STM32MP1 are already in an order that follows this order
so they don't need to be changed.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-10 12:08:35 +02:00
Adam Mitchell
dcf94aaf7b dts: arm: st: h7: Add support for STM32H742
Adds base Devicetree files for H742Xi/g variants

Signed-off-by: Adam Mitchell <adam.mitchell@brillpower.com>
2025-06-10 08:51:45 +02:00
Sudan Landge
5a3c4941a2 pinctrl: add support for mps4
Add MPS4 pinctrl support by referring to
`mps4/common/partition/platform_base_address.h`
from TF-M's main branch.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2025-06-09 14:35:12 -07:00
Sudan Landge
d1e830fe0d boards: arm: add support for MPS4 Corstone-320
Add initial support for the MPS4 Corstone-320 platform, including board
and SoC definitions. This platform features a Cortex-M85 CPU with an
Ethos-U85 NPU and runs in simulation using the FVP_Corstone_SSE-320
Fixed Virtual Platform.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2025-06-09 14:35:12 -07:00
Harris Tomy
d280d89214 dts/kconfig: stm32u5: add f9 and clean up dts node locations
Adds skeleton dtsi for u5f9 for u5g9 to inherit from

Moves the peripheral nodes into dtsi's that actually has the peripheral
and includes them for SoC's higher in the series where applicable.

signed-off-by: Harris Tomy <harristomy@gmail.com>
2025-06-09 14:26:11 -07:00
Phuc Pham
adeaad5e6f soc: renesas: Add initial support for Renesas RZ/G2UL
Add initial support for Renesas RZ/G2UL

Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
2025-06-09 10:26:45 +01:00
Lin Yu-Cheng
b2e13bd6c3 driver: crypto: add crypto driver for rts5912
Add crypto driver for Realtek rts5912

Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
2025-06-07 13:29:07 +01:00
Henrik Lindblom
24b4ce189f drivers: stm32: dma: fix external dcache support
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.

In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.

The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.

Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
2025-06-06 10:19:58 +02:00
Axel Le Bourhis
3c6a3826ad soc: nxp: rw: adjust ACL bt_conn_tx contexts to match Controller's
RW61x's controller uses 8 ACL packets, adjust `BT_BUF_ACL_TX_COUNT`
to match it.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
2025-06-06 08:45:33 +02:00
Axel Le Bourhis
df2dac7a68 soc: nxp: mcxw: adjust ACL bt_conn_tx contexts to match Controller's
MCXW7x's controller uses 12 ACL packets, adjust `BT_BUF_ACL_TX_COUNT`
to match it.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
2025-06-06 08:45:33 +02:00
Mike J. Chen
2923504780 soc: nxp: imxrt: imxrt5xx: add Fusion F1 DSP selects
Add select for GEN_HANDLERS to use the more efficient
generated interrupt handlers.

Add select for HIFI3, which are the SIMD related registers.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2025-06-06 08:43:52 +02:00
Tomasz Leman
e70765391f soc: intel_adsp: Fix typo in cavs/power.c comment
This patch makes cosmetic changes to cavs/power.c by updating comments to
Doxygen style, fixing typos.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2025-06-06 08:43:15 +02:00
Tomasz Leman
c26b0767f2 soc: intel_adsp: Update comment style and fix typos
This patch makes cosmetic changes to ace/power.c by updating comments to
Doxygen style, fixing typos, and removing an extraneous character for
improved readability and consistency.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2025-06-06 08:43:15 +02:00
Tomasz Leman
fbafada9b6 soc: intel_adsp: Manage power gating based on core activity
This patch enhances the power management capabilities of the Intel ADSP
by ensuring that power gating states are appropriately managed based on
core activity. It prevents the primary core from entering power gating
if secondary cores are active and re-enables power gating when all
secondary cores are off, using pm_policy_state_lock_get and
pm_policy_state_lock_put functions.

The Sound Open Firmware (SOF) project currently uses a custom power
management policy to achieve these effects. With this patch, the default
power management policy can be utilized, allowing the option to disable
the custom policy while maintaining system reliability and performance
across different core states.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2025-06-06 08:43:15 +02:00
Tim Lin
a8e467cf2d soc/ite/ec/common: Rename functions to use generic names
Renamed two functions and a macro to use more generic names,
removing chip-specific identifiers.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-06-05 09:34:23 +02:00
Tim Lin
4aaa0f8547 soc/ite/ec: it51xxx: Add condition to select the mode based on CONFIG_ESPI
If CONFIG_ESPI is defined, use 0xA4 (eSPI mode).
Otherwise, use 0xA5 (LPC mode).

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-06-05 09:34:23 +02:00
Tim Lin
5f502499e9 drivers/espi: ite: Refactor register defines into .c for SoC flexibility
Move register definitions from chip_chipregs.h into espi_it8xxx2.c to
make the driver more adaptable to different SoCs.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-06-05 09:34:23 +02:00
Jiafei Pan
c0aee5c224 soc: imx943: add imx943 soc support
This patch add i.MX 943 soc support.

The i.MX 943 applications processors integrate up to four Arm Cortex-A55
cores and supports functional safety with built-in 2x Arm Cortex -M33 and
-M7 cores which can be configured as a safety island. Optimizing
performance and power efficiency for Industrial, IoT and automotive
devices, i.MX 943 processors are built with NXP’s innovative Energy Flex
architecture.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-04 15:51:36 -04:00
TOKITA Hiroshi
a76ed223d5 soc: rpi_pico: Set the default SYS_CLOCK_HW_CYCLES_PER_SEC from dt
Avoid the individual `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` for each
board instead to referencing the dt value.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2025-06-04 15:50:44 -04:00
Arunmani Alagarsamy
112c8e6939 soc: silabs: siwg917: Restore missing config and update default settings
Commit `2844850` inadvertently omitted
`SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_160MHZ`. This commit restores
the missing flag to ensure proper SOC clock setup.

Additionally, `SL_SI91X_CUSTOM_FEAT_LIMIT_PACKETS_PER_STA` is now enabled
as the default setting, aligning with the driver Kconfig.

Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
2025-06-04 17:04:24 +02:00
Marcio Ribeiro
77c350c149 soc: esp32: virtual e-fuses support
Adds support for virtual e-fuses on esp32 socs

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-06-04 17:00:20 +02:00
Tien Nguyen
9970d21348 soc: renesas: Add initial support for Renesas RZ/V2H
Add initial support for Renesas RZ/V2H

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
2025-06-04 17:00:01 +02:00
Jiafei Pan
e624cffd9b soc: imx: disable dcache until mmu is enabled during booting
Enable CONFIG_ARM64_BOOT_DISABLE_DCACHE for i.MX Cortex-A platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-04 16:59:43 +02:00
Tom Hughes
94edd97233 soc: npcx: Add __packed to flags struct in npcx_pinctrl
When building with clang and CONFIG_LTO, clang warns:

soc/nuvoton/npcx/common/pinctrl_soc.h:141:4: error: field flags within
'struct npcx_pinctrl' is less aligned than 'struct (unnamed struct at
soc/nuvoton/npcx/common/./pinctrl_soc.h:128:2)' and is usually due to
'struct npcx_pinctrl' being packed, which can lead to unaligned accesses
[-Werror,-Wunaligned-access]
         } flags;
           ^

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
2025-06-02 22:35:14 -04:00
Filip Kokosinski
07e4ba4240 soc/sifive: differentiate between FE310-G000 and FE310-G002
This commit reflects a difference between FE310-G000 and FE310-G002 SoCs,
since only the latter supports PMP. The result of that is the split of the
HiFive1 board into two separate targets, since the HWMv2 right now assumes
that board revisions share the same SoC.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2025-06-02 17:37:32 +02:00
Adam Kondraciuk
fa55c30e46 soc: nordic_nrf: add support for TDM
Add Kconfig options for TDM130 and TDM131.

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
2025-06-02 13:29:10 +02:00
Derek Snell
1fd24fbdbb soc: nxp: mcx: MCXNx4x: update SOC to use flash_k4 driver
Use flash_k4 driver for internal flash instead of ROM API driver.  One
benefit is the flash program phrase size decreases from 128 Bytes to 16
Bytes.  16 Byte phrases enables this SOC to leverage the Zephyr NVS
subsystem, and the MCUboot swap mode.

Signed-off-by: Derek Snell <derek.snell@nxp.com>

Conflicts:
	west.yml
2025-05-31 05:57:40 -04:00
Manuel Argüelles
6681f8d342 soc: nxp: s32k3: configure missing mpu regions
This fixes a regression introduced in c31640239c where all regions
except Flash and RAM where left unmapped. Before introducing region
0 that prevents speculative access to the entire memory space, we
were relying on the architectural background map to access them.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2025-05-31 05:57:18 -04:00
Matthieu Speder
66d90e7782 soc: nxp_kinetis: Mark __kinetis_flash_config with __used attribute
This is a fix for issue #90426 .
Marking __kinetis_flash_config  with __used attribute prevents
unwanted deletion when compiling with LTO.

Signed-off-by: Matthieu Speder <mspeder@users.sourceforge.net>
2025-05-31 03:37:20 +02:00
Andrej Butok
eb5014f7a3 soc: imxrt: add mimxrt1052/1062 flashing configuration
- Adds a flash runner configuration for mimxrt1052 and mimxrt1062,
  used for sysbuild multi-image projects, mainly for MCU-boot.
- Avoid unwanted multiple erases and resets.

Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
2025-05-31 03:36:24 +02:00
Declan Snyder
4598c18754 soc: rw: Switch main clock on PM2 to LPOSC
On RW, normal configuration has all clock generators gated in PM2.
Only the LPOSC is available for main clock source since it is a low
power clock.

Many of the peripherals on the chip are still "on" and do need a
main clock source in order to be effective as wakeup sources
to the chip as intended. So we should make this switch for PM2
specifically in order to achieve desired wakeup capabilities.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-05-30 19:40:11 +02:00
Raffael Rostagno
588c2e66e9 soc: esp32c6: Fix sleep routine
PMU related functions need to be located in IRAM when sleep
process is triggered, as cache is disabled past a certain point
in the execution of the sleep process.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-05-30 16:34:48 +02:00
Mark Wang
a8796ca6ee boards: nxp: add uhc support for frdm_k22f, rt1060, lpc55s69 and lpc55s28
add uhc related items to dts.
add clock initialization
add BM4 if CONFIG_USB_UHC_NXP_KHCI is enabled
add pin mux
update board related CMakeLists.txt
update sdk-ng CMake to include NXP controller drivers
update west.yml to contain the hal_nxp pr

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2025-05-30 16:34:41 +02:00
jhan bo chao
da767376ca driver: espi: add espi peripheral channel 8042_KBC driver for rts5912
add espi peripheral channel 8042_KBC driver for rts5912

Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
2025-05-29 23:25:27 +02:00
jhan bo chao
8ceb0d0f11 driver: espi: add espi peripheral channel HOST_CMD driver for rts5912
espi: add espi peripheral channel HOST_CMD driver for rts5912

Unlike other chips using IO port 0x800-0x8ff, we utilize shared memory to
transfer host command parameters. The AP firmware must have corresponding
settings for this configuration.

Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
2025-05-29 23:25:27 +02:00
jhan bo chao
1bc30251a6 driver: espi: add espi peripheral channel port 80 driver for rts5912
add espi peripheral channel port 80 driver for rts5912

Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
2025-05-29 23:25:27 +02:00
jhan bo chao
537791facf driver: espi: add espi driver for rts5912
add espi driver for rts5912

Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
2025-05-29 23:25:27 +02:00
Manuel Argüelles
c31640239c soc: nxp: s32k3: fix erratum ERR011573
Due to erratum ERR011573, speculative accesses might be performed
to normal memory unmapped in the MPU. This can be avoided by using
MPU region 0 to cover all unmapped memory and make this region
execute-never and inaccessible.

Fixes #89852

Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2025-05-29 20:17:14 +02:00
Marcin Szymczyk
b5ca5b4147 soc: nordic: nrf54l: fix ordering in Kconfig
Application cores should be next to eachother.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2025-05-29 15:16:52 +01:00
Tim Lin
022043c6f6 soc/ite/ec: it51xxx: Add a new SoC variant it51526bw
1. Add it51526bw SoC variant to it51xxx SoC series.
2. Create the .dtsi file with adjusted flash size for 512Kb (default = 1M).

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-05-29 08:42:08 +02:00
Derek Snell
7c77d0ea48 soc: nxp: MCXNx4x: enable booting from QSPI flash
The ROM bootloader has the option to boot from external QSPI flash on
the FlexSPI instead of internal flash.  Adds
CONFIG_NXP_FLEXSPI_BOOT_HEADER to include the FlexSPI boot ROM header
in the image.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2025-05-28 21:29:29 +02:00
Sreeram Tatapudi
b3067bde98 board: infineon: add XMC7200 Eval board support
- Support for kit_xmc72_evk

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Signed-off-by: Yurii Lozynskyi <yurii.lozynskyi@infineon.com>
2025-05-28 21:29:20 +02:00
Benson Huang
3e8ec3aaf2 driver: flash: Add Set/ Get write protect function
Add Set_WP function to set SPI flash WP line to low
Add Get_WP function to obtain status of the SPI flash WP line

Signed-off-by: Benson Huang <benson7633769@gmail.com>
2025-05-28 08:14:27 +02:00
Tony Han
21da37b400 soc: microchip: sam: add code for sama7g5 clocks
Add code for sama7g5 Generic Clock, Main Clock, Main System Bus Clock,
Peripheral Clock, Programmable Clock and PLL Clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-05-28 08:14:08 +02:00
Tony Han
c7efdb9c73 soc: microchip: add new soc sama7g54
Product URL: https://www.microchip.com/en-us/product/SAMA7G54

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-05-28 08:14:08 +02:00
Sadik Ozer
4e858066bc soc: adi: max32: Add dependency to idle cpu hook
To simplify usage add dependecy to MAX32_ON_ENTER_CPU_IDLE_HOOK
If CONFIG_PM not defined set to to y as current,
If CONFIG_PM defined not set it
If user set CONFIG_PM not need to disable
MAX32_ON_ENTER_CPU_IDLE_HOOK anymore

Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2025-05-28 01:46:50 +02:00
Sadik Ozer
9b7927f2a3 soc: arm: adi: max32: Add power management feature
This commit add power.c file that provides device goes to low power modes

Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2025-05-28 01:46:50 +02:00
David Leach
c52bea0a6d soc: imxrt: remove MEMC config selection
MEMC no longer needs to be default y on RT builds.

Fixes #89782

Signed-off-by: David Leach <david.leach@nxp.com>
2025-05-27 16:44:37 +02:00
Muzaffar Ahmed
9600995af8 drivers: wifi: siwx91x: Fix NWP bootup assert
Fixed the assert related to AP mode / Hidden SSID in NWP bootup

Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
2025-05-27 11:51:17 +02:00