Deprecate the m33 and hazard3 cpucluster's Kconfigs and replace with
m33_0 and hazard3_0 cpuclusters. The m33 cpucluster will be removed
from the soc.yml in a later release to avoid breaking downstream boards.
Signed-off-by: Andrew Fantino <fantino@qti.qualcomm.com>
The rp2350 has 2 cores that can independently configured to use either
the Cortex-M33 or the Hazard3 cpu. The current m33 and hazard3 cpu
clusters do not conform to the hardware model v2.
The m33 and hazard3 cpucluster's Kconfigs will be deprecated and
replaced with m33_0 and hazard3_0 cpuclusters.
The m33 cpucluster will be removed from the soc.yml in a later release
to avoid breaking downstream boards.
Signed-off-by: Andrew Fantino <fantino@qti.qualcomm.com>
MCUboot's soc_early_init_hook() calls CLOCK_DeinitTddrRefClk() even when
not using Ethernet, which clears the TDDR_PDB bit and powers down the
TDDR PLL. When the application later boots and re-initializes Ethernet,
the NXP SDK's clock enable functions re-enable the peripheral clock
outputs but never re-set the PLL power-down-bypass bit.
Add an explicit write of the TDDR_PDB bit to PLL_CTRL before resetting
the ENET peripherals. This is a no-op on cold boot since the bit is
already set, but fixes Ethernet after any scenario where
CLOCK_DeinitTddrRefClk() was called (sysbuild).
Fixes: zephyrproject-rtos/zephyr#108399
Signed-off-by: Mike Szczys <michael.szczys@canonical.com>
Add the STM32MP135D device variant to the STM32MP13 SoC metadata and
Kconfig selection.
The STM32Cube MP13 HAL already provides the STM32MP135Dxx device header,
so this enables boards using that variant to select the matching CMSIS
device definition.
Signed-off-by: Aleksandr Dobkin <alex@dobk.in>
Assisted-by: ChatGPT:gpt-5.6-sol
XIP is a 'select' on SOC_SERIES_RP2040, so an application cannot turn it
off to be linked to run from RAM. MCUboot's RAM load mode sets
CONFIG_XIP=n for the application it boots, which ends up being silently
discarded. Nothing about the RP2040 requires execute in place, and XIP is
already 'imply' on SOC_SERIES_RP2350, changed from a 'select' in #97010.
An 'imply' still defaults XIP on, so existing configurations are
unaffected. Verified by building for rpi_pico under sysbuild with
MCUboot RAM load.
Signed-off-by: James Smith <james@loopj.com>
DYNAMIC_THREAD are enabled in case of using the DMA2D.
DYNAMIC_THREAD_POOL_SIZE defines the amount of stacks
which can be allocated dynamically. 1 is enough in case
of only using the DMA2D but is not enough when enabling as
well the GPU2D for which it should be increased to 2.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
dma2d is an HW block part of the SOC and as such should have its
DT node with status okay. However its usage depends on the
application request which can be use via the Kconfig
LV_USE_DRAW_DMA2D.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Update the Kconfig of LVGL and STM32 common in order to
enable the GPU2D HW whenever the NEMAGFX is necessary within
LVGL. Until now the GPU2D driver was always enabled as soon
as the gpu2d node is okay within the DT, leaving a potentially
unnecessary driver compiled in even if un-necessary.
Keep the STM32_NEOCHROM_GPU2D disabled by default even if
the node is okay within the DT and make LVGL select it whenever
LVGL is compiled with the NEMAGFX support.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
This patch adds nxp_crypto_hal components and enables
PSA crypto HW acceleration for MCXA, MCXN and RW6xx family devices
Also increasing default stack size when SGI_PKC enabled.
test/crypto/psa must add boards config to override main prj.conf
Signed-off-by: Vit Solcik <vit.solcik@nxp.com>
Add a driver for the ESP32-P4 pixel processing accelerator, which
offloads solid fills, alpha blends and scale-rotate-mirror
operations from the processor through its 2D DMA channels.
Blocking and non-blocking transactions are both supported, and a
request the driver cannot express is rejected rather than run
with the wrong geometry.
The registers and the interrupt come from the devicetree node, so
the accelerator is described as hardware while the Kconfig option
only decides whether the code is built.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Program the Trusted Resource Domain Controller (TRDC) to grant the host
CM33 access to every peripheral that device tree enables. Without this,
a future TRDC-locked Sentinel image would fault on the first access to
any LPUART, GPIO, or NBU register and prevent the kernel from booting.
TRDC access control is a property of the MCXW72 SoC, not of any board,
so run it from soc_early_init_hook() rather than a board hook. The MBC
and slave-memory layout differs per NPI, so the mcxw72_trdc.c source,
its soc.h prototype, and its call are guarded by CONFIG_SOC_MCXW727C.
This keeps the shared mcxw7xx soc.c untouched for MCXW70/MCXW71 and lets
every MCXW72 board (frdm_mcxw72, mcxw72_evk) inherit the configuration.
The fsl_trdc HAL driver it uses is pulled in by NXP_TRDC, defaulted on
for SOC_MCXW727C.
The NBU map at 0x4880_0000..0x489F_FFFF (Radio Flash/IFR, NBU CIU2,
FRO192M, RF FMU/CMC, LPTPM2, NBU SMU2) is guarded by the region checker
MRC0, not by an MBC, so add an MRC0 full-access region for it in
addition to the MBC block grants. Without it the host CM33 cannot reach
the NBU-boot and SMU2 shared-memory registers, which the MBC descriptors
alone never covered.
Grant the peripheral windows to the CM33 host domain only instead of to
all three domains, so the per-domain tables keep their intended
separation. The DAC then assigns every master (CM33, DMA3, data stream
buffer, Radio NBU) a domain, but preserves any valid boot-ROM (Sentinel)
assignment already present in the MDA registers and applies a fallback
DID only otherwise. The host grant domain is likewise read back from the
CM33 MDA register so the grants follow whatever domain the ROM chose.
Document in soc.c that soc_reset_hook and SystemInit() run before this
hook and already access SPC0 and WDOG0, so a TRDC-locked Sentinel must
pre-grant the minimal boot blocks (code flash, ECC TCM banks, SPC0,
WDOG0) before starting this image; the hook then opens the full
peripheral set the kernel and enabled drivers need.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Rename the TRDC HAL component gating symbols from TRDC_MCUX_TRDC and
TRDC_MCUX_TRDC_1 to NXP_TRDC and NXP_TRDC_1, and define them centrally
in modules/hal_nxp/mcux/Kconfig.mcux alongside the other MCUX_* driver
options (each with a help block, per the Kconfig style guide).
Migrate the existing users to the new symbols so no platform loses the
driver.trdc / driver.trdc_1 HAL component:
- imxrt118x: TRDC_MCUX_TRDC -> NXP_TRDC
- imx93: TRDC_MCUX_TRDC_1 -> NXP_TRDC_1
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Register MCXA536/537/556/557/566/567/577/457/456/287/286 under the
existing mcxaxx7 series in Kconfig.soc.
Add the same parts to soc.yml's mcxaxx7 family and to the --erase/
--reset runner qualifier groups, so `west flash`/`west debug`/`west
erase`/`west reset` resolve correctly for each new SoC.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
The ECC (P256 / ECDH) operations for BLE on STM32WBA devices are
based on the PKA Controller module (pka_ctrl), which requires
a PKA DTS node, instead of the legacy BLE PKA module.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Assisted-by: claude:haiku-4.5
Add the clock controller and syscon to the Hydrogen platform.
Enable both by default and reduce the syscon priority to load
this driver before the clock controller.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
ICBMSG IPC service backend runs receive callback in the interrupt
context and when Ironside is used then GPPI connection allocation
and freeing requires communication with Ironside which is only
supported in the thread context. Defer connection allocation and
freeing to the thread context (system work queue).
Assisted-by: Claude:opus-5
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Fixes various issues with Kconfigs, including:
- Redundent `default n` on bools
- Not select deprecated on supposed deprecated symbols
- Using the wrong indentation
- Not having [DEPRECATED] in the prompt, or not having it at the
end
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Going into light sleep runs a long call chain on the idle thread's
stack, and sleep code in it needs at least 680 bytes. The idle thread
gets 512 by default on RISC-V, so it overflows every time the system
sleeps: on ESP32-C5 the PMP stack guard catches this and the board
resets in a loop, elsewhere it silently overwrites whatever sits
below the stack.
Raise the default to 2048 bytes when PM is enabled.
Assisted-by: Claude:opus-5
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
For MAX32657 revisions earlier than A3, ROM will use 8 bytes of SRAM
at address 0x3000a558. Use the stack to push those 8 bytes, then pop
once returned from S2RAM. Make sure we're not pushing to those 8 bytes.
Add dependency TRUSTED_EXECUTION_SECURE as a dependency for PM_S2RAM.
Signed-off-by: Kevin Gillespie <Kevin.Gillespie@analog.com>
When RTC is activated in the DT, configure it's register region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
The MMU region for the PMC used the uppercase label PMC instead of
the correct lowercase label pmc, causing DT_NODE_HAS_STATUS_OKAY()
to silently evaluate to false and the PMC region to be omitted from
the MMU table.
There is no runtime impact because the PMC is not accessed after the
MMU is configured.
Fixes: 0443254b69 ("soc: microchip: sam: add new SoC sam5d2")
Signed-off-by: Tony Han <tony.han@microchip.com>
The host can't go to sleep until the NWP is initialized. So,
siwx91x_power_init() adds a PS4 requirement and this requirement is
removed from siwx91x_nwp_apply_power_profile().
However, this is confusing. The host PM policy is related to the NWP
initialization and is not related to the RF power profile. The current
code tends to mix both.
In addition, siwx91x_nwp_apply_power_profile() is called each time the
user changes the WiFi PS parameters. So,
sl_si91x_power_manager_remove_ps_requirement() is called again on a
requirement already removed. The power manager rejects the call with
SL_STATUS_INVALID_PARAMETER, which is silently ignored.
Relocate this call in siwx91x_nwp_init(), once the NWP is initialized.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Assisted-by: Claude:fable-5
Until now, the wifi power save request was discarded if CONFIG_PM was not
set. It does not make sense since CONFIG_PM only impacts the host CPU (and
devices if we consider CONFIG_PM_DEVICE). The RF power profile of the NWP
is independent from the host power management.
Probably the condition was only here to avoid the call to
sl_si91x_power_manager_remove_ps_requirement() when CONFIG_PM is not set.
While revisiting the feature, we can notice data->power_profile was only
initialized at boot and never changed afterward. So, it has nothing to do
in the data structure. It provided the default profile applied during the
NWP initialization: ASSOCIATED_POWER_SAVE when WiFi or BLE is enabled,
DEEP_SLEEP_WITH_RAM_RETENTION otherwise. Hardcode these cases in
siwx91x_nwp_apply_power_profile().
The default WiFi profile is now HIGH_PERFORMANCE instead of
ASSOCIATED_POWER_SAVE. This is not a functional change: the WiFi driver
applies HIGH_PERFORMANCE on every association unless the user has
explicitly enabled the power save, and ASSOCIATED_POWER_SAVE has no
effect until the interface is associated. Power save has to be requested
explicitly by the user, whether CONFIG_PM is set or not.
The only observable difference is when CONFIG_PM is set with both WiFi
and BLE enabled: the coex profile is HIGH_PERFORMANCE from the boot,
while it was ASSOCIATED_POWER_SAVE until the first WiFi association. The
BLE power save now consistently follows the WiFi power save setting, as
imposed by the WiseConnect coex profile table.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Assisted-by: Claude:fable-5
This commit aims to fix a HCI controller timeout assertion at boot when
mcxw70 platform is used with vendor radio implementation.
This behaviour is fixed by increasing the default OpenThread init
priority, 40, to match the IEEE driver one, 80.
Signed-off-by: Cristian Bulacu <cristian.bulacu@nxp.com>
Add devicetree sources, Kconfig, CMakeLists, and early-init source
for the Infineon PSOC4000T SoC series (CY8C4046LQI-T452), an
Arm Cortex-M0+ MCU with 64 KB flash and 8 KB SRAM.
Signed-off-by: Yurii Lozynskyi <Yurii.Lozynskyi-EE@infineon.com>
Gets the clock speed from dts rather than a magic number, and
fixes invalid stack size configuration
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The UART's FIFO-mode receive interrupts do not work on this SoC: with
FIFOs enabled, neither the receive trigger level nor the character
timeout raises an interrupt, so received data sits in the FIFO
unnoticed. Default to 16450 mode, where the received data available
interrupt fires for every character.
Signed-off-by: Anuj Deshpande <anuj@makerville.io>
Add support for the C-DAC THEJAS32 SoC, based on the VEGA ET1031 32-bit
(RV32IM) single-core, in-order RISC-V processor developed under India's
Digital India RISC-V (DIR-V) programme.
The image is loaded into and executed from the 256 KB internal SRAM,
which is mapped at 0x00200000, so execute-in-place is not used. The
kernel system clock is driven by the CLINT machine timer.
THEJAS32 follows the RISC-V privileged specification for trap handling
but uses a custom (non-PLIC) interrupt controller, so the SoC does not
select RISCV_PRIVILEGED. Instead it provides its own reset entry, machine
trap acknowledge and interrupt-management code that routes second-level
interrupts to the THEJAS32 interrupt controller driver and first-level
interrupts to the mie CSR.
The memory map and register definitions were cross-checked against the
C-DAC VEGA board support package.
Signed-off-by: Anuj Deshpande <anuj@makerville.io>
MCXN unconditionally sets CMC DBGCTL[SOD] on every low power entry, which
shuts the debug logic off while the core is asleep. That is the right
default for power measurements, but it also drops the debug probe
connection, so a suspended target cannot be halted, inspected or
reflashed without a reset.
Add SOC_FAMILY_MCXN_DEBUG_IN_LOW_POWER to pick the other side of the
trade-off. It defaults to n, so the existing behavior is unchanged.
MCXA and MCXN are separate SoC families, each with its own power.c, so
the option is defined per family rather than once for the whole mcx
directory.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
MCXA unconditionally sets CMC DBGCTL[SOD] on every low power entry, which
shuts the debug logic off while the core is asleep. That is the right
default for power measurements, but it also drops the debug probe
connection, so a suspended target cannot be halted, inspected or
reflashed without a reset.
Add SOC_FAMILY_MCXA_DEBUG_IN_LOW_POWER to pick the other side of the
trade-off. It defaults to n, so the existing behavior is unchanged.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Replaced SOC dependent kconfigs CONFIG_SOC_SERIES_NRF54H,
CONFIG_SOC_SERIES_NRF92 with feature oriented
CONFIG_HAS_MULTI_OPTION_CLOCKS, in clock related drivers.
Signed-off-by: Michal Frankiewicz <michal.frankiewicz@nordicsemi.no>
Add a dedicated clock_tree target and Python report script to dump resolved
SiWx91x clock topology from EDT for DTS review and debug.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Assisted-by: Cursor:Grok 4.5
Add the "silabs clocks" shell command and related build/test wiring to
inspect clock status and rate during bring-up and PM validation.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Assisted-by: Cursor:Grok 4.5
This commit enables the new clock managers by switching the device
tree to use the new bindings. It also moves some initialization code
from the old clock manager to soc_early_init_hook() since some clocks
configuration needs to be done before the clock drivers are initialized.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Introduce dedicated clock-control drivers for HP, ULP and AON domains
plus the shared helper API used by consumers, and refresh helper
documentation to match the current DT wiring and ownership model.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Make the Deep Power Down modes reachable from the standard API. Implement
z_sys_poweroff() on top of power_enter_deep_power_down(), compile it under
CONFIG_POWEROFF and select HAS_POWEROFF on both cm33 cores.
Add a "System power-off mode" choice so a board can pick Deep Power Down,
which keeps the VDD1V8_AON island alive, or Full Deep Power Down, which
turns off VDD1V8_PMC as well and leaves wake to the always-on RTC path.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Layer the poweroff modes onto the shared sequence. Both domains gain DPD
and FDPD power_mode_desc entries -- an empty request, so every resource
is voted down, and low_power_mode set to the one-way LP_DPD / LP_FDPD --
and a power_enter_deep_power_down() entry point.
power_commit() asserts the matching PDSLEEPCFG0 mode bit, and for DPD
additionally clears the DSR request bits in PDRUNCFG0 so a stale request
cannot leak into the cold-boot state. FDPD needs one more write: it
leaves the voltage references in high-power mode so that a rising VDD1V8
can wake the chip, which costs 85uA and makes FDPD -- the deeper of the
two modes -- draw more than plain DPD. Measured at the RT700-EVK SOC
supply, 381uA in FDPD against 330uA in DPD. No wake-up source here uses
that path, so POWERCFG[FDPDBGLP] puts the band gap in low-power mode
instead, which brings FDPD down to 216uA. The bit is cleared by every
cold reset, the FDPD wake-up included, so it has to be set on each entry
rather than once at init.
Extending enum low_power_mode with LP_DPD and LP_FDPD is what keeps the
sequence honest about these modes. They sort above the returning modes,
so power_mode_returns() is false for both: power_enter_common() stops at
the one-way exit instead of saving and restoring arch state, and
power_keepalive_collect() stops holding up the SLEEPCON rail for a mode
that never observes a wake-up event.
power_common.c is now shared between the PM and the poweroff paths, so
both CMakeLists gates widen to PM or POWEROFF, and the domain modules
split their contents three ways accordingly. That also means the file
must build without CONFIG_PM, where arch_pm_state_set_prepare() and
_finish() do not exist: the weak fallback in arch/common/pm.c and the
Cortex-M override in cortex_m/cpu_idle.c are both CONFIG_PM-gated.
Testing the descriptor flag at run time is not enough, since the
reference still has to resolve at link time, so those calls carry a
compile-time guard.
CONFIG_POWEROFF cannot be selected yet; the following commit adds
HAS_POWEROFF and the sys_poweroff() backend that reaches this code.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
With both domains in place, connect them to the PM subsystem so the states
declared in devicetree can actually be entered.
pm_state_set() maps PM_STATE_RUNTIME_IDLE to a plain WFI with SLEEPDEEP
clear, PM_STATE_SUSPEND_TO_IDLE to deep sleep on either core, and
PM_STATE_STANDBY to DSR on the Compute domain only. DSR resets the OS
Timer, which therefore cannot wake the system; the system-timer low-power
companion armed by the timer driver owns wakeup instead
(CONFIG_SYSTEM_TIMER_RESET_BY_LPM). pm_state_exit_post_ops() has nothing
left to do, because power_enter_common() already restores the interrupt
state it changed.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Supply the Sense core's half of the framework: the resource map for
SLEEPCON1, the power_domain describing CPU1 (no DSR, no XIP responsibility,
no DSP) and a power_mode_desc for deep sleep, entered through
power_enter_common().
SLEEPCON1 is the shorter of the two SLEEPCFG layouts -- no compute main
clock and no FRO0/FRO1 -- so the resources it cannot control simply carry a
zero mask and power_commit() skips them. It is also why this domain's
res_sleepcon_rail is PWR_RES_NONE: SLEEPCON1 sits in VDD1_SENSE, which no
PDSLEEPCFG0 field of PMC1 controls, so there is no rail here for
power_keepalive_collect() to hold up on RM 31.3.3's account.
Unlike Compute, the shared-clock power-down-ready ignore bits for FRO2 and
LPOSC are set unconditionally. Sense cannot tell whether the Compute
domain is still using those clocks, and it is never the arbiter of which
domain goes down first, so it must not wait for a handshake that may never
complete. The Sense deep-sleep mode may still collapse the core rails and
retain only its own SRAM: the PMC aggregates both domains' votes, so while
Compute is running its own configuration holds the shared resources up and
Sense's votes are aggregated away.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
