The AES CCM AD (Additional Authenticated Data) relies on
dynamic memory allocation, the heap memory pool size
must be greater than zero.
This commit sets the heap memory one block size when you
enable crypto with CCM support. This ensures that the crypto
sample can be built and run.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Add support for the WCH QingKe V3A SoC series (CH32V10x family),
including Kconfig, CMake, pinctrl, and interrupt vector table.
Register the series in soc.yml.
Signed-off-by: Lucy Wong <mova845@outlook.com>
Add initial SoC support for the Microchip SmartFusion2 M2S010
platform.
This commit introduces the SmartFusion2 SoC integration layer
required to enable platform initialization and Zephyr build
integration for the M2S010 family. The implementation includes
basic SoC initialization code, register definitions, Kconfig
integration, and build system support.
Signed-off-by: Anton Vynohradov <vynohradov.external@bavariamatic.com>
When application is running in xip from the nor flash controlled by
the xspi manager, prevent controller full re-initialization.
Tested with
west build samples/hello_world
-b stm32h7s78_dk/stm32h7s7xx/ext_flash_app
--sysbuild -p
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The sleeptimer service from the gecko_sdk is a generic API which supports
multiple hardware timer peripherals internally. The reason we want to use
this rather than a Zephyr native driver, is that sleeptimer is what's used
by the power_manager service from the SDK which in turn is used by librail.
Combined with other, future commits, this will allow reducing the power
consumption of gecko_sdk based SoCs while they are idle.
Since the APIs between gecko_sdk and simplicity_sdk are the same, all
that's needed is to adjust the Kconfig dependencies and compile the
relevant sdk code. For now, this supports the RTCC peripheral only, which
is used on efr32mg13p, which is what I test with.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Add a shared ETM channel allocator that routes a peripheral event to a
peripheral task in hardware. Gated by the new in-tree
ESP32_SOC_ETM_SUPPORTED capability.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Following commit 4b57150 where stm32mp133.dtsi has been introduced.
For compliance purpose, complete SoC configuration consequently.
Signed-off-by: Erwan SZYMANSKI <erwan.szymanski@st.com>
Without esp_clk_tree_initialize() the clock tree stays uninitialized
and esp_clk_tree_enable_src() is a no-op, so peripheral source clocks
are not brought up. Initialize it at boot, as done on esp32p4.
Signed-off-by: Sylvio Alves <sylviojalves@gmail.com>
This commit adds the necessary Kconfig for TF-M support on STM32U3.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Read the chip revision during hardware init and log a warning when the
silicon is older than the minimum configured through
SOC_ESP32P4_REV_MIN_FULL, so a revision mismatch is visible at boot.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Pre-v3 silicon places the L2 cache at the high end of HP SRAM, so
usable RAM starts at the SRAM base instead of after the cache, and the
ROM reserves its static data at a lower address. Select the SRAM origin
and the ROM-reserved boundary based on the configured revision so the
linker places code, data and stack in valid RAM on both pre-v3 and
v3.x parts.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The per-context interrupt threshold CSR mintthresh (0x347) only exists
on ESP32-P4 rev v3.0 and above. On pre-v3 silicon, accessing it in the
context save/restore path is an illegal instruction, which traps on the
first context switch and hangs the kernel. Guard the save and restore
of this CSR so it is skipped on pre-v3 builds.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add hidden SOC_ESP32P4_REV_* symbols (v1.3, v3.0, v3.1) and the
derived SOC_ESP32P4_REV_MIN_FULL integer so a board can declare the
minimum supported chip revision. The v3.x family floors at v3.1,
matching the reference SDK.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/openisa/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
CONFIG_LEGACY_GENERATED_INCLUDE_PATH is deprecated and no longer
enabled by default, so generated headers must be included with the
zephyr/ prefix. Fix the legacy <autoconf.h> include in the HiFi4
memory layout header so the SoC builds without the deprecated
compatibility option.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
CONFIG_LEGACY_GENERATED_INCLUDE_PATH is deprecated and no longer
enabled by default, so generated headers must be included with the
zephyr/ prefix. Fix the legacy <autoconf.h> include in the linker
script so the SoC builds without the deprecated compatibility
option.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a system timer driver for the NXP RTC (rtc_jdp) IP on the MCXE31x
family. It implements the standard system clock interfaces and is
selected through the zephyr,system-timer chosen property pointing at an
nxp,rtc-jdp node.
The RTC is a free-running 32-bit up-counter with a single absolute
compare register (RTCVAL); the driver runs tickless against it. Because
the RTC keeps counting in all low-power states, it can serve as the
kernel tick source without a companion timer.
RTCVAL is an equality compare that synchronizes into the slow RTC clock
domain and sets INV_RTC while in progress, during which further RTCVAL
writes are ignored. The driver waits for INV_RTC to clear before a write
and, after it, re-reads the counter and retries with the compare bumped
forward if the count has already reached it, so a match is never lost to
the sync latency (a miss would only recur after a full 32-bit wrap). The
scheduling horizon is capped at half the counter range so a compare
cannot wrap past the counter and look like the past, mirroring
mcux_stm_timer.c.
The counter rate (clock-frequency / prescaler) is published at runtime
via TIMER_READS_ITS_FREQUENCY_AT_RUNTIME, making the devicetree
prescaler the single source of truth for the tick rate. The MCXE31x SoC
defconfig disables SysTick and defaults the tick rate when this timer is
selected.
Validated on frdm_mcxe31b: tests/kernel/timer/timer_api passes 15/15.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The R5 cores in K3 platform devices have only a small amount of local
memory. For larger projects much of the code is intended to be placed in
DRAM. But DRAM is XN by default. If Zephyr code area is in DRAM then we
need to setup a simple MPU region to enable execute permissions before
jumping to the real Zephyr start code in DRAM.
If placing Zephyr in DRAM, keep a small stub in ATCM which does this.
This is only active when setting Zephyr to run from DRAM, it can
still be run entirely from ATCM if the application is small enough
to allow for that by leaving `zephyr,sram = &atcm;` in DT.
Signed-off-by: Andrew Davis <afd@ti.com>
Customer demand requires porting the MEC172x version 2 eSPI
driver to MEC174x/5x/165x. We must move the eSPI V2 headers
out of the MEC172x SoC directory into a common directory.
There are several other small changes due to register
differences in various hardware subystems such as PCR,
KBC-8042, QMSPI, etc.
We added old register structures and defines allowing eSPI SAF V2
driver to build. These will be removed in the future PR updating
eSPI SAF V2 to use Zephyr system register access inline functions.
We can then remove the difficult to maintain registe stuctures.
Signed-off-by: scott worley <scott.worley@microchip.com>
The ACE and CAVS Xtensa linker scripts never included the generated
snippets-data-sections.ld file, so any section registered through
zephyr_linker_sources(DATA_SECTIONS ...) was silently dropped. The new
ztest benchmark framework registers its iterable RAM sections this way,
which made benchmark tests fail to link with undefined references to
_ztest_benchmark_*_list_start/end on these SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
With the introduction of the DEVICE_MMIO facilities in the Xilinx GEM
device driver in #87313, the two static, identity-mapped MMU entries
for the register spaces of the two GEM instances defined at the SoC
level and processed when initially setting up the MMU page tables are
no longer used and no longer required for the driver to function.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/nuvoton/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/infineon/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/st/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Clarify the explanation regarding DMA2D / LVGL alignments are
use configdefault instead of config for LV_DRAW_DMA2D_HAL_INCLUDE
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Data cache is managed only if CONFIG_CACHE_MANAGEMENT is enabled.
Use both Kconfigs (DCACHE and CACHE_MANAGEMENT) to determine
data cache support in dmm.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
MAX32651 is secure version of MAX32650 SoC. For secure SoCs, SBT(ADI
Secure Boot Tools) is used to sign the firmware. This commit implements
signing the firmware feature by using SBT's scripts. To enable this
feature, the following changes are made:
- New Kconfig options are added to enable SBT signing.
- CONFIG_SOC_FAMILY_MAX32_SECURE_SOC_SIGNING
- CONFIG_SOC_FAMILY_MAX32_SECURE_SOC_KEY_PATH
- Created sbt_signing.cmake to automate firmware signing workflow.
- Added sbt_sla_header.ld linker file to allocate a header section in
rom_start region and placed this region before IVT.
- Added sbt_sla_symbols.ld linker file to define the symbols used by
SBT.
- Added linker_with_sig_section.ld linker file and set this as
'CUSTOM_LINKER_SCRIPT' for secure SoCs. This linker file is a copy of
ARM Cortex-M linker file. The only difference is that there is a '.sig'
section defined after '.last_section' section to store image signiture.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
- The MRCC reset registers use different instance and field
names across MCX families.
Add a set of abstraction macros that select the correct
names based on the SoC family,
allowing the driver to build for the MCXL family in addition to
the existing MCX SoCs.
- Enables the RESET driver by default on the MCXL family when an
nxp,mrcc-reset node is enabled in devicetree.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Don't overwrite disassembly_flag_inline_source
otherwise CONFIG_OUTPUT_DISASSEMBLY_WITH_SOURCE
does not work.
This is should only be set in
zephyr/cmake/bintools/*/target_bintools.cmake
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This option can be used to override `CONFIG_SOC` at STM32Cube HAL module
level, which is useful for a few specific products where the SoC name
does not match the preprocessor definition that the HAL needs to add
in order to work properly.
While at it, update the STM32F0 and STM32F4 series Kconfig to make use
of this new option, allowing `CONFIG_SOC` to now always reflect the
selected SoC's actual name.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Various SoCs were declared in `Kconfig.soc` but had no corresponding
entry in the top-level `soc.yml`: add the missing entries.
Found using the following command:
comm -23
<(grep -h "^config SOC_STM32[^_]*$" soc/st/stm32/*/Kconfig.soc
| sed 's/config SOC_//'
| tr '[:upper:]' '[:lower:]'
| sort)
<(grep "^\s*- name: stm32" soc/st/stm32/soc.yml
| sed 's/.*- name: //'
| sort)
Note: this commands displays false positives for STM32WB0 SoCs due to
these SoC's Kconfig options using an `XX` suffix for consistency with
other series, despite the value of `CONFIG_SOC` not using any suffix.
This is on purpose and not an error: the value in `CONFIG_SOC` does
match what's in `soc.yml`.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add STM32WBAx suspend-to-RAM support and hook the SoC-specific
implementation into the build when CONFIG_PM_S2RAM is enabled.
Select the custom S2RAM marking capability and add the STM32WBAx S2RAM
support source file.
Update the suspend-to-RAM path to clear the hardware standby flag as early
as possible after resume. Use standby_entered as a software indicator to
track whether standby was effectively entered and cleared, so resume
handling only restores radio state when needed.
Signed-off-by: Romain Jayles <romain.jayles@st.com>
