Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Only uart2 and uart6 were considered before, so if any other uart
was used, it wouldn't work and even worse, it would crash when
trying to access it because the RDC wasn't configured.
Signed-off-by: Diego Herranz <diegoherranz@diegoherranz.com>
When RISCV_ISA_EXT_A is enabled,
ATOMIC_OPERATIONS_BUILTIN automaticly enabled,
we don't need to do it at the soc level again.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The Kconfig symbols for selecting HAL content should be part
of the HAL module integration, not defined by the SoC. Split the
symbols between the Series 0/1 Gecko HAL and Series 2 SiSDK HAL
when moving them.
For now, the Series 0/1 HAL symbols retain their name, while new
names consistent with the symbols already defined in the module
integration layer are used for the Series 2 HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Series 2 specific defconfigs for Bluetooth related options should
be set in the Series 2 specific defconfig file.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Move the Kconfig symbol for the SE HAL to hal_silabs.
Select the symbol in the entropy driver rather than unconditionally
at the SoC level.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
COUNTER_GECKO_STIMER is defined by the counter driver. It should
not be present in SoC Kconfig.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Kconfig symbols for selecting HAL content should be part of the
HAL module integration, not defined in the SoC tree.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The indirection through a backend symbol for PM implementation
isn't necessary. Define symbol for PM HAL in HAL Kconfig, and
leverage it at SoC level.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Kconfig symbols for selecting HAL content should be part of the
HAL module integration, not defined in the SoC tree. Define the
sleeptimer symbol for WiSeConnect and SiSDK since both use it.
In the future, WiSeConnect should include the SiSDK configuration
and reuse it instead of redefining everything itself. This is a
larger scale refactor that this commit doesn't start tackling.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add ITM to common device tree and set the correct clock config
when using SWO as a logging backend
Signed-off-by: Henrik Grunmach <henrik.grunmach@rohde-schwarz.com>
- create 'mcxe' as family and 'mcxe24x' as series
- add pinctrl_soc.h
- add soc.c/.h to do system initialization
- Support flash boot if CONFIG_MCXE_FLASH_CONFIG==1
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Adds HPPASS SAR ADC driver and HPPASS Analog driver files to support
ADC conversion for the PSOC C3 family of MCUs.
Signed-off-by: John Batch <john.batch@infineon.com>
This allows adding the CPU ID to the number of NOPs in
the custom arch_spin_relax(). With the same number of NOPs
for all CPUs, it is possible to have them all doing RCW
transactions at the same time over and over again if they
enter and exit the spin relax loop at the same time.
This behavior has been observed when doing lots of context
switching, like in the SMP switching stress test. So adds
a new kconfig to fine tune the relax loop behavior if
needed. The new kconfig allows adding the CPU ID to
the number of NOPs which will add some minimal offsetting
to workaround the above mentioned situation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
MAX32658 is the 1.8V variant of MAX32657. From a software perspective,
both SoCs are functionally equivalent. Reuse the existing MAX32657
backend for MAX32658 to enable support with minimal changes.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Adds initial SoC-level support for the Microchip
PIC32CZ CA80/9x series, including SoC definition files.
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
When the XDMAC is activated in the DT, configure it's register region
with strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Product URL: https://www.microchip.com/en-us/product/SAMA7D65
The files under 'soc/microchip/sam/sama7/' will be used for both
sama7d5 and sama7d65 SoCs after the directory structure for sama7g5
is reorganized.
Signed-off-by: Tony Han <tony.han@microchip.com>
Replace the array size for sama7g5 registered clocks with macros and
put the macros to soc.h with descriptions.
Signed-off-by: Tony Han <tony.han@microchip.com>
Change the location of the names for programable clocks from the
stack to "static struct clk_programmable" array.
Signed-off-by: Tony Han <tony.han@microchip.com>
We added ECIA GIRQ get/set/clear functions avaiable for
all MEC parts. Drivers can make use of these functions
to get, set, and clear GIRQ status and enables for
their peripheral. In cases where code requires 8/16 bit
access to these or other SoC registers we added inline
helpers modeled after Zephyr's 32-bit sys_read/write/test
routines. This commit is part of a long term goal to share
drivers among all the MEC parts.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
When the PWM is activated in the DT, configure it's register region
with strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Adds initial SoC-level support for the Microchip
PIC32CX SG series, including SoC definition files.
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
