soc: renesas: Add initial support for Renesas RZ/G2UL

Add initial support for Renesas RZ/G2UL

Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit is contained in:
Phuc Pham 2025-05-26 17:21:15 +07:00 committed by Fabio Baltieri
commit adeaad5e6f
9 changed files with 120 additions and 1 deletions

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@ -1,6 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# Copyright (c) 2024-2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_RENESAS_RZ
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
if SOC_FAMILY_RENESAS_RZ
rsource "*/Kconfig"

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@ -0,0 +1,8 @@
# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(soc.c)
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RZG2UL
select ARM
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RZ_FSP
select CPU_CORTEX_M_HAS_DWT
select SOC_EARLY_INIT_HOOK

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_RZG2UL
config NUM_IRQS
default 480
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config FLASH_SIZE
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
config SYS_CLOCK_EXISTS
default y
config INIT_ARCH_HW_AT_BOOT
default y
endif # SOC_SERIES_RZG2UL

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RZG2UL
bool
select SOC_FAMILY_RENESAS_RZ
help
Renesas RZ/G2UL series
config SOC_SERIES
default "rzg2ul" if SOC_SERIES_RZG2UL
config SOC_R9A07G043U11GBG
bool
select SOC_SERIES_RZG2UL
help
R9A07G043U11GBG
config SOC_R9A07G043U11GBG_CM33
bool
select SOC_R9A07G043U11GBG
config SOC
default "r9a07g043u11gbg" if SOC_R9A07G043U11GBG

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_RENESAS_RZ_RZG2UL_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RENESAS_RZ_RZG2UL_PINCTRL_SOC_H_
#include <pinctrl_rzg.h>
#endif /* ZEPHYR_SOC_RENESAS_RZ_RZG2UL_PINCTRL_SOC_H_ */

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Renesas RZ/G2UL Group
*/
#include <zephyr/init.h>
#include <bsp_api.h>
/* System core clock is set to 200 MHz after reset */
uint32_t SystemCoreClock = 200000000;
void soc_early_init_hook(void)
{
/* Configure system clocks. */
bsp_clock_init();
}

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_RENESAS_RZG2UL_SOC_H_
#define ZEPHYR_SOC_RENESAS_RZG2UL_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RZG2UL_SOC_H_ */

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@ -15,6 +15,11 @@ family:
- name: r9a07g044c22gbg
cpuclusters:
- name: cm33
- name: rzg2ul
socs:
- name: r9a07g043u11gbg
cpuclusters:
- name: cm33
- name: rzg3s
socs:
- name: r9a08g045s33gbg