boards: arm: add support for MPS4 Corstone-320
Add initial support for the MPS4 Corstone-320 platform, including board and SoC definitions. This platform features a Cortex-M85 CPU with an Ethos-U85 NPU and runs in simulation using the FVP_Corstone_SSE-320 Fixed Virtual Platform. Signed-off-by: Sudan Landge <sudan.landge@arm.com>
This commit is contained in:
Sudan Landge
Dan Kalowsky
parent
5ba88753cc
commit
d1e830fe0d
19 changed files with 769 additions and 0 deletions
23
boards/arm/mps4/Kconfig.defconfig
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23
boards/arm/mps4/Kconfig.defconfig
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# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_MPS4_CORSTONE320_FVP
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if SERIAL
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config UART_INTERRUPT_DRIVEN
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default y
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endif # SERIAL
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if ROMSTART_RELOCATION_ROM && BOARD_MPS4_CORSTONE320_FVP
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config ROMSTART_REGION_ADDRESS
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default $(dt_nodelabel_reg_addr_hex,itcm)
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config ROMSTART_REGION_SIZE
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default $(dt_nodelabel_reg_size_hex,itcm,0,k)
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endif
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endif
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6
boards/arm/mps4/Kconfig.mps4
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6
boards/arm/mps4/Kconfig.mps4
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# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MPS4
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select SOC_SERIES_MPS4
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select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS
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45
boards/arm/mps4/board.cmake
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45
boards/arm/mps4/board.cmake
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# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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# SPDX-License-Identifier: Apache-2.0
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#
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# Default emulation:
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# FVP is used by default for corstone320/fvp.
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#
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if(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS)
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set(SUPPORTED_EMU_PLATFORMS armfvp)
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set(ARMFVP_BIN_NAME FVP_Corstone_SSE-320)
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if(CONFIG_BOARD_MPS4_CORSTONE320_FVP)
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set(ARMFVP_FLAGS
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# default is '0x11000000' but should match cpu<i>.INITSVTOR which is 0.
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-C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0
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# default is 0x8, this change is needed since we split flash into itcm
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# and sram and it reduces the number of available mpu regions causing a
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# few MPU tests to fail.
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-C mps4_board.subsystem.cpu0.MPU_S=16
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)
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endif()
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endif()
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if(CONFIG_BUILD_WITH_TFM)
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set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex)
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endif()
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# FVP Parameters
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# -C indicate a config option in the form of:
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# instance.parameter=value
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# Run the FVP with --list-params to list all options
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set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
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-C mps4_board.uart0.out_file=-
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-C mps4_board.uart0.unbuffered_output=1
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-C mps4_board.uart1.out_file=-
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-C mps4_board.uart1.unbuffered_output=1
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-C mps4_board.uart2.out_file=-
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-C mps4_board.uart2.unbuffered_output=1
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-C mps4_board.visualisation.disable-visualisation=1
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-C mps4_board.telnetterminal0.start_telnet=0
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-C mps4_board.telnetterminal1.start_telnet=0
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-C mps4_board.telnetterminal2.start_telnet=0
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-C vis_hdlcd.disable_visualisation=1
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)
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10
boards/arm/mps4/board.yml
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10
boards/arm/mps4/board.yml
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board:
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name: mps4
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full_name: MPS4
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vendor: arm
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socs:
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- name: 'corstone320'
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variants:
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- name: 'fvp'
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variants:
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- name: 'ns'
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119
boards/arm/mps4/mps4_common.dtsi
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119
boards/arm/mps4/mps4_common.dtsi
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/*
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* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* /dts-v1/; */
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#include <arm/armv8.1-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <mem.h>
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/ {
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aliases {
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led0 = &led_0;
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led1 = &led_1;
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sw0 = &user_button_0;
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sw1 = &user_button_1;
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};
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leds {
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compatible = "gpio-leds";
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led_0: led_0 {
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gpios = <&gpio_led0 0>;
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label = "USERLED0";
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};
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led_1: led_1 {
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gpios = <&gpio_led0 1>;
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label = "USERLED1";
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};
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led_2: led_2 {
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gpios = <&gpio_led0 2>;
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label = "USERLED2";
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};
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led_3: led_3 {
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gpios = <&gpio_led0 3>;
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label = "USERLED3";
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};
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led_4: led_4 {
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gpios = <&gpio_led0 4>;
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label = "USERLED4";
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};
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led_5: led_5 {
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gpios = <&gpio_led0 5>;
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label = "USERLED5";
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};
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led_6: led_6 {
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gpios = <&gpio_led0 6>;
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label = "USERLED6";
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};
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led_7: led_7 {
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gpios = <&gpio_led0 7>;
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label = "USERLED7";
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};
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led_8: led_8 {
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gpios = <&gpio_led0 8>;
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label = "PB1LED";
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};
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led_9: led_9 {
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gpios = <&gpio_led0 9>;
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label = "PB2LED";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_0: button_0 {
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label = "USERPB0";
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gpios = <&gpio_button 0>;
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zephyr,code = <INPUT_KEY_0>;
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};
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user_button_1: button_1 {
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label = "USERPB1";
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gpios = <&gpio_button 1>;
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zephyr,code = <INPUT_KEY_1>;
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};
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};
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null_ptr_detect: null_ptr_detect@0 {
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compatible = "zephyr,memory-region";
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/* 0 - CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE> */
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reg = <0x0 0x400>;
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zephyr,memory-region = "NULL_PTR_DETECT";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>;
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};
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/* DDR4 - 2G, alternates non-secure/secure every 256M */
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ddr4: memory@60000000 {
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device_type = "memory";
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compatible = "zephyr,memory-region";
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reg = <0x60000000 DT_SIZE_M(256)
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0x70000000 DT_SIZE_M(256)
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0x80000000 DT_SIZE_M(256)
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0x90000000 DT_SIZE_M(256)
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0xa0000000 DT_SIZE_M(256)
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0xb0000000 DT_SIZE_M(256)
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0xc0000000 DT_SIZE_M(256)
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0xd0000000 DT_SIZE_M(256)>;
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zephyr,memory-region = "DDR4";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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209
boards/arm/mps4/mps4_common_soc_peripheral.dtsi
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209
boards/arm/mps4/mps4_common_soc_peripheral.dtsi
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@ -0,0 +1,209 @@
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/*
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* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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#clock-cells = <0>;
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};
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gpio0: gpio@100000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x100000 0x1000>;
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interrupts = <69 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@101000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x101000 0x1000>;
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interrupts = <70 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: gpio@102000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x102000 0x1000>;
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interrupts = <71 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio3: gpio@103000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x103000 0x1000>;
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interrupts = <72 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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eth0: eth@400000 {
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/* Linux has "smsc,lan9115" */
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compatible = "smsc,lan9220";
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/* Actual reg range is ~0x200 */
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reg = <0x400000 0x100000>;
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interrupts = <49 3>;
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};
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i2c_touch: i2c@8100000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8100000 0x1000>;
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};
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i2c_audio_conf: i2c@8101000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8101000 0x1000>;
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};
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spi_adc: spi@8102000 {
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compatible = "arm,pl022";
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reg = <0x8102000 DT_SIZE_K(4)>;
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interrupts = <53 3>;
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interrupt-names = "shield_adc";
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clocks = <&sysclk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi_shield0: spi@8103000 {
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compatible = "arm,pl022";
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reg = <0x8103000 DT_SIZE_K(4)>;
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interrupts = <54 3>;
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interrupt-names = "shield0_spi";
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clocks = <&sysclk>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&spi3_default>;
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pinctrl-names = "default";
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};
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spi_shield1: spi@8104000 {
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compatible = "arm,pl022";
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reg = <0x8104000 DT_SIZE_K(4)>;
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interrupts = <55 3>;
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interrupt-names = "shield1_spi";
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clocks = <&sysclk>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&spi4_default>;
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pinctrl-names = "default";
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};
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i2c_shield0: i2c@8105000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8105000 0x1000>;
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pinctrl-0 = <&sbcon2_default>;
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pinctrl-names = "default";
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};
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i2c_shield1: i2c@8106000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8106000 0x1000>;
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pinctrl-0 = <&sbcon3_default>;
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pinctrl-names = "default";
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};
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i2c_ddr4_eeprom: i2c@8108000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8108000 0x1000>;
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};
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gpio_led0: mps4_fpgaio@8202000 {
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compatible = "arm,mmio32-gpio";
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reg = <0x8202000 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <8>;
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};
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gpio_button: mps4_fpgaio@8202008 {
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compatible = "arm,mmio32-gpio";
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reg = <0x8202008 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <2>;
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direction-input;
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};
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gpio_misc: mps4_fpgaio@820204c {
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compatible = "arm,mmio32-gpio";
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reg = <0x820204c 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <3>;
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};
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uart0: uart@8203000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x8203000 0x1000>;
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interrupts = <34 3 33 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart1: uart@8204000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x8204000 0x1000>;
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interrupts = <36 3 35 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart2: uart@8205000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x8205000 0x1000>;
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interrupts = <38 3 37 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart3: uart@8206000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x8206000 0x1000>;
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interrupts = <40 3 39 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart4: uart@8207000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x8207000 0x1000>;
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interrupts = <42 3 41 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart5: uart@8208000 {
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compatible = "arm,cmsdk-uart";
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status = "disabled";
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reg = <0x8208000 0x1000>;
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interrupt-names = "tx", "rx";
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interrupts = <126 3 125 3>;
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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97
boards/arm/mps4/mps4_corstone320_fvp.dts
Normal file
97
boards/arm/mps4/mps4_corstone320_fvp.dts
Normal file
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/*
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* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm/armv8.1-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <mem.h>
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/ {
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compatible = "arm,mps4-fvp";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &sram;
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zephyr,flash = &isram;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m85";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8.1m-mpu";
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reg = <0xe000ed90 0x40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethosu {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&nvic>;
|
||||
|
||||
ethosu0: ethosu@50004000 {
|
||||
compatible = "arm,ethos-u";
|
||||
reg = <0x50004000>;
|
||||
interrupts = <16 3>;
|
||||
secure-enable;
|
||||
privilege-enable;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
/* We utilize the secure addresses, if you subtract 0x10000000
|
||||
* you'll get the non-secure alias
|
||||
*/
|
||||
itcm: itcm@10000000 { /* alias @ 0x0 */
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x10000000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "ITCM";
|
||||
};
|
||||
|
||||
sram: sram@12000000 { /* alias @ 0x01000000 */
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x12000000 DT_SIZE_M(2)>;
|
||||
zephyr,memory-region = "SRAM";
|
||||
};
|
||||
|
||||
dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x30000000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
||||
isram: sram@31000000 { /* alias @ 0x21000000 */
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x31000000 DT_SIZE_M(4)>;
|
||||
zephyr,memory-region = "ISRAM";
|
||||
};
|
||||
|
||||
soc {
|
||||
peripheral@50000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x50000000 0x10000000>;
|
||||
|
||||
#include "mps4_common_soc_peripheral.dtsi"
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "mps4_common.dtsi"
|
||||
25
boards/arm/mps4/mps4_corstone320_fvp.yaml
Normal file
25
boards/arm/mps4/mps4_corstone320_fvp.yaml
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
identifier: mps4/corstone320/fvp
|
||||
name: Arm MPS4-Corstone320-FVP
|
||||
type: mcu
|
||||
arch: arm
|
||||
ram: 2048
|
||||
flash: 4096
|
||||
simulation:
|
||||
- name: armfvp
|
||||
exec: FVP_Corstone_SSE-320
|
||||
toolchain:
|
||||
- gnuarmemb
|
||||
- zephyr
|
||||
supported:
|
||||
- gpio
|
||||
testing:
|
||||
default: true
|
||||
ignore_tags:
|
||||
- drivers
|
||||
- bluetooth
|
||||
- net
|
||||
- timer
|
||||
vendor: arm
|
||||
19
boards/arm/mps4/mps4_corstone320_fvp_defconfig
Normal file
19
boards/arm/mps4/mps4_corstone320_fvp_defconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
CONFIG_RUNTIME_NMI=y
|
||||
CONFIG_ARM_TRUSTZONE_M=y
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# GPIOs
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Serial
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_SERIAL=y
|
||||
|
||||
# Build a Secure firmware image
|
||||
CONFIG_TRUSTED_EXECUTION_SECURE=y
|
||||
# ROMSTART_REGION address and size are defined in Kconfig.defconfig
|
||||
CONFIG_ROMSTART_RELOCATION_ROM=y
|
||||
102
boards/arm/mps4/mps4_corstone320_fvp_ns.dts
Normal file
102
boards/arm/mps4/mps4_corstone320_fvp_ns.dts
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <arm/armv8.1-m.dtsi>
|
||||
#include <zephyr/dt-bindings/i2c/i2c.h>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
#include <mem.h>
|
||||
|
||||
/ {
|
||||
compatible = "arm,mps4-fvp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen {
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,sram = &ram;
|
||||
zephyr,flash = &code;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m85";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mpu: mpu@e000ed90 {
|
||||
compatible = "arm,armv8.1m-mpu";
|
||||
reg = <0xe000ed90 0x40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* We utilize the secure addresses, if you subtract 0x10000000
|
||||
* you'll get the non-secure alias
|
||||
*/
|
||||
itcm: itcm@0 {
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x0 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "ITCM";
|
||||
};
|
||||
|
||||
sram: sram@1000000 {
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x1000000 DT_SIZE_M(2)>;
|
||||
zephyr,memory-region = "SRAM";
|
||||
};
|
||||
|
||||
dtcm: dtcm@20000000 {
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x20000000 DT_SIZE_K(512)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
||||
isram: sram@21000000 {
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x21000000 DT_SIZE_M(4)>;
|
||||
zephyr,memory-region = "ISRAM";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* The memory regions defined below must match what the TF-M
|
||||
* project has defined for that board - a single image boot is
|
||||
* assumed. Please see the memory layout in:
|
||||
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps4/corstone320/common/partition/flash_layout.h
|
||||
*/
|
||||
|
||||
code: memory@28080000 {
|
||||
reg = <0x28080000 DT_SIZE_K(512)>;
|
||||
};
|
||||
|
||||
ram: memory@21020000 {
|
||||
reg = <0x21020000 DT_SIZE_M(1)>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
peripheral@40000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x40000000 0x10000000>;
|
||||
|
||||
#include "mps4_common_soc_peripheral.dtsi"
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "mps4_common.dtsi"
|
||||
15
boards/arm/mps4/mps4_corstone320_fvp_ns.yaml
Normal file
15
boards/arm/mps4/mps4_corstone320_fvp_ns.yaml
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
identifier: mps4/corstone320/fvp/ns
|
||||
name: Arm MPS4-Corstone320-FVP_ns
|
||||
type: mcu
|
||||
arch: arm
|
||||
ram: 1024
|
||||
flash: 512
|
||||
toolchain:
|
||||
- gnuarmemb
|
||||
- zephyr
|
||||
testing:
|
||||
only_tags:
|
||||
- trusted-firmware-m
|
||||
19
boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig
Normal file
19
boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
CONFIG_ARM_TRUSTZONE_M=y
|
||||
CONFIG_RUNTIME_NMI=y
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# GPIOs
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Serial
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_SERIAL=y
|
||||
|
||||
# Build a Non-secure firmware image
|
||||
CONFIG_TRUSTED_EXECUTION_SECURE=n
|
||||
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
|
||||
CONFIG_BUILD_WITH_TFM=y
|
||||
6
soc/arm/mps4/CMakeLists.txt
Normal file
6
soc/arm/mps4/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
21
soc/arm/mps4/Kconfig
Normal file
21
soc/arm/mps4/Kconfig
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_MPS4
|
||||
select ARM
|
||||
select GPIO_MMIO32 if GPIO
|
||||
|
||||
config SOC_MPS4_CORSTONE320
|
||||
select CPU_CORTEX_M85
|
||||
select CPU_HAS_ARM_SAU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_FPU
|
||||
select ARMV8_M_DSP
|
||||
select ARMV8_1_M_MVEI
|
||||
select ARMV8_1_M_MVEF
|
||||
select ARMV8_1_M_PMU
|
||||
select ARM_MPU_PXN if ARM_MPU
|
||||
|
||||
config ARMV8_1_M_PMU_EVENTCNT
|
||||
int
|
||||
default 8 if SOC_MPS4_CORSTONE320
|
||||
11
soc/arm/mps4/Kconfig.defconfig
Normal file
11
soc/arm/mps4/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_MPS4
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(dt_nodelabel_path,sysclk),clock-frequency)
|
||||
|
||||
rsource "Kconfig.defconfig.mps4*"
|
||||
|
||||
endif # SOC_SERIES_MPS4
|
||||
9
soc/arm/mps4/Kconfig.defconfig.mps4_corstone320
Normal file
9
soc/arm/mps4/Kconfig.defconfig.mps4_corstone320
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MPS4_CORSTONE320
|
||||
|
||||
config NUM_IRQS
|
||||
default 232
|
||||
|
||||
endif
|
||||
18
soc/arm/mps4/Kconfig.soc
Normal file
18
soc/arm/mps4/Kconfig.soc
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_MPS4
|
||||
bool
|
||||
select SOC_FAMILY_ARM
|
||||
help
|
||||
Enable support for ARM MPS4 MCU Series
|
||||
|
||||
config SOC_SERIES
|
||||
default "mps4" if SOC_SERIES_MPS4
|
||||
|
||||
config SOC_MPS4_CORSTONE320
|
||||
bool
|
||||
select SOC_SERIES_MPS4
|
||||
|
||||
config SOC
|
||||
default "corstone320" if SOC_MPS4_CORSTONE320
|
||||
12
soc/arm/mps4/soc.h
Normal file
12
soc/arm/mps4/soc.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_H_
|
||||
#define _SOC_H_
|
||||
|
||||
#include <cmsis_core_m_defaults.h>
|
||||
|
||||
#endif /* _SOC_H_ */
|
||||
|
|
@ -15,6 +15,9 @@ family:
|
|||
socs:
|
||||
- name: corstone300
|
||||
- name: corstone310
|
||||
- name: mps4
|
||||
socs:
|
||||
- name: corstone320
|
||||
- name: musca
|
||||
socs:
|
||||
- name: musca_b1
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue