soc: renesas: Add initial support for Renesas RZ/V2H

Add initial support for Renesas RZ/V2H

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
This commit is contained in:
Tien Nguyen 2025-05-07 09:57:40 +07:00 committed by Benjamin Cabé
commit 9970d21348
9 changed files with 129 additions and 0 deletions

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
if(CONFIG_SOC_R9A09G057H44GBG_CM33)
zephyr_include_directories(cm33)
zephyr_sources(cm33/soc.c)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
endif()

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_R9A09G057H44GBG_CM33
select ARM
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RZ_FSP
select CPU_CORTEX_M_HAS_DWT
select SOC_EARLY_INIT_HOOK
select CPU_HAS_FPU
select ARMV8_M_DSP

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_RZV2H
rsource "Kconfig.defconfig.*"
endif # SOC_SERIES_RZV2H

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_R9A09G057H44GBG_CM33
config NUM_IRQS
default 480
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config FLASH_SIZE
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
config SYS_CLOCK_EXISTS
default y
config INIT_ARCH_HW_AT_BOOT
default y
endif # SOC_R9A09G057H44GBG_CM33

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RZV2H
bool
select SOC_FAMILY_RENESAS_RZ
help
Renesas RZ/V2H series
config SOC_SERIES
default "rzv2h" if SOC_SERIES_RZV2H
config SOC_R9A09G057H44GBG
bool
select SOC_SERIES_RZV2H
help
R9A09G057H44GBG
config SOC_R9A09G057H44GBG_CM33
bool
select SOC_R9A09G057H44GBG
help
RZ/V2H CM33
config SOC
default "r9a09g057h44gbg" if SOC_R9A09G057H44GBG

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Renesas RZ/V2H Group
*/
#include <zephyr/init.h>
#include <bsp_api.h>
/* System core clock is set to 200 MHz after reset */
uint32_t SystemCoreClock = 200000000;
void soc_early_init_hook(void)
{
bsp_clock_init();
}

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_RENESAS_RZV2H_SOC_H_
#define ZEPHYR_SOC_RENESAS_RZV2H_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RZV2H_SOC_H_ */

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_RENESAS_RZ_RZV2H_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RENESAS_RZ_RZV2H_PINCTRL_SOC_H_
#include <pinctrl_rzv.h>
#endif /* ZEPHYR_SOC_RENESAS_RZ_RZV2H_PINCTRL_SOC_H_ */

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@ -25,6 +25,11 @@ family:
- name: r9a07g054l23gbg
cpuclusters:
- name: cm33
- name: rzv2h
socs:
- name: r9a09g057h44gbg
cpuclusters:
- name: cm33
- name: rzn2l
socs:
- name: r9a07g084m04gbg