driver: espi: add espi peripheral channel port 80 driver for rts5912
add espi peripheral channel port 80 driver for rts5912 Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
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3 changed files with 117 additions and 0 deletions
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@ -10,6 +10,9 @@ config ESPI_RTS5912
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if ESPI_RTS5912
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config ESPI_PERIPHERAL_DEBUG_PORT_80
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default y
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config ESPI_OOB_CHANNEL
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default y
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@ -18,6 +18,7 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
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#include "espi_utils.h"
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#include "reg/reg_espi.h"
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#include "reg/reg_port80.h"
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "support only one espi compatible node");
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@ -25,6 +26,11 @@ struct espi_rts5912_config {
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volatile struct espi_reg *const espi_reg;
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uint32_t espislv_clk_grp;
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uint32_t espislv_clk_idx;
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#ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
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volatile struct port80_reg *const port80_reg;
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uint32_t port80_clk_grp;
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uint32_t port80_clk_idx;
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#endif
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const struct device *clk_dev;
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const struct pinctrl_dev_config *pcfg;
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};
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@ -45,6 +51,62 @@ struct espi_rts5912_data {
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#endif
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};
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/*
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* =========================================================================
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* ESPI Peripheral Debug Port 80
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* =========================================================================
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*/
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#ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
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static void espi_port80_isr(const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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struct espi_rts5912_data *espi_data = dev->data;
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struct espi_event evt = {ESPI_BUS_PERIPHERAL_NOTIFICATION,
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ESPI_PERIPHERAL_INDEX_0 << 16 | ESPI_PERIPHERAL_DEBUG_PORT80,
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ESPI_PERIPHERAL_NODATA};
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volatile struct port80_reg *const port80_reg = espi_config->port80_reg;
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evt.evt_data = port80_reg->DATA;
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espi_send_callbacks(&espi_data->callbacks, dev, evt);
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}
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static int espi_peri_ch_port80_setup(const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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struct rts5912_sccon_subsys sccon;
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volatile struct port80_reg *const port80_reg = espi_config->port80_reg;
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int rc;
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if (!device_is_ready(espi_config->clk_dev)) {
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return -ENODEV;
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}
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sccon.clk_grp = espi_config->port80_clk_grp;
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sccon.clk_idx = espi_config->port80_clk_idx;
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rc = clock_control_on(espi_config->clk_dev, (clock_control_subsys_t)&sccon);
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if (rc != 0) {
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return rc;
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}
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port80_reg->ADDR = 0x80UL;
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port80_reg->CFG = PORT80_CFG_CLRFLG | PORT80_CFG_THREEN;
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port80_reg->INTEN = PORT80_INTEN_THREINTEN;
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NVIC_ClearPendingIRQ(DT_IRQ_BY_NAME(DT_DRV_INST(0), port80, irq));
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), port80, irq),
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DT_IRQ_BY_NAME(DT_DRV_INST(0), port80, priority), espi_port80_isr,
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DEVICE_DT_GET(DT_DRV_INST(0)), 0);
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irq_enable(DT_IRQ_BY_NAME(DT_DRV_INST(0), port80, irq));
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return 0;
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80 */
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/*
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* =========================================================================
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* ESPI VWIRE channel
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@ -1573,6 +1635,15 @@ static int espi_rts5912_init(const struct device *dev)
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/* Setup eSPI bus reset */
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espi_bus_reset_setup(dev);
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#ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
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/* Setup Port80 */
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rc = espi_peri_ch_port80_setup(dev);
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if (rc != 0) {
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LOG_ERR("eSPI Port80 setup failed");
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goto exit;
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}
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#endif
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#ifdef CONFIG_ESPI_VWIRE_CHANNEL
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/* Setup eSPI virtual-wire channel */
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espi_vw_ch_setup(dev);
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@ -1608,6 +1679,11 @@ static const struct espi_rts5912_config espi_rts5912_config = {
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.espi_reg = (volatile struct espi_reg *const)DT_INST_REG_ADDR_BY_NAME(0, espi_target),
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.espislv_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), espi_target, clk_grp),
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.espislv_clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), espi_target, clk_idx),
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#ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
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.port80_reg = (volatile struct port80_reg *const)DT_INST_REG_ADDR_BY_NAME(0, port80),
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.port80_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), port80, clk_grp),
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.port80_clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), port80, clk_idx),
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#endif
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.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
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};
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38
soc/realtek/ec/rts5912/reg/reg_port80.h
Normal file
38
soc/realtek/ec/rts5912/reg/reg_port80.h
Normal file
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2025 Realtek, SIBG-SD7
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_PORT80_H
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#define ZEPHYR_SOC_REALTEK_RTS5912_REG_PORT80_H
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struct port80_reg {
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const uint32_t STS;
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uint32_t CFG;
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uint32_t INTEN;
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uint32_t DATA;
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uint32_t ADDR;
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};
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/* STS */
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#define PORT80_STS_FIFOEM BIT(0)
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#define PORT80_STS_FIFOFUL BIT(1)
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#define PORT80_STS_FIFOOVRN BIT(2)
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/* CFG */
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#define PORT80_CFG_CLRFLG BIT(0)
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#define PORT80_CFG_THRE GENMASK(2, 1)
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#define PORT80_CFG_THREEN BIT(7)
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#define PORT80_CFG_UARTPASS BIT(8)
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/* INTEN */
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#define PORT80_INTEN_THREINTEN BIT(0)
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/* DATA */
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#define PORT80_DATA_DATA GENMASK(7, 0)
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/* ADDR */
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#define PORT80_ADDR_ADDR GENMASK(7, 0)
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#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_PORT80_H */
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