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soc: imx943: add imx943 soc support

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This patch add i.MX 943 soc support.

The i.MX 943 applications processors integrate up to four Arm Cortex-A55
cores and supports functional safety with built-in 2x Arm Cortex -M33 and
-M7 cores which can be configured as a safety island. Optimizing
performance and power efficiency for Industrial, IoT and automotive
devices, i.MX 943 processors are built with NXP’s innovative Energy Flex
architecture.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This commit is contained in:
Jiafei Pan 2025-05-08 16:26:00 +08:00 • committed by Anas Nashif
commit c0aee5c224
11 changed files with 221 additions and 0 deletions
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2
soc/nxp/imx/imx9/CMakeLists.txt
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@ -5,6 +5,8 @@ if(CONFIG_SOC_MIMX9131)
add_subdirectory(imx91)
elseif(CONFIG_SOC_MIMX9352)
add_subdirectory(imx93)
elseif(CONFIG_SOC_MIMX94398)
add_subdirectory(imx943)
elseif(CONFIG_SOC_MIMX9596)
add_subdirectory(imx95)
endif()

8
soc/nxp/imx/imx9/imx943/CMakeLists.txt Normal file
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@ -0,0 +1,8 @@
# Copyright 2025 NXP
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
if(CONFIG_SOC_MIMX94398_A55)
add_subdirectory(a55)
endif()

9
soc/nxp/imx/imx9/imx943/Kconfig Normal file
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@ -0,0 +1,9 @@
# Copyright 2025 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_MIMX94398_A55
select ARM64
select CPU_CORTEX_A55
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
select HAS_MCUX
select HAS_MCUX_CACHE

8
soc/nxp/imx/imx9/imx943/Kconfig.defconfig Normal file
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@ -0,0 +1,8 @@
# Copyright 2025 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMX9
rsource "Kconfig.defconfig.*"
endif # SOC_SERIES_IMX9

28
soc/nxp/imx/imx9/imx943/Kconfig.defconfig.mimx94398.a55 Normal file
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@ -0,0 +1,28 @@
# Copyright 2025 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMX94398_A55
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_FLASH := zephyr,flash
config FLASH_SIZE
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
# Enable GIC Safe Configuration to run multiple OSes on Cortex-A Cores
config GIC_SAFE_CONFIG
default y
config MCUX_CORE_SUFFIX
default "_ca55" if SOC_MIMX94398_A55
config NUM_IRQS
default 320
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 24000000
endif

21
soc/nxp/imx/imx9/imx943/Kconfig.soc Normal file
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@ -0,0 +1,21 @@
# Copyright 2025 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_MIMX94398
bool
select SOC_SERIES_IMX9
config SOC_MIMX94398_A55
bool
select SOC_MIMX94398
help
NXP i.MX943 A55
config SOC
default "mimx94398" if SOC_MIMX94398
config SOC_PART_NUMBER_MIMX94398AVKM
bool
config SOC_PART_NUMBER
default "MIMX94398AVKM" if SOC_PART_NUMBER_MIMX94398AVKM

6
soc/nxp/imx/imx9/imx943/a55/CMakeLists.txt Normal file
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@ -0,0 +1,6 @@
# Copyright 2025 NXP
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

31
soc/nxp/imx/imx9/imx943/a55/mmu_regions.c Normal file
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@ -0,0 +1,31 @@
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/arm64/arm_mmu.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_mbox_imx_mu,
(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_lpuart,
(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
};
const struct arm_mmu_config mmu_config = {
.num_regions = ARRAY_SIZE(mmu_regions),
.mmu_regions = mmu_regions,
};

12
soc/nxp/imx/imx9/imx943/a55/soc.h Normal file
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@ -0,0 +1,12 @@
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_NXP_IMX_IMX943_A55_SOC_H_
#define _SOC_NXP_IMX_IMX943_A55_SOC_H_
#include <fsl_device_registers.h>
#endif /* _SOC_NXP_IMX_IMX943_A55_SOC_H_ */

93
soc/nxp/imx/imx9/imx943/pinctrl_soc.h Normal file
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@ -0,0 +1,93 @@
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM64_NXP_IMX943_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM64_NXP_IMX943_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PIN_CONFIG_TYPE_MUX 192
#define PIN_CONFIG_TYPE_CONFIG 193
#define PIN_CONFIG_TYPE_DAISY_ID 194
#define PIN_CONFIG_TYPE_DAISY_CFG 195
#define IOMUXC_MUX_MODE(x) IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)
#define IOMUXC_SION(x) IOMUXC_SW_MUX_CTL_PAD_SION(x)
#define IOMUXC_MUXREG (IOMUXC_BASE)
#define IOMUXC_CFGREG (IOMUXC_BASE + 0x304)
#define IOMUXC_DAISYREG (IOMUXC_BASE + 0x608)
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_OD_SHIFT
#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC_SW_PAD_CTL_PAD_PD_SHIFT
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PU_SHIFT
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL1_SHIFT
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
#define IOMUXC_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define IOMUXC_INPUT_ENABLE(x) ((x >> IOMUXC_INPUT_ENABLE_SHIFT) & 0x1)
#define Z_PINCTRL_IOMUXC_PINCFG_INIT(node_id) \
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
(DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) | \
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
((~(0xffffffff << DT_ENUM_IDX(node_id, drive_strength))) \
<< MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
(DT_PROP(node_id, input_enable) << IOMUXC_INPUT_ENABLE_SHIFT))
/* This struct must be present. It is used by the mcux gpio driver */
struct pinctrl_soc_pinmux {
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
uint32_t input_daisy: 4; /*!< Mux value for SELECT_INPUT_DAISY register */
};
struct pinctrl_soc_pin {
struct pinctrl_soc_pinmux pinmux;
uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
};
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
/* This definition must be present. It is used by the mcux gpio driver */
#define MCUX_IMX_PINMUX(node_id) \
{ \
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
}
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
{ \
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
.pin_ctrl_flags = Z_PINCTRL_IOMUXC_PINCFG_INIT(group_id), \
},
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
Z_PINCTRL_STATE_PIN_INIT)};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM64_NXP_IMX943_PINCTRL_SOC_H_ */

3
soc/nxp/imx/soc.yml
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@ -40,6 +40,9 @@ family:
cpuclusters:
- name: a55
- name: m33
- name: mimx94398
cpuclusters:
- name: a55
- name: mimx9596
cpuclusters:
- name: a55