drivers/espi: ite: Refactor register defines into .c for SoC flexibility
Move register definitions from chip_chipregs.h into espi_it8xxx2.c to make the driver more adaptable to different SoCs. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin
Benjamin Cabé
parent
49595c7309
commit
5f502499e9
4 changed files with 572 additions and 562 deletions
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@ -76,6 +76,578 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
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#define IT8XXX2_ESPI_PUT_FLASH_TAG_MASK GENMASK(7, 4)
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#define IT8XXX2_ESPI_PUT_FLASH_LEN_MASK GENMASK(6, 0)
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/*
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* EC2I bridge registers
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*/
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struct ec2i_regs {
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/* 0x00: Indirect Host I/O Address Register */
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volatile uint8_t IHIOA;
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/* 0x01: Indirect Host Data Register */
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volatile uint8_t IHD;
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/* 0x02: Lock Super I/O Host Access Register */
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volatile uint8_t LSIOHA;
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/* 0x03: Super I/O Access Lock Violation Register */
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volatile uint8_t SIOLV;
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/* 0x04: EC to I-Bus Modules Access Enable Register */
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volatile uint8_t IBMAE;
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/* 0x05: I-Bus Control Register */
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volatile uint8_t IBCTL;
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};
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/* Index list of the host interface registers of PNPCFG */
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enum host_pnpcfg_index {
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/* Logical Device Number */
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HOST_INDEX_LDN = 0x07,
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/* Chip ID Byte 1 */
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HOST_INDEX_CHIPID1 = 0x20,
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/* Chip ID Byte 2 */
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HOST_INDEX_CHIPID2 = 0x21,
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/* Chip Version */
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HOST_INDEX_CHIPVER = 0x22,
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/* Super I/O Control */
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HOST_INDEX_SIOCTRL = 0x23,
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/* Super I/O IRQ Configuration */
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HOST_INDEX_SIOIRQ = 0x25,
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/* Super I/O General Purpose */
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HOST_INDEX_SIOGP = 0x26,
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/* Super I/O Power Mode */
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HOST_INDEX_SIOPWR = 0x2D,
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/* Depth 2 I/O Address */
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HOST_INDEX_D2ADR = 0x2E,
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/* Depth 2 I/O Data */
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HOST_INDEX_D2DAT = 0x2F,
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/* Logical Device Activate Register */
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HOST_INDEX_LDA = 0x30,
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/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
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HOST_INDEX_IOBAD0_MSB = 0x60,
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/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
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HOST_INDEX_IOBAD0_LSB = 0x61,
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/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
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HOST_INDEX_IOBAD1_MSB = 0x62,
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/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
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HOST_INDEX_IOBAD1_LSB = 0x63,
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/* Interrupt Request Number and Wake-Up on IRQ Enabled */
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HOST_INDEX_IRQNUMX = 0x70,
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/* Interrupt Request Type Select */
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HOST_INDEX_IRQTP = 0x71,
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/* DMA Channel Select 0 */
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HOST_INDEX_DMAS0 = 0x74,
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/* DMA Channel Select 1 */
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HOST_INDEX_DMAS1 = 0x75,
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/* Device Specific Logical Device Configuration 1 to 10 */
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HOST_INDEX_DSLDC1 = 0xF0,
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HOST_INDEX_DSLDC2 = 0xF1,
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HOST_INDEX_DSLDC3 = 0xF2,
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HOST_INDEX_DSLDC4 = 0xF3,
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HOST_INDEX_DSLDC5 = 0xF4,
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HOST_INDEX_DSLDC6 = 0xF5,
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HOST_INDEX_DSLDC7 = 0xF6,
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HOST_INDEX_DSLDC8 = 0xF7,
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HOST_INDEX_DSLDC9 = 0xF8,
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HOST_INDEX_DSLDC10 = 0xF9,
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HOST_INDEX_DSLDC11 = 0xFA,
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HOST_INDEX_DSLDC12 = 0xFB,
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HOST_INDEX_DSLDC13 = 0xFD,
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};
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/* List of logical device number (LDN) assignments */
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enum logical_device_number {
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/* Serial Port 1 */
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LDN_UART1 = 0x01,
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/* Serial Port 2 */
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LDN_UART2 = 0x02,
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/* System Wake-Up Control */
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LDN_SWUC = 0x04,
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/* KBC/Mouse Interface */
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LDN_KBC_MOUSE = 0x05,
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/* KBC/Keyboard Interface */
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LDN_KBC_KEYBOARD = 0x06,
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/* Consumer IR */
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LDN_CIR = 0x0A,
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/* Shared Memory/Flash Interface */
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LDN_SMFI = 0x0F,
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/* RTC-like Timer */
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LDN_RTCT = 0x10,
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/* Power Management I/F Channel 1 */
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LDN_PMC1 = 0x11,
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/* Power Management I/F Channel 2 */
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LDN_PMC2 = 0x12,
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/* Serial Peripheral Interface */
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LDN_SSPI = 0x13,
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/* Platform Environment Control Interface */
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LDN_PECI = 0x14,
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/* Power Management I/F Channel 3 */
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LDN_PMC3 = 0x17,
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/* Power Management I/F Channel 4 */
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LDN_PMC4 = 0x18,
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/* Power Management I/F Channel 5 */
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LDN_PMC5 = 0x19,
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};
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/* Structure for initializing PNPCFG via ec2i. */
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struct ec2i_t {
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/* index port */
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enum host_pnpcfg_index index_port;
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/* data port */
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uint8_t data_port;
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};
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/* EC2I access index/data port */
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enum ec2i_access {
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/* index port */
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EC2I_ACCESS_INDEX = 0,
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/* data port */
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EC2I_ACCESS_DATA = 1,
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};
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/* EC to I-Bus Access Enabled */
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#define EC2I_IBCTL_CSAE BIT(0)
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/* EC Read from I-Bus */
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#define EC2I_IBCTL_CRIB BIT(1)
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/* EC Write to I-Bus */
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#define EC2I_IBCTL_CWIB BIT(2)
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#define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB)
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/* PNPCFG Register EC Access Enable */
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#define EC2I_IBMAE_CFGAE BIT(0)
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/*
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* KBC registers
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*/
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struct kbc_regs {
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/* 0x00: KBC Host Interface Control Register */
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volatile uint8_t KBHICR;
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/* 0x01: Reserved1 */
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volatile uint8_t reserved1;
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/* 0x02: KBC Interrupt Control Register */
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volatile uint8_t KBIRQR;
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/* 0x03: Reserved2 */
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volatile uint8_t reserved2;
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/* 0x04: KBC Host Interface Keyboard/Mouse Status Register */
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volatile uint8_t KBHISR;
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/* 0x05: Reserved3 */
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volatile uint8_t reserved3;
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/* 0x06: KBC Host Interface Keyboard Data Output Register */
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volatile uint8_t KBHIKDOR;
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/* 0x07: Reserved4 */
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volatile uint8_t reserved4;
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/* 0x08: KBC Host Interface Mouse Data Output Register */
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volatile uint8_t KBHIMDOR;
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/* 0x09: Reserved5 */
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volatile uint8_t reserved5;
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/* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */
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volatile uint8_t KBHIDIR;
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};
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/* Output Buffer Full */
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#define KBC_KBHISR_OBF BIT(0)
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/* Input Buffer Full */
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#define KBC_KBHISR_IBF BIT(1)
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/* A2 Address (A2) */
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#define KBC_KBHISR_A2_ADDR BIT(3)
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#define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF | KBC_KBHISR_A2_ADDR)
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/* Clear Output Buffer Full */
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#define KBC_KBHICR_COBF BIT(6)
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/* IBF/OBF Clear Mode Enable */
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#define KBC_KBHICR_IBFOBFCME BIT(5)
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/* Input Buffer Full CPU Interrupt Enable */
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#define KBC_KBHICR_IBFCIE BIT(3)
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/* Output Buffer Empty CPU Interrupt Enable */
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#define KBC_KBHICR_OBECIE BIT(2)
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/* Output Buffer Full Mouse Interrupt Enable */
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#define KBC_KBHICR_OBFMIE BIT(1)
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/* Output Buffer Full Keyboard Interrupt Enable */
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#define KBC_KBHICR_OBFKIE BIT(0)
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/*
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* PMC registers
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*/
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struct pmc_regs {
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/* 0x00: Host Interface PM Channel 1 Status */
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volatile uint8_t PM1STS;
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/* 0x01: Host Interface PM Channel 1 Data Out Port */
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volatile uint8_t PM1DO;
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/* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */
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volatile uint8_t PM1DOSCI;
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/* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */
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volatile uint8_t PM1DOSMI;
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/* 0x04: Host Interface PM Channel 1 Data In Port */
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volatile uint8_t PM1DI;
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/* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */
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volatile uint8_t PM1DISCI;
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/* 0x06: Host Interface PM Channel 1 Control */
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volatile uint8_t PM1CTL;
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/* 0x07: Host Interface PM Channel 1 Interrupt Control */
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volatile uint8_t PM1IC;
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/* 0x08: Host Interface PM Channel 1 Interrupt Enable */
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volatile uint8_t PM1IE;
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/* 0x09-0x0f: Reserved1 */
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volatile uint8_t reserved1[7];
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/* 0x10: Host Interface PM Channel 2 Status */
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volatile uint8_t PM2STS;
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/* 0x11: Host Interface PM Channel 2 Data Out Port */
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volatile uint8_t PM2DO;
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/* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */
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volatile uint8_t PM2DOSCI;
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/* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */
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volatile uint8_t PM2DOSMI;
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/* 0x14: Host Interface PM Channel 2 Data In Port */
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volatile uint8_t PM2DI;
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/* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */
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volatile uint8_t PM2DISCI;
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/* 0x16: Host Interface PM Channel 2 Control */
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volatile uint8_t PM2CTL;
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/* 0x17: Host Interface PM Channel 2 Interrupt Control */
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volatile uint8_t PM2IC;
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/* 0x18: Host Interface PM Channel 2 Interrupt Enable */
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volatile uint8_t PM2IE;
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/* 0x19: Mailbox Control */
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volatile uint8_t MBXCTRL;
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/* 0x1a-0x1f: Reserved2 */
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volatile uint8_t reserved2[6];
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/* 0x20-0xff: Reserved3 */
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volatile uint8_t reserved3[0xe0];
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};
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/* Input Buffer Full Interrupt Enable */
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#define PMC_PM1CTL_IBFIE BIT(0)
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/* Output Buffer Full */
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#define PMC_PM1STS_OBF BIT(0)
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/* Input Buffer Full */
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#define PMC_PM1STS_IBF BIT(1)
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/* General Purpose Flag */
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#define PMC_PM1STS_GPF BIT(2)
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/* A2 Address (A2) */
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#define PMC_PM1STS_A2_ADDR BIT(3)
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/* PMC2 Input Buffer Full Interrupt Enable */
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#define PMC_PM2CTL_IBFIE BIT(0)
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/* General Purpose Flag */
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#define PMC_PM2STS_GPF BIT(2)
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/*
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* Dedicated Interrupt
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* 0b:
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* INT3: PMC Output Buffer Empty Int
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* INT25: PMC Input Buffer Full Int
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* 1b:
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* INT3: PMC1 Output Buffer Empty Int
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* INT25: PMC1 Input Buffer Full Int
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* INT26: PMC2 Output Buffer Empty Int
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* INT27: PMC2 Input Buffer Full Int
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*/
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#define PMC_MBXCTRL_DINT BIT(5)
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/*
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* eSPI slave registers
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*/
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struct espi_slave_regs {
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/* 0x00-0x03: Reserved1 */
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volatile uint8_t reserved1[4];
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/* 0x04: General Capabilities and Configuration 0 */
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volatile uint8_t GCAPCFG0;
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/* 0x05: General Capabilities and Configuration 1 */
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volatile uint8_t GCAPCFG1;
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/* 0x06: General Capabilities and Configuration 2 */
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volatile uint8_t GCAPCFG2;
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/* 0x07: General Capabilities and Configuration 3 */
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volatile uint8_t GCAPCFG3;
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/* Channel 0 (Peripheral Channel) Capabilities and Configurations */
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/* 0x08: Channel 0 Capabilities and Configuration 0 */
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volatile uint8_t CH_PC_CAPCFG0;
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/* 0x09: Channel 0 Capabilities and Configuration 1 */
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volatile uint8_t CH_PC_CAPCFG1;
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/* 0x0A: Channel 0 Capabilities and Configuration 2 */
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volatile uint8_t CH_PC_CAPCFG2;
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/* 0x0B: Channel 0 Capabilities and Configuration 3 */
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volatile uint8_t CH_PC_CAPCFG3;
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/* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */
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/* 0x0C: Channel 1 Capabilities and Configuration 0 */
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volatile uint8_t CH_VW_CAPCFG0;
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/* 0x0D: Channel 1 Capabilities and Configuration 1 */
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volatile uint8_t CH_VW_CAPCFG1;
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/* 0x0E: Channel 1 Capabilities and Configuration 2 */
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volatile uint8_t CH_VW_CAPCFG2;
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/* 0x0F: Channel 1 Capabilities and Configuration 3 */
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volatile uint8_t CH_VW_CAPCFG3;
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/* Channel 2 (OOB Message Channel) Capabilities and Configurations */
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/* 0x10: Channel 2 Capabilities and Configuration 0 */
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volatile uint8_t CH_OOB_CAPCFG0;
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/* 0x11: Channel 2 Capabilities and Configuration 1 */
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volatile uint8_t CH_OOB_CAPCFG1;
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/* 0x12: Channel 2 Capabilities and Configuration 2 */
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volatile uint8_t CH_OOB_CAPCFG2;
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/* 0x13: Channel 2 Capabilities and Configuration 3 */
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volatile uint8_t CH_OOB_CAPCFG3;
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/* Channel 3 (Flash Access Channel) Capabilities and Configurations */
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/* 0x14: Channel 3 Capabilities and Configuration 0 */
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volatile uint8_t CH_FLASH_CAPCFG0;
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/* 0x15: Channel 3 Capabilities and Configuration 1 */
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volatile uint8_t CH_FLASH_CAPCFG1;
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/* 0x16: Channel 3 Capabilities and Configuration 2 */
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volatile uint8_t CH_FLASH_CAPCFG2;
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/* 0x17: Channel 3 Capabilities and Configuration 3 */
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volatile uint8_t CH_FLASH_CAPCFG3;
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/* Channel 3 Capabilities and Configurations 2 */
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/* 0x18: Channel 3 Capabilities and Configuration 2-0 */
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volatile uint8_t CH_FLASH_CAPCFG2_0;
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/* 0x19: Channel 3 Capabilities and Configuration 2-1 */
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volatile uint8_t CH_FLASH_CAPCFG2_1;
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/* 0x1A: Channel 3 Capabilities and Configuration 2-2 */
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volatile uint8_t CH_FLASH_CAPCFG2_2;
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/* 0x1B: Channel 3 Capabilities and Configuration 2-3 */
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volatile uint8_t CH_FLASH_CAPCFG2_3;
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/* 0x1c-0x1f: Reserved2 */
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volatile uint8_t reserved2[4];
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/* 0x20-0x8f: Reserved3 */
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volatile uint8_t reserved3[0x70];
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/* 0x90: eSPI PC Control 0 */
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volatile uint8_t ESPCTRL0;
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/* 0x91: eSPI PC Control 1 */
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volatile uint8_t ESPCTRL1;
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/* 0x92: eSPI PC Control 2 */
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volatile uint8_t ESPCTRL2;
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/* 0x93: eSPI PC Control 3 */
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volatile uint8_t ESPCTRL3;
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/* 0x94: eSPI PC Control 4 */
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volatile uint8_t ESPCTRL4;
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/* 0x95: eSPI PC Control 5 */
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volatile uint8_t ESPCTRL5;
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/* 0x96: eSPI PC Control 6 */
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volatile uint8_t ESPCTRL6;
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/* 0x97: eSPI PC Control 7 */
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volatile uint8_t ESPCTRL7;
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/* 0x98-0x9f: Reserved4 */
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volatile uint8_t reserved4[8];
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/* 0xa0: eSPI General Control 0 */
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volatile uint8_t ESGCTRL0;
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/* 0xa1: eSPI General Control 1 */
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volatile uint8_t ESGCTRL1;
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/* 0xa2: eSPI General Control 2 */
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volatile uint8_t ESGCTRL2;
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/* 0xa3: eSPI General Control 3 */
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volatile uint8_t ESGCTRL3;
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/* 0xa4-0xaf: Reserved5 */
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volatile uint8_t reserved5[12];
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/* 0xb0: eSPI Upstream Control 0 */
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volatile uint8_t ESUCTRL0;
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/* 0xb1: eSPI Upstream Control 1 */
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volatile uint8_t ESUCTRL1;
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/* 0xb2: eSPI Upstream Control 2 */
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volatile uint8_t ESUCTRL2;
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/* 0xb3: eSPI Upstream Control 3 */
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volatile uint8_t ESUCTRL3;
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/* 0xb4-0xb5: Reserved6 */
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volatile uint8_t reserved6[2];
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/* 0xb6: eSPI Upstream Control 6 */
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volatile uint8_t ESUCTRL6;
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/* 0xb7: eSPI Upstream Control 7 */
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volatile uint8_t ESUCTRL7;
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/* 0xb8: eSPI Upstream Control 8 */
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volatile uint8_t ESUCTRL8;
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/* 0xb9-0xbf: Reserved7 */
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volatile uint8_t reserved7[7];
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/* 0xc0: eSPI OOB Control 0 */
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volatile uint8_t ESOCTRL0;
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/* 0xc1: eSPI OOB Control 1 */
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volatile uint8_t ESOCTRL1;
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/* 0xc2-0xc3: Reserved8 */
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volatile uint8_t reserved8[2];
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/* 0xc4: eSPI OOB Control 4 */
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volatile uint8_t ESOCTRL4;
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/* 0xc5-0xcf: Reserved9 */
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volatile uint8_t reserved9[11];
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/* 0xd0: eSPI SAFS Control 0 */
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volatile uint8_t ESPISAFSC0;
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/* 0xd1: eSPI SAFS Control 1 */
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volatile uint8_t ESPISAFSC1;
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/* 0xd2: eSPI SAFS Control 2 */
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volatile uint8_t ESPISAFSC2;
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/* 0xd3: eSPI SAFS Control 3 */
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volatile uint8_t ESPISAFSC3;
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/* 0xd4: eSPI SAFS Control 4 */
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volatile uint8_t ESPISAFSC4;
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/* 0xd5: eSPI SAFS Control 5 */
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volatile uint8_t ESPISAFSC5;
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/* 0xd6: eSPI SAFS Control 6 */
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volatile uint8_t ESPISAFSC6;
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/* 0xd7: eSPI SAFS Control 7 */
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volatile uint8_t ESPISAFSC7;
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};
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/*
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* eSPI VW registers
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*/
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struct espi_vw_regs {
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/* 0x00-0x7f: VW index */
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volatile uint8_t VW_INDEX[0x80];
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/* 0x80-0x8f: Reserved1 */
|
||||
volatile uint8_t reserved1[0x10];
|
||||
/* 0x90: VW Control 0 */
|
||||
volatile uint8_t VWCTRL0;
|
||||
/* 0x91: VW Control 1 */
|
||||
volatile uint8_t VWCTRL1;
|
||||
/* 0x92: VW Control 2 */
|
||||
volatile uint8_t VWCTRL2;
|
||||
/* 0x93: VW Control 3 */
|
||||
volatile uint8_t VWCTRL3;
|
||||
/* 0x94: Reserved2 */
|
||||
volatile uint8_t reserved2;
|
||||
/* 0x95: VW Control 5 */
|
||||
volatile uint8_t VWCTRL5;
|
||||
/* 0x96: VW Control 6 */
|
||||
volatile uint8_t VWCTRL6;
|
||||
/* 0x97: VW Control 7 */
|
||||
volatile uint8_t VWCTRL7;
|
||||
/* 0x98-0x99: Reserved3 */
|
||||
volatile uint8_t reserved3[2];
|
||||
};
|
||||
|
||||
#define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80
|
||||
/*
|
||||
* eSPI Queue 0 registers
|
||||
*/
|
||||
struct espi_queue0_regs {
|
||||
/* 0x00-0x3f: PUT_PC Data Byte 0-63 */
|
||||
volatile uint8_t PUT_PC_DATA[0x40];
|
||||
/* 0x40-0x7f: Reserved1 */
|
||||
volatile uint8_t reserved1[0x40];
|
||||
/* 0x80-0xcf: PUT_OOB Data Byte 0-79 */
|
||||
volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
|
||||
};
|
||||
|
||||
/*
|
||||
* eSPI Queue 1 registers
|
||||
*/
|
||||
struct espi_queue1_regs {
|
||||
/* 0x00-0x4f: Upstream Data Byte 0-79 */
|
||||
volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
|
||||
/* 0x50-0x7f: Reserved1 */
|
||||
volatile uint8_t reserved1[0x30];
|
||||
/* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */
|
||||
volatile uint8_t PUT_FLASH_NP_DATA[0x40];
|
||||
};
|
||||
|
||||
/* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */
|
||||
#define SMFI_H2RAMPS BIT(4)
|
||||
/* H2RAM Window 1 Enable */
|
||||
#define SMFI_H2RAMW1E BIT(1)
|
||||
/* H2RAM Window 0 Enable */
|
||||
#define SMFI_H2RAMW0E BIT(0)
|
||||
/* Host RAM Window x Write Protect Enable (All protected) */
|
||||
#define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4))
|
||||
|
||||
/* Accept Port 80h Cycle */
|
||||
#define IT8XXX2_GCTRL_ACP80 BIT(6)
|
||||
/* Accept Port 81h Cycle */
|
||||
#define IT8XXX2_GCTRL_ACP81 BIT(3)
|
||||
|
||||
#define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2
|
||||
#define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1
|
||||
#define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS)
|
||||
|
||||
/*
|
||||
* VCC Detector Option.
|
||||
* bit[7-6] = 1: The VCC power status is treated as power-on.
|
||||
* The VCC supply of eSPI and related functions (EC2I, KBC, PMC and
|
||||
* PECI). It means VCC should be logic high before using these
|
||||
* functions, or firmware treats VCC logic high.
|
||||
*/
|
||||
#define IT8XXX2_GCTRL_VCCDO_MASK (BIT(6) | BIT(7))
|
||||
#define IT8XXX2_GCTRL_VCCDO_VCC_ON BIT(6)
|
||||
/*
|
||||
* bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH
|
||||
* register and WRST#.
|
||||
*/
|
||||
#define IT8XXX2_GCTRL_HGRST BIT(3)
|
||||
/* bit[2] = 1: Enable global reset. */
|
||||
#define IT8XXX2_GCTRL_GRST BIT(2)
|
||||
|
||||
/*
|
||||
* IT8XXX2 register structure size/offset checking macro function to mitigate
|
||||
* the risk of unexpected compiling results.
|
||||
*/
|
||||
#define IT8XXX2_ESPI_REG_SIZE_CHECK(reg_def, size) \
|
||||
BUILD_ASSERT(sizeof(struct reg_def) == size, "Failed in size check of register " \
|
||||
"structure!")
|
||||
#define IT8XXX2_ESPI_REG_OFFSET_CHECK(reg_def, member, offset) \
|
||||
BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
|
||||
"Failed in offset check of register structure member!")
|
||||
|
||||
/* EC2I register structure check */
|
||||
IT8XXX2_ESPI_REG_SIZE_CHECK(ec2i_regs, 0x06);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(ec2i_regs, IHIOA, 0x00);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(ec2i_regs, IHD, 0x01);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(ec2i_regs, LSIOHA, 0x02);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(ec2i_regs, IBMAE, 0x04);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(ec2i_regs, IBCTL, 0x05);
|
||||
|
||||
/* KBC register structure check */
|
||||
IT8XXX2_ESPI_REG_SIZE_CHECK(kbc_regs, 0x0b);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(kbc_regs, KBHICR, 0x00);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(kbc_regs, KBIRQR, 0x02);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(kbc_regs, KBHISR, 0x04);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(kbc_regs, KBHIKDOR, 0x06);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(kbc_regs, KBHIMDOR, 0x08);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(kbc_regs, KBHIDIR, 0x0a);
|
||||
|
||||
/* PMC register structure check */
|
||||
IT8XXX2_ESPI_REG_SIZE_CHECK(pmc_regs, 0x100);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM1STS, 0x00);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM1DO, 0x01);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM1DI, 0x04);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM1CTL, 0x06);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2STS, 0x10);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2DO, 0x11);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2DI, 0x14);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2CTL, 0x16);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, MBXCTRL, 0x19);
|
||||
|
||||
/* eSPI slave register structure check */
|
||||
IT8XXX2_ESPI_REG_SIZE_CHECK(espi_slave_regs, 0xd8);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, GCAPCFG1, 0x05);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, CH_PC_CAPCFG3, 0x0b);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, CH_VW_CAPCFG3, 0x0f);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, CH_OOB_CAPCFG3, 0x13);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, CH_FLASH_CAPCFG3, 0x17);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, CH_FLASH_CAPCFG2_3, 0x1b);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESPCTRL0, 0x90);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL0, 0xa0);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL1, 0xa1);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL2, 0xa2);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESUCTRL0, 0xb0);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESOCTRL0, 0xc0);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESOCTRL1, 0xc1);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESPISAFSC0, 0xd0);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_slave_regs, ESPISAFSC7, 0xd7);
|
||||
|
||||
/* eSPI vw register structure check */
|
||||
IT8XXX2_ESPI_REG_SIZE_CHECK(espi_vw_regs, 0x9a);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_vw_regs, VW_INDEX, 0x00);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_vw_regs, VWCTRL0, 0x90);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_vw_regs, VWCTRL1, 0x91);
|
||||
|
||||
/* eSPI Queue 0 registers structure check */
|
||||
IT8XXX2_ESPI_REG_SIZE_CHECK(espi_queue0_regs, 0xd0);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_queue0_regs, PUT_OOB_DATA, 0x80);
|
||||
|
||||
/* eSPI Queue 1 registers structure check */
|
||||
IT8XXX2_ESPI_REG_SIZE_CHECK(espi_queue1_regs, 0xc0);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_queue1_regs, UPSTREAM_DATA, 0x00);
|
||||
IT8XXX2_ESPI_REG_OFFSET_CHECK(espi_queue1_regs, PUT_FLASH_NP_DATA, 0x80);
|
||||
|
||||
struct espi_it8xxx2_wuc {
|
||||
/* WUC control device structure */
|
||||
const struct device *wucs;
|
||||
|
|
|
|||
|
|
@ -189,9 +189,6 @@ struct gpio_it51xxx_regs {
|
|||
/* 0x00: General Control */
|
||||
#define IT51XXX_GPIO_LPCRSTEN (BIT(2) | BIT(1))
|
||||
#define ITE_EC_GPIO_LPCRSTEN IT51XXX_GPIO_LPCRSTEN
|
||||
#define IT51XXX_GPIO_GCR_ESPI_RST_D2 0x2
|
||||
#define IT51XXX_GPIO_GCR_ESPI_RST_POS 1
|
||||
#define IT51XXX_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT51XXX_GPIO_GCR_ESPI_RST_POS)
|
||||
/* 0xF0: General Control 1 */
|
||||
#define IT51XXX_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2)
|
||||
#define IT51XXX_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0)
|
||||
|
|
|
|||
|
|
@ -24,68 +24,6 @@ IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_HRAMW0AAS, 0x5d);
|
|||
IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_HRAMW1AAS, 0x5e);
|
||||
IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_FLHCTRL6R, 0xa2);
|
||||
|
||||
/* EC2I register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(ec2i_regs, 0x06);
|
||||
IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IHIOA, 0x00);
|
||||
IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IHD, 0x01);
|
||||
IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, LSIOHA, 0x02);
|
||||
IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IBMAE, 0x04);
|
||||
IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IBCTL, 0x05);
|
||||
|
||||
/* KBC register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(kbc_regs, 0x0b);
|
||||
IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHICR, 0x00);
|
||||
IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBIRQR, 0x02);
|
||||
IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHISR, 0x04);
|
||||
IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHIKDOR, 0x06);
|
||||
IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHIMDOR, 0x08);
|
||||
IT8XXX2_REG_OFFSET_CHECK(kbc_regs, KBHIDIR, 0x0a);
|
||||
|
||||
/* PMC register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(pmc_regs, 0x100);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1STS, 0x00);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1DO, 0x01);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1DI, 0x04);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1CTL, 0x06);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2STS, 0x10);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2DO, 0x11);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2DI, 0x14);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2CTL, 0x16);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, MBXCTRL, 0x19);
|
||||
|
||||
/* eSPI slave register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(espi_slave_regs, 0xd8);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, GCAPCFG1, 0x05);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_PC_CAPCFG3, 0x0b);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_VW_CAPCFG3, 0x0f);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_OOB_CAPCFG3, 0x13);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_FLASH_CAPCFG3, 0x17);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, CH_FLASH_CAPCFG2_3, 0x1b);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESPCTRL0, 0x90);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL0, 0xa0);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL1, 0xa1);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESGCTRL2, 0xa2);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESUCTRL0, 0xb0);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESOCTRL0, 0xc0);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESOCTRL1, 0xc1);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESPISAFSC0, 0xd0);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_slave_regs, ESPISAFSC7, 0xd7);
|
||||
|
||||
/* eSPI vw register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(espi_vw_regs, 0x9a);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_vw_regs, VW_INDEX, 0x00);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_vw_regs, VWCTRL0, 0x90);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_vw_regs, VWCTRL1, 0x91);
|
||||
|
||||
/* eSPI Queue 0 registers structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(espi_queue0_regs, 0xd0);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_queue0_regs, PUT_OOB_DATA, 0x80);
|
||||
|
||||
/* eSPI Queue 1 registers structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(espi_queue1_regs, 0xc0);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_queue1_regs, UPSTREAM_DATA, 0x00);
|
||||
IT8XXX2_REG_OFFSET_CHECK(espi_queue1_regs, PUT_FLASH_NP_DATA, 0x80);
|
||||
|
||||
/* GPIO register structure check */
|
||||
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
|
||||
IT8XXX2_REG_SIZE_CHECK(gpio_it8xxx2_regs, 0x100);
|
||||
|
|
|
|||
|
|
@ -913,15 +913,6 @@ struct smfi_it8xxx2_regs {
|
|||
/* Scratch SRAM enable */
|
||||
#define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3)
|
||||
|
||||
/* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */
|
||||
#define SMFI_H2RAMPS BIT(4)
|
||||
/* H2RAM Window 1 Enable */
|
||||
#define SMFI_H2RAMW1E BIT(1)
|
||||
/* H2RAM Window 0 Enable */
|
||||
#define SMFI_H2RAMW0E BIT(0)
|
||||
|
||||
/* Host RAM Window x Write Protect Enable (All protected) */
|
||||
#define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4))
|
||||
/* 0x42: Scratch SRAM 0 address high byte */
|
||||
#define SCARH_ADDR_BIT19 BIT(7)
|
||||
#define SCARH_ENABLE BIT(3)
|
||||
|
|
@ -1094,9 +1085,6 @@ struct gpio_it8xxx2_regs {
|
|||
/* 0x00: General Control */
|
||||
#define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1))
|
||||
#define ITE_EC_GPIO_LPCRSTEN IT8XXX2_GPIO_LPCRSTEN
|
||||
#define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2
|
||||
#define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1
|
||||
#define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS)
|
||||
/* 0xF0: General Control 1 */
|
||||
#define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2)
|
||||
#define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0)
|
||||
|
|
@ -1661,32 +1649,11 @@ struct gctrl_it8xxx2_regs {
|
|||
#define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0)
|
||||
/* 0x5D: RISCV ILM Configuration 0 */
|
||||
#define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0)
|
||||
/* Accept Port 80h Cycle */
|
||||
#define IT8XXX2_GCTRL_ACP80 BIT(6)
|
||||
/* Accept Port 81h Cycle */
|
||||
#define IT8XXX2_GCTRL_ACP81 BIT(3)
|
||||
/* USB Debug Enable */
|
||||
#define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7)
|
||||
/* USB Pad Power-On Enable */
|
||||
#define IT8XXX2_GCTRL_PMER2_USB_PAD_EN BIT(7)
|
||||
|
||||
/*
|
||||
* VCC Detector Option.
|
||||
* bit[7-6] = 1: The VCC power status is treated as power-on.
|
||||
* The VCC supply of eSPI and related functions (EC2I, KBC, PMC and
|
||||
* PECI). It means VCC should be logic high before using these
|
||||
* functions, or firmware treats VCC logic high.
|
||||
*/
|
||||
#define IT8XXX2_GCTRL_VCCDO_MASK (BIT(6) | BIT(7))
|
||||
#define IT8XXX2_GCTRL_VCCDO_VCC_ON BIT(6)
|
||||
/*
|
||||
* bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH
|
||||
* register and WRST#.
|
||||
*/
|
||||
#define IT8XXX2_GCTRL_HGRST BIT(3)
|
||||
/* bit[2] = 1: Enable global reset. */
|
||||
#define IT8XXX2_GCTRL_GRST BIT(2)
|
||||
|
||||
/**
|
||||
*
|
||||
* (22xxh) Battery-backed SRAM (BRAM) registers
|
||||
|
|
@ -1705,470 +1672,6 @@ enum bram_indices {
|
|||
};
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/*
|
||||
* EC2I bridge registers
|
||||
*/
|
||||
struct ec2i_regs {
|
||||
/* 0x00: Indirect Host I/O Address Register */
|
||||
volatile uint8_t IHIOA;
|
||||
/* 0x01: Indirect Host Data Register */
|
||||
volatile uint8_t IHD;
|
||||
/* 0x02: Lock Super I/O Host Access Register */
|
||||
volatile uint8_t LSIOHA;
|
||||
/* 0x03: Super I/O Access Lock Violation Register */
|
||||
volatile uint8_t SIOLV;
|
||||
/* 0x04: EC to I-Bus Modules Access Enable Register */
|
||||
volatile uint8_t IBMAE;
|
||||
/* 0x05: I-Bus Control Register */
|
||||
volatile uint8_t IBCTL;
|
||||
};
|
||||
|
||||
/* Index list of the host interface registers of PNPCFG */
|
||||
enum host_pnpcfg_index {
|
||||
/* Logical Device Number */
|
||||
HOST_INDEX_LDN = 0x07,
|
||||
/* Chip ID Byte 1 */
|
||||
HOST_INDEX_CHIPID1 = 0x20,
|
||||
/* Chip ID Byte 2 */
|
||||
HOST_INDEX_CHIPID2 = 0x21,
|
||||
/* Chip Version */
|
||||
HOST_INDEX_CHIPVER = 0x22,
|
||||
/* Super I/O Control */
|
||||
HOST_INDEX_SIOCTRL = 0x23,
|
||||
/* Super I/O IRQ Configuration */
|
||||
HOST_INDEX_SIOIRQ = 0x25,
|
||||
/* Super I/O General Purpose */
|
||||
HOST_INDEX_SIOGP = 0x26,
|
||||
/* Super I/O Power Mode */
|
||||
HOST_INDEX_SIOPWR = 0x2D,
|
||||
/* Depth 2 I/O Address */
|
||||
HOST_INDEX_D2ADR = 0x2E,
|
||||
/* Depth 2 I/O Data */
|
||||
HOST_INDEX_D2DAT = 0x2F,
|
||||
/* Logical Device Activate Register */
|
||||
HOST_INDEX_LDA = 0x30,
|
||||
/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
|
||||
HOST_INDEX_IOBAD0_MSB = 0x60,
|
||||
/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
|
||||
HOST_INDEX_IOBAD0_LSB = 0x61,
|
||||
/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
|
||||
HOST_INDEX_IOBAD1_MSB = 0x62,
|
||||
/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
|
||||
HOST_INDEX_IOBAD1_LSB = 0x63,
|
||||
/* Interrupt Request Number and Wake-Up on IRQ Enabled */
|
||||
HOST_INDEX_IRQNUMX = 0x70,
|
||||
/* Interrupt Request Type Select */
|
||||
HOST_INDEX_IRQTP = 0x71,
|
||||
/* DMA Channel Select 0 */
|
||||
HOST_INDEX_DMAS0 = 0x74,
|
||||
/* DMA Channel Select 1 */
|
||||
HOST_INDEX_DMAS1 = 0x75,
|
||||
/* Device Specific Logical Device Configuration 1 to 10 */
|
||||
HOST_INDEX_DSLDC1 = 0xF0,
|
||||
HOST_INDEX_DSLDC2 = 0xF1,
|
||||
HOST_INDEX_DSLDC3 = 0xF2,
|
||||
HOST_INDEX_DSLDC4 = 0xF3,
|
||||
HOST_INDEX_DSLDC5 = 0xF4,
|
||||
HOST_INDEX_DSLDC6 = 0xF5,
|
||||
HOST_INDEX_DSLDC7 = 0xF6,
|
||||
HOST_INDEX_DSLDC8 = 0xF7,
|
||||
HOST_INDEX_DSLDC9 = 0xF8,
|
||||
HOST_INDEX_DSLDC10 = 0xF9,
|
||||
};
|
||||
|
||||
/* List of logical device number (LDN) assignments */
|
||||
enum logical_device_number {
|
||||
/* Serial Port 1 */
|
||||
LDN_UART1 = 0x01,
|
||||
/* Serial Port 2 */
|
||||
LDN_UART2 = 0x02,
|
||||
/* System Wake-Up Control */
|
||||
LDN_SWUC = 0x04,
|
||||
/* KBC/Mouse Interface */
|
||||
LDN_KBC_MOUSE = 0x05,
|
||||
/* KBC/Keyboard Interface */
|
||||
LDN_KBC_KEYBOARD = 0x06,
|
||||
/* Consumer IR */
|
||||
LDN_CIR = 0x0A,
|
||||
/* Shared Memory/Flash Interface */
|
||||
LDN_SMFI = 0x0F,
|
||||
/* RTC-like Timer */
|
||||
LDN_RTCT = 0x10,
|
||||
/* Power Management I/F Channel 1 */
|
||||
LDN_PMC1 = 0x11,
|
||||
/* Power Management I/F Channel 2 */
|
||||
LDN_PMC2 = 0x12,
|
||||
/* Serial Peripheral Interface */
|
||||
LDN_SSPI = 0x13,
|
||||
/* Platform Environment Control Interface */
|
||||
LDN_PECI = 0x14,
|
||||
/* Power Management I/F Channel 3 */
|
||||
LDN_PMC3 = 0x17,
|
||||
/* Power Management I/F Channel 4 */
|
||||
LDN_PMC4 = 0x18,
|
||||
/* Power Management I/F Channel 5 */
|
||||
LDN_PMC5 = 0x19,
|
||||
};
|
||||
|
||||
/* Structure for initializing PNPCFG via ec2i. */
|
||||
struct ec2i_t {
|
||||
/* index port */
|
||||
enum host_pnpcfg_index index_port;
|
||||
/* data port */
|
||||
uint8_t data_port;
|
||||
};
|
||||
|
||||
/* EC2I access index/data port */
|
||||
enum ec2i_access {
|
||||
/* index port */
|
||||
EC2I_ACCESS_INDEX = 0,
|
||||
/* data port */
|
||||
EC2I_ACCESS_DATA = 1,
|
||||
};
|
||||
|
||||
/* EC to I-Bus Access Enabled */
|
||||
#define EC2I_IBCTL_CSAE BIT(0)
|
||||
/* EC Read from I-Bus */
|
||||
#define EC2I_IBCTL_CRIB BIT(1)
|
||||
/* EC Write to I-Bus */
|
||||
#define EC2I_IBCTL_CWIB BIT(2)
|
||||
#define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB)
|
||||
|
||||
/* PNPCFG Register EC Access Enable */
|
||||
#define EC2I_IBMAE_CFGAE BIT(0)
|
||||
|
||||
/*
|
||||
* KBC registers
|
||||
*/
|
||||
struct kbc_regs {
|
||||
/* 0x00: KBC Host Interface Control Register */
|
||||
volatile uint8_t KBHICR;
|
||||
/* 0x01: Reserved1 */
|
||||
volatile uint8_t reserved1;
|
||||
/* 0x02: KBC Interrupt Control Register */
|
||||
volatile uint8_t KBIRQR;
|
||||
/* 0x03: Reserved2 */
|
||||
volatile uint8_t reserved2;
|
||||
/* 0x04: KBC Host Interface Keyboard/Mouse Status Register */
|
||||
volatile uint8_t KBHISR;
|
||||
/* 0x05: Reserved3 */
|
||||
volatile uint8_t reserved3;
|
||||
/* 0x06: KBC Host Interface Keyboard Data Output Register */
|
||||
volatile uint8_t KBHIKDOR;
|
||||
/* 0x07: Reserved4 */
|
||||
volatile uint8_t reserved4;
|
||||
/* 0x08: KBC Host Interface Mouse Data Output Register */
|
||||
volatile uint8_t KBHIMDOR;
|
||||
/* 0x09: Reserved5 */
|
||||
volatile uint8_t reserved5;
|
||||
/* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */
|
||||
volatile uint8_t KBHIDIR;
|
||||
};
|
||||
|
||||
/* Output Buffer Full */
|
||||
#define KBC_KBHISR_OBF BIT(0)
|
||||
/* Input Buffer Full */
|
||||
#define KBC_KBHISR_IBF BIT(1)
|
||||
/* A2 Address (A2) */
|
||||
#define KBC_KBHISR_A2_ADDR BIT(3)
|
||||
#define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF | KBC_KBHISR_A2_ADDR)
|
||||
|
||||
/* Clear Output Buffer Full */
|
||||
#define KBC_KBHICR_COBF BIT(6)
|
||||
/* IBF/OBF Clear Mode Enable */
|
||||
#define KBC_KBHICR_IBFOBFCME BIT(5)
|
||||
/* Input Buffer Full CPU Interrupt Enable */
|
||||
#define KBC_KBHICR_IBFCIE BIT(3)
|
||||
/* Output Buffer Empty CPU Interrupt Enable */
|
||||
#define KBC_KBHICR_OBECIE BIT(2)
|
||||
/* Output Buffer Full Mouse Interrupt Enable */
|
||||
#define KBC_KBHICR_OBFMIE BIT(1)
|
||||
/* Output Buffer Full Keyboard Interrupt Enable */
|
||||
#define KBC_KBHICR_OBFKIE BIT(0)
|
||||
|
||||
/*
|
||||
* PMC registers
|
||||
*/
|
||||
struct pmc_regs {
|
||||
/* 0x00: Host Interface PM Channel 1 Status */
|
||||
volatile uint8_t PM1STS;
|
||||
/* 0x01: Host Interface PM Channel 1 Data Out Port */
|
||||
volatile uint8_t PM1DO;
|
||||
/* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */
|
||||
volatile uint8_t PM1DOSCI;
|
||||
/* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */
|
||||
volatile uint8_t PM1DOSMI;
|
||||
/* 0x04: Host Interface PM Channel 1 Data In Port */
|
||||
volatile uint8_t PM1DI;
|
||||
/* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */
|
||||
volatile uint8_t PM1DISCI;
|
||||
/* 0x06: Host Interface PM Channel 1 Control */
|
||||
volatile uint8_t PM1CTL;
|
||||
/* 0x07: Host Interface PM Channel 1 Interrupt Control */
|
||||
volatile uint8_t PM1IC;
|
||||
/* 0x08: Host Interface PM Channel 1 Interrupt Enable */
|
||||
volatile uint8_t PM1IE;
|
||||
/* 0x09-0x0f: Reserved1 */
|
||||
volatile uint8_t reserved1[7];
|
||||
/* 0x10: Host Interface PM Channel 2 Status */
|
||||
volatile uint8_t PM2STS;
|
||||
/* 0x11: Host Interface PM Channel 2 Data Out Port */
|
||||
volatile uint8_t PM2DO;
|
||||
/* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */
|
||||
volatile uint8_t PM2DOSCI;
|
||||
/* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */
|
||||
volatile uint8_t PM2DOSMI;
|
||||
/* 0x14: Host Interface PM Channel 2 Data In Port */
|
||||
volatile uint8_t PM2DI;
|
||||
/* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */
|
||||
volatile uint8_t PM2DISCI;
|
||||
/* 0x16: Host Interface PM Channel 2 Control */
|
||||
volatile uint8_t PM2CTL;
|
||||
/* 0x17: Host Interface PM Channel 2 Interrupt Control */
|
||||
volatile uint8_t PM2IC;
|
||||
/* 0x18: Host Interface PM Channel 2 Interrupt Enable */
|
||||
volatile uint8_t PM2IE;
|
||||
/* 0x19: Mailbox Control */
|
||||
volatile uint8_t MBXCTRL;
|
||||
/* 0x1a-0x1f: Reserved2 */
|
||||
volatile uint8_t reserved2[6];
|
||||
/* 0x20-0xff: Reserved3 */
|
||||
volatile uint8_t reserved3[0xe0];
|
||||
};
|
||||
|
||||
/* Input Buffer Full Interrupt Enable */
|
||||
#define PMC_PM1CTL_IBFIE BIT(0)
|
||||
/* Output Buffer Full */
|
||||
#define PMC_PM1STS_OBF BIT(0)
|
||||
/* Input Buffer Full */
|
||||
#define PMC_PM1STS_IBF BIT(1)
|
||||
/* General Purpose Flag */
|
||||
#define PMC_PM1STS_GPF BIT(2)
|
||||
/* A2 Address (A2) */
|
||||
#define PMC_PM1STS_A2_ADDR BIT(3)
|
||||
|
||||
/* PMC2 Input Buffer Full Interrupt Enable */
|
||||
#define PMC_PM2CTL_IBFIE BIT(0)
|
||||
/* General Purpose Flag */
|
||||
#define PMC_PM2STS_GPF BIT(2)
|
||||
|
||||
/*
|
||||
* Dedicated Interrupt
|
||||
* 0b:
|
||||
* INT3: PMC Output Buffer Empty Int
|
||||
* INT25: PMC Input Buffer Full Int
|
||||
* 1b:
|
||||
* INT3: PMC1 Output Buffer Empty Int
|
||||
* INT25: PMC1 Input Buffer Full Int
|
||||
* INT26: PMC2 Output Buffer Empty Int
|
||||
* INT27: PMC2 Input Buffer Full Int
|
||||
*/
|
||||
#define PMC_MBXCTRL_DINT BIT(5)
|
||||
|
||||
/*
|
||||
* eSPI slave registers
|
||||
*/
|
||||
struct espi_slave_regs {
|
||||
/* 0x00-0x03: Reserved1 */
|
||||
volatile uint8_t reserved1[4];
|
||||
|
||||
/* 0x04: General Capabilities and Configuration 0 */
|
||||
volatile uint8_t GCAPCFG0;
|
||||
/* 0x05: General Capabilities and Configuration 1 */
|
||||
volatile uint8_t GCAPCFG1;
|
||||
/* 0x06: General Capabilities and Configuration 2 */
|
||||
volatile uint8_t GCAPCFG2;
|
||||
/* 0x07: General Capabilities and Configuration 3 */
|
||||
volatile uint8_t GCAPCFG3;
|
||||
|
||||
/* Channel 0 (Peripheral Channel) Capabilities and Configurations */
|
||||
/* 0x08: Channel 0 Capabilities and Configuration 0 */
|
||||
volatile uint8_t CH_PC_CAPCFG0;
|
||||
/* 0x09: Channel 0 Capabilities and Configuration 1 */
|
||||
volatile uint8_t CH_PC_CAPCFG1;
|
||||
/* 0x0A: Channel 0 Capabilities and Configuration 2 */
|
||||
volatile uint8_t CH_PC_CAPCFG2;
|
||||
/* 0x0B: Channel 0 Capabilities and Configuration 3 */
|
||||
volatile uint8_t CH_PC_CAPCFG3;
|
||||
|
||||
/* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */
|
||||
/* 0x0C: Channel 1 Capabilities and Configuration 0 */
|
||||
volatile uint8_t CH_VW_CAPCFG0;
|
||||
/* 0x0D: Channel 1 Capabilities and Configuration 1 */
|
||||
volatile uint8_t CH_VW_CAPCFG1;
|
||||
/* 0x0E: Channel 1 Capabilities and Configuration 2 */
|
||||
volatile uint8_t CH_VW_CAPCFG2;
|
||||
/* 0x0F: Channel 1 Capabilities and Configuration 3 */
|
||||
volatile uint8_t CH_VW_CAPCFG3;
|
||||
|
||||
/* Channel 2 (OOB Message Channel) Capabilities and Configurations */
|
||||
/* 0x10: Channel 2 Capabilities and Configuration 0 */
|
||||
volatile uint8_t CH_OOB_CAPCFG0;
|
||||
/* 0x11: Channel 2 Capabilities and Configuration 1 */
|
||||
volatile uint8_t CH_OOB_CAPCFG1;
|
||||
/* 0x12: Channel 2 Capabilities and Configuration 2 */
|
||||
volatile uint8_t CH_OOB_CAPCFG2;
|
||||
/* 0x13: Channel 2 Capabilities and Configuration 3 */
|
||||
volatile uint8_t CH_OOB_CAPCFG3;
|
||||
|
||||
/* Channel 3 (Flash Access Channel) Capabilities and Configurations */
|
||||
/* 0x14: Channel 3 Capabilities and Configuration 0 */
|
||||
volatile uint8_t CH_FLASH_CAPCFG0;
|
||||
/* 0x15: Channel 3 Capabilities and Configuration 1 */
|
||||
volatile uint8_t CH_FLASH_CAPCFG1;
|
||||
/* 0x16: Channel 3 Capabilities and Configuration 2 */
|
||||
volatile uint8_t CH_FLASH_CAPCFG2;
|
||||
/* 0x17: Channel 3 Capabilities and Configuration 3 */
|
||||
volatile uint8_t CH_FLASH_CAPCFG3;
|
||||
/* Channel 3 Capabilities and Configurations 2 */
|
||||
/* 0x18: Channel 3 Capabilities and Configuration 2-0 */
|
||||
volatile uint8_t CH_FLASH_CAPCFG2_0;
|
||||
/* 0x19: Channel 3 Capabilities and Configuration 2-1 */
|
||||
volatile uint8_t CH_FLASH_CAPCFG2_1;
|
||||
/* 0x1A: Channel 3 Capabilities and Configuration 2-2 */
|
||||
volatile uint8_t CH_FLASH_CAPCFG2_2;
|
||||
/* 0x1B: Channel 3 Capabilities and Configuration 2-3 */
|
||||
volatile uint8_t CH_FLASH_CAPCFG2_3;
|
||||
|
||||
/* 0x1c-0x1f: Reserved2 */
|
||||
volatile uint8_t reserved2[4];
|
||||
/* 0x20-0x8f: Reserved3 */
|
||||
volatile uint8_t reserved3[0x70];
|
||||
|
||||
/* 0x90: eSPI PC Control 0 */
|
||||
volatile uint8_t ESPCTRL0;
|
||||
/* 0x91: eSPI PC Control 1 */
|
||||
volatile uint8_t ESPCTRL1;
|
||||
/* 0x92: eSPI PC Control 2 */
|
||||
volatile uint8_t ESPCTRL2;
|
||||
/* 0x93: eSPI PC Control 3 */
|
||||
volatile uint8_t ESPCTRL3;
|
||||
/* 0x94: eSPI PC Control 4 */
|
||||
volatile uint8_t ESPCTRL4;
|
||||
/* 0x95: eSPI PC Control 5 */
|
||||
volatile uint8_t ESPCTRL5;
|
||||
/* 0x96: eSPI PC Control 6 */
|
||||
volatile uint8_t ESPCTRL6;
|
||||
/* 0x97: eSPI PC Control 7 */
|
||||
volatile uint8_t ESPCTRL7;
|
||||
/* 0x98-0x9f: Reserved4 */
|
||||
volatile uint8_t reserved4[8];
|
||||
|
||||
/* 0xa0: eSPI General Control 0 */
|
||||
volatile uint8_t ESGCTRL0;
|
||||
/* 0xa1: eSPI General Control 1 */
|
||||
volatile uint8_t ESGCTRL1;
|
||||
/* 0xa2: eSPI General Control 2 */
|
||||
volatile uint8_t ESGCTRL2;
|
||||
/* 0xa3: eSPI General Control 3 */
|
||||
volatile uint8_t ESGCTRL3;
|
||||
/* 0xa4-0xaf: Reserved5 */
|
||||
volatile uint8_t reserved5[12];
|
||||
|
||||
/* 0xb0: eSPI Upstream Control 0 */
|
||||
volatile uint8_t ESUCTRL0;
|
||||
/* 0xb1: eSPI Upstream Control 1 */
|
||||
volatile uint8_t ESUCTRL1;
|
||||
/* 0xb2: eSPI Upstream Control 2 */
|
||||
volatile uint8_t ESUCTRL2;
|
||||
/* 0xb3: eSPI Upstream Control 3 */
|
||||
volatile uint8_t ESUCTRL3;
|
||||
/* 0xb4-0xb5: Reserved6 */
|
||||
volatile uint8_t reserved6[2];
|
||||
/* 0xb6: eSPI Upstream Control 6 */
|
||||
volatile uint8_t ESUCTRL6;
|
||||
/* 0xb7: eSPI Upstream Control 7 */
|
||||
volatile uint8_t ESUCTRL7;
|
||||
/* 0xb8: eSPI Upstream Control 8 */
|
||||
volatile uint8_t ESUCTRL8;
|
||||
/* 0xb9-0xbf: Reserved7 */
|
||||
volatile uint8_t reserved7[7];
|
||||
|
||||
/* 0xc0: eSPI OOB Control 0 */
|
||||
volatile uint8_t ESOCTRL0;
|
||||
/* 0xc1: eSPI OOB Control 1 */
|
||||
volatile uint8_t ESOCTRL1;
|
||||
/* 0xc2-0xc3: Reserved8 */
|
||||
volatile uint8_t reserved8[2];
|
||||
/* 0xc4: eSPI OOB Control 4 */
|
||||
volatile uint8_t ESOCTRL4;
|
||||
/* 0xc5-0xcf: Reserved9 */
|
||||
volatile uint8_t reserved9[11];
|
||||
|
||||
/* 0xd0: eSPI SAFS Control 0 */
|
||||
volatile uint8_t ESPISAFSC0;
|
||||
/* 0xd1: eSPI SAFS Control 1 */
|
||||
volatile uint8_t ESPISAFSC1;
|
||||
/* 0xd2: eSPI SAFS Control 2 */
|
||||
volatile uint8_t ESPISAFSC2;
|
||||
/* 0xd3: eSPI SAFS Control 3 */
|
||||
volatile uint8_t ESPISAFSC3;
|
||||
/* 0xd4: eSPI SAFS Control 4 */
|
||||
volatile uint8_t ESPISAFSC4;
|
||||
/* 0xd5: eSPI SAFS Control 5 */
|
||||
volatile uint8_t ESPISAFSC5;
|
||||
/* 0xd6: eSPI SAFS Control 6 */
|
||||
volatile uint8_t ESPISAFSC6;
|
||||
/* 0xd7: eSPI SAFS Control 7 */
|
||||
volatile uint8_t ESPISAFSC7;
|
||||
};
|
||||
|
||||
/*
|
||||
* eSPI VW registers
|
||||
*/
|
||||
struct espi_vw_regs {
|
||||
/* 0x00-0x7f: VW index */
|
||||
volatile uint8_t VW_INDEX[0x80];
|
||||
/* 0x80-0x8f: Reserved1 */
|
||||
volatile uint8_t reserved1[0x10];
|
||||
/* 0x90: VW Contrl 0 */
|
||||
volatile uint8_t VWCTRL0;
|
||||
/* 0x91: VW Contrl 1 */
|
||||
volatile uint8_t VWCTRL1;
|
||||
/* 0x92: VW Contrl 2 */
|
||||
volatile uint8_t VWCTRL2;
|
||||
/* 0x93: VW Contrl 3 */
|
||||
volatile uint8_t VWCTRL3;
|
||||
/* 0x94: Reserved2 */
|
||||
volatile uint8_t reserved2;
|
||||
/* 0x95: VW Contrl 5 */
|
||||
volatile uint8_t VWCTRL5;
|
||||
/* 0x96: VW Contrl 6 */
|
||||
volatile uint8_t VWCTRL6;
|
||||
/* 0x97: VW Contrl 7 */
|
||||
volatile uint8_t VWCTRL7;
|
||||
/* 0x98-0x99: Reserved3 */
|
||||
volatile uint8_t reserved3[2];
|
||||
};
|
||||
|
||||
#define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80
|
||||
/*
|
||||
* eSPI Queue 0 registers
|
||||
*/
|
||||
struct espi_queue0_regs {
|
||||
/* 0x00-0x3f: PUT_PC Data Byte 0-63 */
|
||||
volatile uint8_t PUT_PC_DATA[0x40];
|
||||
/* 0x40-0x7f: Reserved1 */
|
||||
volatile uint8_t reserved1[0x40];
|
||||
/* 0x80-0xcf: PUT_OOB Data Byte 0-79 */
|
||||
volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
|
||||
};
|
||||
|
||||
/*
|
||||
* eSPI Queue 1 registers
|
||||
*/
|
||||
struct espi_queue1_regs {
|
||||
/* 0x00-0x4f: Upstream Data Byte 0-79 */
|
||||
volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
|
||||
/* 0x50-0x7f: Reserved1 */
|
||||
volatile uint8_t reserved1[0x30];
|
||||
/* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */
|
||||
volatile uint8_t PUT_FLASH_NP_DATA[0x40];
|
||||
};
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
/**
|
||||
*
|
||||
* (3Axxh) SPI Slave Controller (SPISC) registers
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue