Add the #include <snippets-sections.ld> directive
to include a linker file automatically.
This file defines additional linker sections that
are dynamically added during the build process.
It is placed at the very end of the SECTIONS block,
ensuring that any sections it defines appear after
all standard sections.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Use CONFIG_STM32_FLASH_PREFETCH config option to enable flash prefetch
in C0/F0/F1/F2/F3/F4/F7/G4/L0/L1/L4/U0/U3/WB/WBA/WBL for consistency
with other SoCs that use this configuration switch, default enabled
at SoC default config level.
Add SoC hidden config option HAS_STM32_FLASH_PREFETCH enabled for
SoCs that support the feature. STM32_FLASH_PREFETCH is default
enabled for all SoC that have HAS_STM32_FLASH_PREFETCH unless target
specific constraints (as for G0Bx/G0Cx SoCs).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
An uninitialized variable was returned on success which could led by
init_nrfs.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The default log process thread stack size needs to be increased to
account for the recursion into resuming power domains, which
may happen within char_out for some backends like uart.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
siwx91x require a specific API to communicate with the bootloader in order
to achieve firmware upgrade. This commit introduces the configuration
symbol to import the helper library.
[Jérôme: split commits, reword the commit log]
Co-authored-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Rahul Gurram <rahul.gurram@silabs.com>
Add an early init hook to check the boot mode and reset into the RP2 USB
bootloader if requested. Includes a snippet to use with any RP2040/RP2350
board to enable the necessary DTS/Kconfig to use the functionality, and
easy DTS includes for boards to use explicitly.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Default disable flash prefetch on G0Bx/G0C1 to prevent issues
described by errata ES0548 2.2.10. Project can still enable
the config if applicable.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This commit adds support using pm_s2ram for 54H when the
MPU is disabled. This is the case for the out of tree
sample `sdk-nrf/samples/nrf54h/empty_app_core`.
Without this commit the linker will fail to link
`z_arm_mpu_init` and `z_arm_configure_static_mpu_regions`.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
This commit adds cache handling for Hifi4 core on RT700.
Enable CACHE_MANAGEMENT and HAS_DCACHE.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Add cpuclk driver for mt8188 platform. Note that the cpuclk driver is
not yet ported, it works only with mt8188.
Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
On MT8188 platform timer interrupts must also be enabled/disabled in
MTK_ADSP_IRQ_EN register in addition to xtensa_irq_enable(),
xtensa_irq_disable()
Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
Add 'ax' flags for .sof_entry ELF section so it merges properly with
.z_xtensa_vectors ELF section
Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
Boot ROM will by default set on/off delays to 0ms before jumping to
firmware. This patch adds an option to to configure the on/off delays to
non-zero values. A flash power cycle guarantees to put the external
flash into a known state before executing code from it. This is required
if using 4-byte address mode in the external flash, as the boot ROM will
always use 3-byte address mode when reading from external flash, causing
a potential deadlock situation requiring a power-cycle (known errata).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
1. the three boards share the same board schematic
- frdm_mcxa266, frdm_mcxa346, frdm_mcxa366
2. board dts,kconfig and cmake file could share
3. add MCXA366 soc and frdm_mcxa366 board
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Add initial power management support for i.MX943 M-core (M33/M7)
This lays the foundation for multi-core PM handling on i.MX943
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Improve how segment information looks like for MCUboot and SimpleBoot.
* silently igonore padding segments (if VMA is 0x0)
* do not duplicate mapped segments lines (IROM and DROM)
* fix IROM segments taht was incorrectly labeled as IRAM
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This reworks the Intel audio DSP host IPC driver as a backend of
the IPC service. This is the first step to rework IPC in SOF
(Sound Open Firmware) into using a more generic IPC API instead
of a SoC specific one.
For now, it keeps the old interface to maintain usability
as it is going to be a multiple process to rework IPC
over there.
Also, the structure of the new IPC backend resembles
the SoC specific driver to make it easier to compare
between them at this first iteration. Future optimizations
will probably be needed once we start modifying the SOF
side to utilize the IPC interface.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoC specific IPC driver is for host IPC, and not IDC (which
is between CPUs). So there is no need to use the IDC devicetree
binding to enable the kconfig.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add micro heap implementation which is using one or more 32 bit masks
to allocate quickly blocks. It is significantly better than using
sys_heap. Difference is especially big on RAM3 heap because heap
control data is in RAM3 space so operations there were extremely
slowly (15 us to allocate a buffer).
Simplified implementation of the heap requires DMM API change as
release functions need to know the length of the allocated buffer as
simple heap requires that (buffer address is enough for the standard
heap).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Default memcpy used in zephyr is not optimized and performs simple
byte by byte copying. Using double word or word access can significantly
reduce copying time especially for RAM3 (slow peripheral RAM).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The RP2350 SoC series contain two Hazard3 cores, which use the RISC-V
instruction set. Define a new CPU cluster (`hazard3`), which is intended
to be used with the two Hazard3 cores 'plugged in' to the two 'sockets'
in the RP2350 series SoCs.
Update the linker script to support linking against the correct
(ISA-specific) linker script, and to generate a correct IMAGE_DEF for
the target ISA.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
The RP2350 uses the Xh3irq interrupt controller, which supports nested
and prioritised interrupts. This adds initial support, configuring the
controller in 'direct' (non-vectored) mode.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Before re-entering Power Mode 3, we should disable the GET
sensor and reinitialize the power rails.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add the mapping for the GRTC_CLKOUT_FAST pinctrl mapping to the
periphconf generation. This allows clocking out the 16MHz clock with a
user selectable divider.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
- add NXP_BOARD_SPECIFIC_MPU_SETTINGS kconfig to provide a switch
for developer if they want to use private mpu settings
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==1 | NXP default setting
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==0 | User specific
- Use DT function to get memory base address and region size for cm7
- CM33 use dts to set mpu settings
- Add REGION_CUSTOMED_MEMORY_SIZE macro provide a common mapping ways
to map actual memory_size_kb to "region_size"
- The settings of the unified memory on cm33/cm7 cores:
ocram1/flexspi2 -> REGION_RAM_NOCACHE_ATTR
ocram2/dtcm -> REGION_RAM_NOCACHE_ATTR
flexspi/itcm -> REGION_FLASH_ATTR
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This commit adds multicore support to copy CM33 CPU1 image
from flash to RAM where it will boot from.
Also added NXP_IMXRT_BOOT_HEADER=y for CPU0 so it can be booted
from FlexSPI Flash.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Sets the default of this Kconfig for the SoC itself as a default,
rather than each board setting it, which minimises the change
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
