Add Kconfig and SoC initialization changes needed for future
MCXW70 TF-M non-secure support.
Secure-only RAM and platform initialization are excluded from
the non-secure startup path, with TF-M responsible for secure
platform setup.
Signed-off-by: Waqar Tahir <waqar.tahir@nxp.com>
Add a dwc_mac platform glue driver for the Synopsys DesignWare MAC
integrated in the Infineon XMC4XXX SoC family. The driver applies
pinctrl, configures the port control, connects the interrupt and
provides a small clock-control shim reporting the Ethernet and PTP
clock frequencies from the SCU.
The new ETH_XMC_DWC_ETHER_1000 symbol depends on !ETH_XMC4XXX, so the
generic dwc_mac driver can be used as an alternative to the XMC4XXX
Ethernet driver.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
CMC System Reset Status (SRS) register and its WAKEUP flag,
set when the reset was caused by a wakeup from Deep Power Down.
Deep Power Down is how PM_STATE_SUSPEND_TO_RAM and poweroff are
entered, and it is the only low-power state that wakes through
the reset routine. The transparent S2RAM resume keeps its marker
and CPU context in this same first 8 KiB of SRAM, so on a wakeup
reset the block already holds valid, ECC-checked data and must be
left intact for arch_pm_s2ram_resume(). It is only cleared to
initialize ECC check bits on a cold boot.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Commands are passed to the network coprocessor through
sli_wifi_send_command(), and its callers build the request structure on
the stack of the calling thread: 1408 bytes for a common flash write or
erase (sli_si91x_request_ta2m4_t), 1028 bytes for a firmware upgrade
chunk (sli_si91x_req_fwup_t). Both memset the full structure, so the
erase path pays for it even though it carries no data.
Measured on siwx917_rb4338a with CONFIG_INIT_STACKS=y, with an empty
settings partition so that the identity has to be written, every thread
that reaches the flash API needs far more stack than its default:
main 2692 used, 2048 default settings_load() from main()
shell_uart 2716 used, 2048 default settings_load() from the shell
sysworkq 2656 used, 2048 default
BT RX WQ 2568 used, 1200 default bt_settings_store_id()
CONFIG_ARM_MPU cannot be enabled on this SoC, so CONFIG_HW_STACK_PROTECTION
is unavailable and the overflow is silent: it corrupts the stack of
whichever thread the linker placed below, and that thread later dies with
wild control flow. The usual symptom is a USAGE FAULT in an unrelated
thread shortly after bt_enable() on a device whose settings partition is
empty.
Raise the defaults for the affected threads to 4096. The condition is
SILABS_SIWX91X_NWP rather than the flash driver alone, because the
firmware upgrade path has the same requirement and is reachable without
the flash driver. MAIN_STACK_SIZE folds into the existing WiseConnect
default rather than getting an entry of its own, because the first
matching configdefault wins and that one comes first.
With CONFIG_STACK_SENTINEL=y the pre-change tree reports "Stack overflow"
naming shell_uart for tests/bluetooth/shell and main for
samples/bluetooth/peripheral; afterwards the sentinel stays quiet and no
stack exceeds its size.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The CH32V series has between 16 KiB and 480 KiB of in-place
programmable program flash. Add a driver that implements the Zephyr
flash API, the appropriate Devicetree nodes, and overlays for the
`flash_shell` sample.
For the sample, trim back the default settings to fit within the ~64
KiB of flash and 8 to 20 K of RAM and add test partitions.
Use Devicetree to define the erase value. For the 003 and 006, this is
the common 0xFF but for the 20x/30x this is 0xE339. The flash API
works correctly on the 20x/30x but systems that require the erase
value to be a single byte, or assume that it is 0xFF, will not. This
can be addressed in future PRs.
Tested on the ch32v00x_core and bluepillplus_ch32v203 board by loading
the sample and running `flash test ...`. The
tests/drivers/flash/common test passes on the bluepillplus except for
the erase test which fails due to the ch32v203's half word erase
pattern.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Use the devicetree enum helper when checking whether external GPIO
antenna selection requires a pinctrl state.
The previous numeric comparison checked the internal enum value and
could emit the external GPIO warning for the wrong configuration.
Verified by building the SiWx917 Wi-Fi shell configuration.
Assisted-by: GitHub Copilot:gpt-5.6-sol
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add a dedicated SiWG917Y111MGABA SoC variant for modules using the
SiWG917M111MGTBA die.
Enable the module's external 32.768 kHz oscillator path, ACX behavior,
and external PSRAM LDO configuration. These settings are required for
the NWP to reach card-ready state and initialize Wi-Fi and Bluetooth.
Verified with hello_world, Wi-Fi scanning, Bluetooth advertising,
PSRAM access, counter alarms, and watchdog resets on BRD2708A.
Assisted-by: GitHub Copilot:gpt-5.6-sol
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Move the stm32n6 specific axisram driver out of the drivers/misc
folder since soc specific drivers should be located into the
related soc folder instead of misc.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
1. compare with SYS_INIT, platform hook is a more recommended way,
refer to:https://github.com/zephyrproject-rtos/zephyr/issues/75907
2. release second core should be executed after board_early_init_hook()
to ensure the clock tree and VDD_CORE are configured, and also after
POST_KERNEL to ensure the mailbox is initialized.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add support for using uart tx pin as a software strapping pin to force
the SoC into an infinite loop.
Tested by:
dut-control cold_reset:on
dut-control ccd_ec_boot_mode_uut:on
dut-control cold_reset:off
dut-control ccd_ec_boot_mode_uut:off
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Remove BOARD_ENABLE_CPUNET, a deprecated pass-through alias whose only
action was to select SOC_NRF53_CPUNET_ENABLE. It was marked deprecated
well before Zephyr 4.2 and has no in-tree users; all in-tree consumers
already use SOC_NRF53_CPUNET_ENABLE directly.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
Remove SOC_DCDC_NRF52X, SOC_DCDC_NRF52X_HV, SOC_DCDC_NRF53X_APP,
SOC_DCDC_NRF53X_NET and SOC_DCDC_NRF53X_HV, deprecated in Zephyr 4.0 in
favour of configuring the internal regulators through devicetree
(regulator-initial-mode on reg1/vregmain/vregradio, status = "okay" on
reg0/vregh).
All five were hidden options that nothing in-tree selected, and every
consumer already had the equivalent devicetree condition next to the
Kconfig one, so in-tree builds are unaffected. Devicetree is now the
single source of truth: the anomaly 160 workaround is still enabled by
the existing DT-driven defaults of SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED,
and the nRF5340 anomaly 166 branch is no longer skipped by a Kconfig
option that disagreed with a vregmain configured in LDO mode.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
Remove the hidden Kconfig option GPIO_AS_PINRESET, deprecated in Zephyr
3.5 in favour of the "gpio-as-nreset" property on the UICR devicetree
node. Nothing in-tree selected it, and the MDK glue in mdk_config.h has
derived NRF_CONFIG_GPIO_AS_PINRESET purely from the devicetree property
since then; only the stale comment naming the Kconfig symbol is updated.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
Two-line copyright notices were wrapped in the SPDX "<text>...</text>"
construct, which is only valid in an SPDX document, not a file header.
The REUSE tool then folds the literal "<text>" into the holder name
and drops the second line from the SBOM.
Remove the markers and tag the continuation line. Holder, year and
e-mail are left unchanged; only the syntax is fixed.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Fix CONFIG_RENESAS_RA_BATTERY_BACKUP_MANUAL_CONFIGURE default value.
Since manual-configure DT property is of boolean type, use of
dt_compat_any_has_prop(..., manual-configure) always returns true.
Set function argument value to True to get the expected behavior.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
cy_device.c / cy_gpio.c are relocated into ITCM (.cy_itcm, see
itcm_mem.ld). With -funwind-tables enabled (CONFIG_ARCH_STACKWALK) the
compiler also emits .ARM.exidx.cy_itcm / .ARM.extab.cy_itcm entries for
that code. Those entries are gathered into the main exidx table in
ROMABLE_REGION, from where the R_ARM_PREL31 relocation back to the ITCM
code cannot be encoded, so the link fails with 'relocation truncated to
fit: R_ARM_PREL31 against .cy_itcm'. The Cortex-M stack unwinder does not
consume these tables, so discard the ITCM-relocated ones.
Assisted-by: AI (GitHub Copilot)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
CONFIG_ARCH_STACKWALK adds -funwind-tables
(arch/arm/core/CMakeLists.txt), so C code emits .ARM.extab
exception-unwinding sections. The generic Cortex-M linker script already
guards the .ARM.extab output section with CONFIG_CPP || CONFIG_RUST ||
CONFIG_ARCH_STACKWALK, but the Infineon cat1b (cyw20829) and edge (pse84)
SOC linker scripts, which override it, were missing the ARCH_STACKWALK
case. As a result .ARM.extab became an orphan section and the link failed
when orphan-section handling is strict (e.g. the perf sample, which
selects ARCH_STACKWALK via the new Arm Cortex-M backend). Sync the guard
with the generic script.
Assisted-by: AI (GitHub Copilot)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
On Microchip SAM0/SAMx54 family SoCs, the MCAN peripheral uses a 16-bit
Message RAM Base Address (MRBA) register relative to 0x20000000.
If MRAM buffers are placed above 0x20010000, the address truncates
and DMA operations access invalid memory locations.
This change introduces a dedicated .mram_noinit section via
zephyr_linker_sources_ifdef in SAM0 common CMake scripts to guarantee
that MRAM buffers are allocated at the start of RAM, staying strictly
within the 64 KB offset limit.
Signed-off-by: Xavier Douville <github@douville.org>
Use DT_PARTITION_ADDR() to obtain flash partition addresses rather than
assuming a fixed layout where the storage partition follows the code
partition.
This makes MPU configuration a bit more robust against partition layout
changes.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Configure the storage flash region with read-only or read-write access
permissions based on the MPU_ALLOW_FLASH_WRITE setting.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Two things kept this SoC on the legacy IRQ-unlocked path. pm_state_set()
cleared BASEPRI and masked with PRIMASK by hand, and
pm_state_exit_post_ops() called gpio_mcux_lpc_trigger_cb() directly
after a standby pin wake. The second one is not a mechanical fix: that
call dispatches user callbacks synchronously, before the PM exit
notifier, sys_clock_idle_exit(), and the CPU PM state teardown have run.
Wrap the raw WFI and every returning POWER_EnterPowerMode() call with
arch_pm_state_set_prepare() and arch_pm_state_set_finish(), and coalesce
the wake pin mask into an atomic before handing it to a static system
workqueue item, so the user callback runs after PM resume completes
rather than from inside the post-op. The handler exchanges the pins out
of the atomic, which preserves exactly-once delivery even if another
wake lands while the work is still pending.
The workqueue path needs multithreading, so keep
PM_STATE_SET_IRQ_UNLOCKED and the previous synchronous dispatch under
"if !MULTITHREADING" rather than forcing multithreading on. A
single-threaded build therefore keeps its old behavior and still links.
Validated on rd_rw612_bga with tests/subsys/pm/power_mgmt_soc: 3 of 3
cases pass, entering both light and deep sleep with timer wake. Also
build-checked with CONFIG_MULTITHREADING=n.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
These hooks are the i.MX95 M7 pattern, including the same hand-written
PRIMASK workaround in pm_state_set() and the PRIMASK clear in
pm_state_exit_post_ops(), so apply the same migration: one
enter_low_power() helper wrapping the WFI with
arch_pm_state_set_prepare() and arch_pm_state_set_finish(), SCMI
wake-mask and CPU RUN restoration left under the PM core lock, and
PM_STATE_SET_IRQ_UNLOCKED removed.
Add imx952_evk/mimx9529/m7 to the power_mgmt_soc platform list.
Validated on imx952_evk/mimx9529/m7: builds with the IRQ-locked
default. Hardware validation of the SCMI wake mask and CPU mode
transitions is still outstanding.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
pm_state_set() masked with PRIMASK and cleared BASEPRI by hand, with a
comment explaining that BASEPRI masking prevents the core from waking
out of WFI. pm_state_exit_post_ops() then cleared PRIMASK after
restoring the SCMI CPU RUN mode, which required the
PM_STATE_SET_IRQ_UNLOCKED opt-out.
Factor the three SCMI sleep modes onto one enter_low_power() helper that
sets the sleep mode and then wraps the WFI with
arch_pm_state_set_prepare() and arch_pm_state_set_finish(). The SCMI
wake-mask setup and the CPU RUN restoration stay where they were, now
running entirely under the PM core lock, and the opt-out is removed.
Validated on imx95_evk/mimx9596/m7: builds with the IRQ-locked default.
Hardware validation of the SCMI wake mask and CPU mode transitions is
still outstanding.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The runtime-idle state reached low power through k_cpu_idle(), which
performs its own IRQ unlock inside the region the PM core keeps locked.
That is why SOC_LPC55S69_CPU0 selected PM_STATE_SET_IRQ_UNLOCKED.
Replace it with a raw WFI wrapped by arch_pm_state_set_prepare() and
arch_pm_state_set_finish(), and remove the opt-out. Only the CPU0
symbol is touched; the rest of the series is unaffected.
Add lpcxpresso55s69/lpc55s69/cpu0 to the power_mgmt_soc platform list.
The test references a cpu0 node label, which this board's devicetree
does not define, so add a board overlay supplying it the same way other
power management tests do.
Validated on lpcxpresso55s69/lpc55s69/cpu0 with
tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass with timer wake.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
system_enter_sleep() cleared BASEPRI and masked with PRIMASK around its
WFI, and pm_state_exit_post_ops() cleared PRIMASK before logging the
previous CM7 and CM4 GPC modes, so that reporting ran with interrupts
already unmasked.
Wrap the WFI with arch_pm_state_set_prepare() and
arch_pm_state_set_finish(), drop the post-op unmask so the GPC state
reporting stays under the PM core lock, and remove the
PM_STATE_SET_IRQ_UNLOCKED opt-out.
Add mimxrt1170_evk/mimxrt1176/cm7 to the power_mgmt_soc platform list so
the SoC has representative coverage.
Validated on mimxrt1170_evk rev B with tests/subsys/pm/power_mgmt_soc:
3 of 3 cases pass, entering both light and deep sleep with timer wake.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Same shape as the RT5xx CM33 hooks: pm_state_set() carried the FIXME
about BASEPRI masking wake IRQs and worked around it with a hand-written
PRIMASK sequence, pm_state_exit_post_ops() unmasked, and the SoC opted
out through PM_STATE_SET_IRQ_UNLOCKED.
Use arch_pm_state_set_prepare() and arch_pm_state_set_finish() around
POWER_EnterSleep() and POWER_EnterDeepSleep(), drop the post-op unmask,
and remove the opt-out. The HAL preserves PRIMASK across its internal
WFI and restores it after wake.
Add mimxrt685_evk/mimxrt685s/cm33 to the power_mgmt_soc platform list so
the SoC has representative coverage.
Validated on mimxrt685_evk/mimxrt685s/cm33 with
tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass, entering both light
and deep sleep with timer wake.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
pm_state_set() reached low power through k_cpu_idle(), which performs
its own IRQ unlock, and pm_state_exit_post_ops() finished with
irq_unlock(0). Nesting an unlock inside the region the PM core keeps
locked is what PM_STATE_SET_IRQ_UNLOCKED had to paper over.
Replace k_cpu_idle() with a raw WFI wrapped by
arch_pm_state_set_prepare() and arch_pm_state_set_finish(), drop the
post-op unlock, and remove the opt-out. The XIP path keeps its
__ramfunc wrapper so the flash prefetch drain and the WFI still execute
from RAM, with the helpers called from outside that body. Rename the
wrapper to wait_for_flash_prefetch_and_wfi() since it no longer calls
the kernel idle entry.
Validated on twr_ke18f with tests/subsys/pm/power_mgmt_soc: builds with
CONFIG_XIP=y and the RAM wrapper resident in .ramfunc.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
pm_state_set() cleared BASEPRI and masked with PRIMASK before calling
into the power library, and pm_state_exit_post_ops() cleared PRIMASK
again, which required the PM_STATE_SET_IRQ_UNLOCKED opt-out.
Wrap the sleep, deep-sleep, and power-down entries with
arch_pm_state_set_prepare() and arch_pm_state_set_finish() instead, drop
the post-op unmask, and remove the opt-out. All three HAL entry paths
preserve PRIMASK across their internal WFI and restore it after wake, so
wrapping the calls themselves is sufficient.
Validated on frdm_mcxw23 with tests/subsys/pm/power_mgmt_soc: 3 of 3
cases pass, entering both light and deep sleep with timer wake.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
pm_state_set() carried a FIXME explaining that the kernel masks with
BASEPRI, which blocks wake IRQs of non-zero priority, and worked around
it by setting PRIMASK and clearing BASEPRI by hand. Zephyr now provides
exactly that sequence as arch_pm_state_set_prepare() and
arch_pm_state_set_finish(), with the kernel retaining ownership of the
IRQ restore.
Use the architecture helpers around POWER_EnterSleep() and
POWER_EnterDeepSleep(), drop the __enable_irq() from
pm_state_exit_post_ops(), and remove the PM_STATE_SET_IRQ_UNLOCKED
opt-out. The HAL preserves PRIMASK across its internal WFI and restores
it after wake, so wrapping the power API call is sufficient.
Validated on mimxrt595_evk/mimxrt595s/cm33 with
tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass, entering both light
and deep sleep with timer wake.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Since commit 85a2085172 ("pm: make IRQ-locked state-set the default")
the PM core keeps IRQs masked across pm_state_set() and
pm_state_exit_post_ops(), and an implementation that unmasks from those
hooks has to opt out through PM_STATE_SET_IRQ_UNLOCKED.
This SoC opted out, and its ordering was the reason to care:
pm_state_exit_post_ops() called __enable_irq() as its very first
statement, before clearing the SPC power-domain low-power request flag.
A wake ISR could therefore observe that flag still set.
Wrap both CMC low-power entries with arch_pm_state_set_prepare() and
arch_pm_state_set_finish() instead of hand-rolling the PRIMASK/BASEPRI
sequence, drop the post-op unmask so the flag is cleared under the PM
core lock, and remove the opt-out from both SoC symbols. The CMC power
domain config is hoisted out of the switch case because two branches
now use it.
Add frdm_mcxw72 to the power_mgmt_soc platform list so the SoC has
representative coverage.
Validated on frdm_mcxw72 with tests/subsys/pm/power_mgmt_soc: 3 of 3
cases pass, entering both light and deep sleep with timer wake.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add a device-memory MPU region for every Clocking Wizard node in
the devicetree that is enabled (status = "okay"). This marks its
register address range as device memory, same as other peripherals,
so it's safe to access from user code.
Without this, the driver would rely on the generic DEVICE region
instead of a properly sized region for its own registers.
Signed-off-by: Beesam Sridhar Sagar <sagar.beesamsridhar@amd.com>
The lp core boots through lp rom before reaching the app entry,
and that delay lets the hp core start sending before the mailbox
interrupt is enabled. Boot straight into lp ram instead. Nothing
is lost, as the rom only sets up its uart and that is already
disabled here. esp32c5 and c6 have no lp rom and boot this way
already.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
An unflashed partition reads back as all ones, which was handed
to the loader as if it were a valid image. Check for it as the
esp32c5 and esp32c6 loaders already do.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The core cleared its sleep stall and reset enables after launch,
so it spun in its halt call instead of sleeping and the timer had
no sleeping core to restart. Keep them, matching esp32c5 and c6.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Changed the SOC_SERIES cmake varible to use
CONFIG_SOC_SERIES as SOC_* variables will be
deprecated.
Signed-off-by: Thamaraimanalan M <thamaraimanalan@linumiz.com>
Add DT helper file for PIC32CM SG/GC family devices to support
SoC-specific device tree definitions and utilities.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
The binary info header is injected into rom_start with sort key
'0x0binary_info_header', which sorts before '0x0vectors' (the ARM
vector table). This places the header at XIP_BASE + 0x100, right
where the RP2040 boot2 stage hardcodes VTOR. The vector table,
pushed to 0x10000200 by ALIGN(0x100) after the header's 24 bytes,
is never reached — the core loads the header marker as its stack
pointer and faults immediately.
Fix by using sort key '0x2binary_info_header' so the header emits
after the vector table snippets ('0x0vectors' / '0x1vectors'). The
vector table sits at 0x10000100 as boot2 expects, and the header
ends at ~offset 0xbc — within the 256-byte limit picotool scans.
Only affects RP2040 builds with CONFIG_RPI_PICO_BINARY_INFO=y.
Signed-off-by: Toon Stegen <toon@toostsolutions.be>
Replace direct NVIC_SetPendingIRQ()/NVIC_EnableIRQ() calls with
k_irq_set_pending() and k_irq_enable() to reduce the dependence on
cmsis_core.h.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Default I2C_DW_IC_CLK_FREQ_OPTIMIZATION for Alif Balletto and Ensemble.
The Alif I2C blocks are clocked from SYST_PCLK through the SoC clock
controller; enabling the driver's IC clock frequency optimization
allows correct timing register calculation on these platforms.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
Replace the NVIC_GetEnableIRQ()/NVIC_EnableIRQ()/NVIC_DisableIRQ()
calls in the vector-table takeover loop with irq_is_enabled()/
irq_enable()/irq_disable().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC_ClearPendingIRQ() calls with
k_irq_clear_pending().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable FlexComm2 as I2C and add the NXP MMA8652FC 3-axis accelerometer at
0x1d, which the fxos8700 driver detects by WHOAMI. The part has no
magnetometer, so the driver is defaulted to accelerometer-only mode.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Add the ESP32-C61 soc port: linker scripts, PMP regions, boot
path, hardware init and Kconfig, mostly mirroring the
single-core C5 behavior. The C61 is single-core RISC-V with a
CLIC interrupt controller and has no LP core.
The APM access-path filters are disabled during early hardware
init: they default to allowing only TEE-mode bus masters while
the application runs in REE mode, so radio and DMA bus accesses
would be silently dropped otherwise.
The bootloader loader segments and the MCUboot image metadata
follow the layout of the other espressif socs. The soc is
allowed to select external ram, while psram itself stays opt-in
through CONFIG_ESP_SPIRAM.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Invert the in-tree ethernet driver configuration logic.
The current logic is boards enabling `NET_L2_ETHERNET`, which then
unconditionally defaults `ETH_DRIVER` to enabled. This means that
`ETH_DRIVER` end up set for boards that use the L2 Ethernet layer but
don't have an ethernet device (see some WiFi drivers).
This commit:
* Removes the `default y if NET_L2_ETHERNET` from `ETH_DRIVER`
* Adds `default y if ETH_DRIVER` to `NET_L2_ETHERNET`
* Adds `imply ETH_DRIVER` to `NET_QEMU_ETHERNET`
* Updates in-tree ethernet boards to default `ETH_DRIVER` instead of
`NET_L2_ETHERNET`
The outcome of this PR is that Kconfig can now use `ETH_DRIVER` to
reasonably assume that an actual ethernet driver is enabled.
Conversion of in-tree boards/samples performed by GPT-5.5.
Assisted-by: GPT-5.5
Signed-off-by: Jordan Yates <jordan@embeint.com>
The previous commit means USE_SWITCH has a missing dependency
(USE_SWITCH_SUPPORTED) if TRUSTED_EXECUTION_NONSECURE holds.
Use the weaker `imply` instead of `select` for enabling USE_SWITCH
on corstone300/corstone320 to avoid a Kconfig warning from this
dependency.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
