Commit graph

5973 commits

Author SHA1 Message Date
Li Feng
132f0088ec ish build: add new manifest v1.1 support
ISH manifest v1.1 applies to ISH 5.8.

Signed-off-by: Li Feng <li1.feng@intel.com>
2025-04-28 08:35:53 +02:00
Titan Chen
31f5d2826d drivers: pwm: rts5912: port pwm driver on Zephyr
Add PWM driver support for Realtek RTS5912

Signed-off-by: Titan Chen <titan.chen@realtek.com>
2025-04-28 08:34:18 +02:00
1d7a095779 soc: wch: move from qingke-v2 to the more specific qingke-v2a
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.

Signed-off-by: Michael Hope <michaelh@juju.nz>
2025-04-26 10:55:45 +02:00
Jacob Wienecke
db63e563a9 drivers: memc: memc_nxp_flexram.h: Move to the public includes directory
Moved to: include/zephyr/drivers/misc/flexram/memc_nxp_flexram.h

This change makes it so that the .h file does not need to be pulled in
using the CMakeLists.txt file, and can be included like other public
includes.

Removes drivers/memc/memc_nxp_flexram.h

Add memc_nxp_flexram.h to include/zephyr/drivers/misc/flexram

Modify drivers/memc/memc_nxp_flexram.c to use the new include path.

Modifies the mimxrt1170 magic_addr sample to include the driver using
the new include path.

Modify the soc file: soc/nxp/imxrt/imxrt11xx/soc.c to use the new path.

Add relevant information to migration-guide-4.2.rst.

Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Co-authored-by: Declan Snyder <declan.snyder@nxp.com>
2025-04-26 10:55:09 +02:00
Michal Kozikowski
9a6f116a6a soc: nordic: nrf54h: Disable GPD for MCUBoot
Disable GPD for MCUBoot build, as it cannot be
reinitialized later in application (SDFW does not
support reinitialization).

Also, remove the GPD disabling from the mcumgr sample
for nRF54H20 iron board app - it was the reinitialization
that caused problems.

Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
2025-04-25 14:06:08 +02:00
Hieu Nguyen
f1b5511a23 drivers: pinctrl: Add initial support for RZ/A2M
Add pinctrl support for RZ/A2M

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
2025-04-25 14:05:01 +02:00
Hoang Nguyen
73a9d2615d soc: renesas: Add support for Renesas RZ/A2M
Add support for Renesas RZ/A2M

Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
2025-04-25 14:05:01 +02:00
Martin Hoff
eac798fc51 soc: adi: remove unused symbol sram_vector_table
The symbol SRAM_VECTOR_TABLE is not used in the adi/max32 soc. Removed
it in order to clean up the Kconfig file and avoid confusion with the
upcoming new definition of SRAM_VECTOR_TABLE symbol. (PR #87468)

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2025-04-25 11:05:17 +02:00
Henrik Lindblom
9de3d6bf64 soc: stm32: use cache peripheral driver
Use the Zephyr cache API in soc initialization code instead of calling the
HAL directly. The change does not modify the pre-existing cache settings,
just changes the path they are enabled.

Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
2025-04-25 11:04:37 +02:00
Ruibin Chang
eb99158a80 drivers/sensor/ite/tach/it51xxx: implement tachometer driver
Implement tachometer driver for ITE it51xxx series chip.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2025-04-24 11:56:44 +02:00
Titan Chen
e6bb7fc6cf soc : realtek: ec: rts5912: add support ULPM
Port rts5912 ULPM on Zephyr

Signed-off-by: Titan Chen <titan.chen@realtek.com>
2025-04-24 11:56:36 +02:00
Erwan Gouriou
b4c1dc63a8 soc: stm32h7r/s: smps is supported on all SoCs
Remove the sanity check between Cube HAL SMPS symbol and Kconfig SMPS
configuration.
SMPS is available on all STM32H7R/S SoC, so misalignment isn't possible.

Additionally, point to the hal commit which revert the fix which was done
on hal_stm32 to add this symbol.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2025-04-24 10:39:34 +02:00
Ricardo Rivera-Matos
2b553ba74f soc: stm32: Adds support for STM32F401XD variants
Introduces config file entries for STM32F401XD variants. The
STM32F401XD family is related to the STM32F401XE family but with a
reduced flash memory.

Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
2025-04-24 01:27:43 +02:00
Gerson Fernando Budke
6520633a90 drivers: pinctrl: bouffalolab: Add bflb pinctrl driver
Add Bouffalo Lab pinctrl driver.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2025-04-24 01:26:37 +02:00
Gerson Fernando Budke
3c45c8b5cf soc: riscv: bouffalolab: Add bl60x series cpu
Add initial version.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2025-04-24 01:26:37 +02:00
Hao Luo
eebd10de8a soc: ambiq: Add missing LOG_MODULE_REGISTER in soc
Need to register log module as we declare it in power.c

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-04-23 10:04:09 +02:00
Kate Wang
587042d0df soc: nxp: imxrt: imxrt7xx: update rt7xx soc files
Add functions to configure MIPI_DSI power and clock when
MIPI_DSI is enabled.

Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
2025-04-23 10:03:42 +02:00
Guillaume Gautier
9f02634d3f soc: st: stm32n6: configure regulator for best performance
Configure the main internal Regulator output voltage for best performance
on STM32N6.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-04-22 14:03:22 +02:00
Dylan Hsieh
f3bc550117 driver: adc: add adc driver for rts5912
Add adc driver for Realtek rts5912.

Signed-off-by: Dylan Hsieh <dylan.hsieh@realtek.com>
2025-04-22 14:02:37 +02:00
Titan Chen
2bca8d4e59 drivers: counter: rts5912: add support timer32 counter driver
Port rts5912 timer32 counter driver on Zephyr

Signed-off-by: Titan Chen <titan.chen@realtek.com>
2025-04-22 14:02:27 +02:00
Hao Luo
f28f4120ef drivers: pinctrl: Add sdif configs to ambiq pinctrl driver
Added sdio cd and wp pin configs to ambiq pinctrl driver

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-04-22 12:10:01 +02:00
Tom Hughes
7f0cd6692b soc: andestech: linker.ld: Handle symtab/strtab/shstrtab to fix warnings
lld will produce warnings for the symtab, strtab, and shstrtab sections
if --orphan-handling=warn is specified and there are no matching rules
in the linker script for these sections. Handle these sections when
building with lld to prevent the warnings.

This is exactly the same as commit
c420733c33, but for the AE350 linker
script.

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
2025-04-22 09:58:57 +02:00
Steven Chang
95edcf70fc driver: i2c: ene_kb1200 i2c slave address
Fix slave address,
Notify transfer completion via semaphore

Signed-off-by: Steven Chang <steven@ene.com.tw>
2025-04-22 09:58:32 +02:00
Kesavan Yogeswaran
2882dab78c soc: nxp: Fix boot header placement when using lld
As well described in a previous PR [1], the GNU ld and LLVM lld linkers
treat the location counter (`.`) differently. lld always inteprets the
location counter as an absolute address whereas ld interprets it as an
offset from the start of the current object.

The NXP boot header linker script files use `.` assignment to specify an
offset within the rom_start region (ld-style). This causes lld to error
out since it interprets this as the location counter moving backwards.

To fix this, re-use the idea from the previous PR [1]:
replace `. = FOO` with `. += FOO - (. - __rom_start_address)`

This sets the location counter in a way that works with both ld and lld.

[1] https://github.com/zephyrproject-rtos/zephyr/pull/58315

Signed-off-by: Kesavan Yogeswaran <hikes@google.com>
2025-04-21 22:03:38 +02:00
Qiang Zhao
893f2e0187 soc: nxp: imx95: fix systick issue for M7
The SLEEP_HOLD_EN is enabled by default, that will
gate systick, clear it to fix

Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
2025-04-21 22:03:27 +02:00
Qiang Zhao
c412ee4597 drivers: firmware: scmi: add cpu domain protocol
Added helpers for NXP SCMI cpu dmomain protocol.

Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
2025-04-21 22:03:27 +02:00
Hao Luo
c188125165 soc: arm: ambiq: apollo510: Add support for Apollo510 SoC
Add all required parts (new SoC family/series, device tree) for
the Ambiq Apollo510 SoC.

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-04-21 20:04:31 +02:00
Titan Chen
5179463750 drivers: timer : fix rtmr and slow timer.
RTMR use slow timer be the busy_wait timers,
only ARCH_HAS_CUSTOM_BUSY_WAIT if slow timer disabled.

Signed-off-by: Titan Chen <titan.chen@realtek.com>
2025-04-21 12:42:28 +02:00
Daniel Leung
d08981527d soc: intel_adsp/ace: use custom arch_spin_relax()
Intel Audio DSP ACE needs to use arch_spin_relax() to give
the bus more time to propagate the RCW transactions among
CPUs, and to avoid sending too many requests to the bus
after failing to lock spinlocks. However, the number of
NOPs results in a very big arch_spin_relax() that spans
multiple instruction cache lines, and requires evicting
them just for NOPs.  With 5 CPUs, it can span 6 cache
lines (if using nop.n instead of nop). That's a waste of
space and cache. So instead, we do a tight loop instead.
Since the SoC supports zero-overhead loops, this should
have minimal performance impact.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-21 07:45:23 +02:00
Daniel Leung
58b035b85f soc: intel_adsp/ace: linker: align cpuhold_* variables
For some weird unknown reasons, the simulator really do not
like the cpuhold_* variables to be tightly packed together.
This results in cpuhold_spawned not being updated, and we
will be stuck in the while loop for it to be set.
Workaround this by explicitly aligning these variables on
16 byte boundary. This seems to work for now.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-21 07:45:23 +02:00
Daniel Leung
e5685cab4a soc: intel_adsp/ace: link xtensa_swap_update_page_tables...
...earlier. Similar to xtensa_do_syscall, we want to group
some functions together.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-21 07:45:23 +02:00
Dylan Hsieh
c60d2c58f8 soc: realtek: rts5912 image tool add SHA2 tag
Let rts5912 image tool to add SHA2 tag at the tail end of image.

Signed-off-by: Dylan Hsieh <dylan.hsieh@realtek.com>
2025-04-21 07:45:14 +02:00
Ioannis Damigos
e41909a32c soc: da1469x: Drop CONFIG_SRAM_VECTOR_TABLE from default configuration
Drop CONFIG_SRAM_VECTOR_TABLE from default configuration.

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2025-04-19 11:48:24 +02:00
Michal Kozikowski
ea6e6c66a1 boards: nordic: nrf54h20dk iron board MCUBoot support
Provide proper adaptions as bootloader ROM offset, flash load
offset and dts definitions for the nRF54H20 iron board to make it
ready for the MCUBoot bootloader.

Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
2025-04-18 17:46:40 +02:00
Eric Ackermann
7ea1bb783f soc: cv32a6: Remove erroneous CPU_HAS_FPU configs
In the default configuration, cv32a6 does not have an FPU and does not
implement RISC-V's F and D extensions.
Hence, the FPU flags should not be added.
In the future, a second SoC for cv32a6 systems with FPU can be added.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
2025-04-18 17:46:30 +02:00
Eric Ackermann
51eaf02626 soc: cva6: Fix CONFIG_MAX_IRQ_PER_AGGREGATOR
The original commit uses the incorrect value 42 for
CONFIG_MAX_IRQ_PER_AGGREGATOR for the cva6 family of SoCs,
which is the total number of IRQs in the system.
This commit corrects this to 30, the number of IRQs for the PLIC.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
2025-04-18 17:46:30 +02:00
Eric Ackermann
6ba7691e96 soc: cva6: Implement missing cache management APIs
In hardware, cva6 currently only provides global disable/enable
functions for the Dcache and Icache. Disabling and re-enabling them also
has the effect of flushing and invalidating the cache.
Future cva6 SoCs will add support RISC-V's standardized cache management
operations.
This commit provides a default implementation for all methods currently
part of the cache API. These implementations can be overwritten at board
or SoC level, as they use weak linking.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
2025-04-18 17:46:30 +02:00
Jamie McCrae
b59d6d3c2d soc: nordic: Add missing flash runner config
Adds missing qualifiers for grouping flash runner configuration

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-04-18 10:41:08 +02:00
Tom Chang
eb5597e90a drivers: espi: npcx: ensure the host receives the value from eSPI VW
This commit adds an option to verify weather the host has read the value
after the wire 3-0 bits have been updated.

Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
2025-04-18 10:40:23 +02:00
Jérôme Pouiller
2bbafa7072 soc: silabs: siwx91x: Allow alternative memory partition
Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
  - 196kB
  - 256kB
  - 320kB

Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2025-04-17 17:23:32 +02:00
Jérôme Pouiller
164bbdf294 drivers: dma: siwx91x: Use DT to declare descriptors
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.

Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.

Then, with this new implementation, the memory mapping is easier to
understand for the reader.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2025-04-17 17:23:32 +02:00
Hao Luo
6f4b92d64d soc: ambiq: Optimize the inclusion relationship of header files
Optimized the inclusion relationship of header files

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-04-17 09:06:18 +02:00
Jun Lin
3f59fa36f1 soc: npcx: update the NUM_IRQS value for npcx4
The npcx4 SoC only uses 86 NVIC IRQ numbers.
This commit updates the number from 128 to 86 to reduce the memory
usage.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2025-04-17 09:06:07 +02:00
Daniel Leung
277fa9e8ac xtensa: userspace: swap page tables via assembly code
Since the necessary register values are now pre-computed and
stored in the memory domain struct, we can use them directly
in various assembly locations, thus replacing the function
call to xtensa_swap_update_page_tables().

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
a4367eb514 xtensa: remove CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP
Remove CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP as it is
remnant from early MMU enabling work which is not needed as
the page table code is different from early version where
the PTEVADDR would be the same for all memory domains.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
The Nguyen
949fc5b5f0 soc: renesas: add linker define for CMake Linker Generator on RA4E2
Initial support for CMake Linker Generator on Renesas RA4E2

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2025-04-17 00:57:08 +02:00
Julien Panis
23a296f26b soc: ti: cc23x0: Add helper macros for device tree
This patch adds an header file which contains helper macros.
These macros can be used to access some device tree properties.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
2025-04-17 00:55:56 +02:00
Arnaud Pouliquen
cea2487d3d soc: st: stm32mp13: add missing arm_mmu.h include
The samples/subsys/llext/shell_loader test fails when running as a
twister test on the stm32mp135f_dk/stm32mp135fxx platform, with the
following error:

soc/st/stm32/stm32mp13x/soc.c:46:36:
error: array type has incomplete element type 'struct arm_mmu_region'
   46 | static const struct arm_mmu_region mmu_regions[] = {

This commit adds the missing arm_mmu.h include to fix the build issue.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
2025-04-16 17:08:37 +02:00
Sai Santhosh Malae
ee55bdc3c2 drivers: timer: siwx91x: Remove sleeptimer as default soc timer
Remove sleeptimer as default soc timer and it should be only
used as soc timer if PM is enabled.

Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
2025-04-16 17:08:13 +02:00
Hao Luo
a499afde23 drivers: pinctrl: Update ambiq nce definitions in pinctrl
Updated nce definitions in pinctrl structure to be consistent
with ambiq HAL.

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-04-16 17:07:51 +02:00