The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Moved to: include/zephyr/drivers/misc/flexram/memc_nxp_flexram.h
This change makes it so that the .h file does not need to be pulled in
using the CMakeLists.txt file, and can be included like other public
includes.
Removes drivers/memc/memc_nxp_flexram.h
Add memc_nxp_flexram.h to include/zephyr/drivers/misc/flexram
Modify drivers/memc/memc_nxp_flexram.c to use the new include path.
Modifies the mimxrt1170 magic_addr sample to include the driver using
the new include path.
Modify the soc file: soc/nxp/imxrt/imxrt11xx/soc.c to use the new path.
Add relevant information to migration-guide-4.2.rst.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Co-authored-by: Declan Snyder <declan.snyder@nxp.com>
Disable GPD for MCUBoot build, as it cannot be
reinitialized later in application (SDFW does not
support reinitialization).
Also, remove the GPD disabling from the mcumgr sample
for nRF54H20 iron board app - it was the reinitialization
that caused problems.
Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
The symbol SRAM_VECTOR_TABLE is not used in the adi/max32 soc. Removed
it in order to clean up the Kconfig file and avoid confusion with the
upcoming new definition of SRAM_VECTOR_TABLE symbol. (PR #87468)
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Use the Zephyr cache API in soc initialization code instead of calling the
HAL directly. The change does not modify the pre-existing cache settings,
just changes the path they are enabled.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Remove the sanity check between Cube HAL SMPS symbol and Kconfig SMPS
configuration.
SMPS is available on all STM32H7R/S SoC, so misalignment isn't possible.
Additionally, point to the hal commit which revert the fix which was done
on hal_stm32 to add this symbol.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Introduces config file entries for STM32F401XD variants. The
STM32F401XD family is related to the STM32F401XE family but with a
reduced flash memory.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
lld will produce warnings for the symtab, strtab, and shstrtab sections
if --orphan-handling=warn is specified and there are no matching rules
in the linker script for these sections. Handle these sections when
building with lld to prevent the warnings.
This is exactly the same as commit
c420733c33, but for the AE350 linker
script.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
As well described in a previous PR [1], the GNU ld and LLVM lld linkers
treat the location counter (`.`) differently. lld always inteprets the
location counter as an absolute address whereas ld interprets it as an
offset from the start of the current object.
The NXP boot header linker script files use `.` assignment to specify an
offset within the rom_start region (ld-style). This causes lld to error
out since it interprets this as the location counter moving backwards.
To fix this, re-use the idea from the previous PR [1]:
replace `. = FOO` with `. += FOO - (. - __rom_start_address)`
This sets the location counter in a way that works with both ld and lld.
[1] https://github.com/zephyrproject-rtos/zephyr/pull/58315
Signed-off-by: Kesavan Yogeswaran <hikes@google.com>
Intel Audio DSP ACE needs to use arch_spin_relax() to give
the bus more time to propagate the RCW transactions among
CPUs, and to avoid sending too many requests to the bus
after failing to lock spinlocks. However, the number of
NOPs results in a very big arch_spin_relax() that spans
multiple instruction cache lines, and requires evicting
them just for NOPs. With 5 CPUs, it can span 6 cache
lines (if using nop.n instead of nop). That's a waste of
space and cache. So instead, we do a tight loop instead.
Since the SoC supports zero-overhead loops, this should
have minimal performance impact.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For some weird unknown reasons, the simulator really do not
like the cpuhold_* variables to be tightly packed together.
This results in cpuhold_spawned not being updated, and we
will be stuck in the while loop for it to be set.
Workaround this by explicitly aligning these variables on
16 byte boundary. This seems to work for now.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Provide proper adaptions as bootloader ROM offset, flash load
offset and dts definitions for the nRF54H20 iron board to make it
ready for the MCUBoot bootloader.
Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
In the default configuration, cv32a6 does not have an FPU and does not
implement RISC-V's F and D extensions.
Hence, the FPU flags should not be added.
In the future, a second SoC for cv32a6 systems with FPU can be added.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The original commit uses the incorrect value 42 for
CONFIG_MAX_IRQ_PER_AGGREGATOR for the cva6 family of SoCs,
which is the total number of IRQs in the system.
This commit corrects this to 30, the number of IRQs for the PLIC.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
In hardware, cva6 currently only provides global disable/enable
functions for the Dcache and Icache. Disabling and re-enabling them also
has the effect of flushing and invalidating the cache.
Future cva6 SoCs will add support RISC-V's standardized cache management
operations.
This commit provides a default implementation for all methods currently
part of the cache API. These implementations can be overwritten at board
or SoC level, as they use weak linking.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
This commit adds an option to verify weather the host has read the value
after the wire 3-0 bits have been updated.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
- 196kB
- 256kB
- 320kB
Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The npcx4 SoC only uses 86 NVIC IRQ numbers.
This commit updates the number from 128 to 86 to reduce the memory
usage.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Since the necessary register values are now pre-computed and
stored in the memory domain struct, we can use them directly
in various assembly locations, thus replacing the function
call to xtensa_swap_update_page_tables().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP as it is
remnant from early MMU enabling work which is not needed as
the page table code is different from early version where
the PTEVADDR would be the same for all memory domains.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch adds an header file which contains helper macros.
These macros can be used to access some device tree properties.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The samples/subsys/llext/shell_loader test fails when running as a
twister test on the stm32mp135f_dk/stm32mp135fxx platform, with the
following error:
soc/st/stm32/stm32mp13x/soc.c:46:36:
error: array type has incomplete element type 'struct arm_mmu_region'
46 | static const struct arm_mmu_region mmu_regions[] = {
This commit adds the missing arm_mmu.h include to fix the build issue.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Remove sleeptimer as default soc timer and it should be only
used as soc timer if PM is enabled.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
