MCUX_LPTMR_TIMER now defaults from the zephyr,system-timer chosen
node, so the NXP SoC defconfig defaults are no longer needed. Remove
the duplicated policy from MCXW7xx, MCXC, KE1xF, i.MX95, and
i.MX952.
The SoC-specific clock-frequency, tick-rate, and SysTick disabling
defaults remain in place and still apply when DTS selects an LPTMR as
the system timer.
Validated that MCXW and KE1xF boards select LPTMR when DTS chooses it,
MCXC444 keeps SysTick without the chosen node, and i.MX95 M7 falls back
to SysTick when the chosen node is removed.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Make the LP core image a regular sysbuild sub-image flashed to
slot0_lpcore_partition, so west flash writes MCUboot, HP and LP
in order while on-chip behavior stays unchanged.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The updated BL616 BLE controller blob calls bflb_mtimer_get_time_us()
from btblecontroller_mtimer_get_time_us(). Provide it from the hardware
port shim, backed by the Zephyr cycle counter.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The updated BL702L BLE controller blob calls bl_timer_now_us64() from
btblecontroller_mtimer_get_time_us(). Provide it from the platform
shim, backed by the Zephyr cycle counter.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Maybe there is a better way to do that, but this plugs a kconfig leak.
Anything you build has a whole lot of Kconfig specific to Realtek right
now, for example, building hello_world for native_sim, gets you this:
#
# HAL Realtek Bee Drivers
#
# CONFIG_REALTEK_BEE_ADC is not set
# CONFIG_REALTEK_BEE_CAN is not set
# CONFIG_REALTEK_BEE_CODEC is not set
# CONFIG_REALTEK_BEE_DMA is not set
# CONFIG_REALTEK_BEE_GPIO is not set
# CONFIG_REALTEK_BEE_I2C is not set
# CONFIG_REALTEK_BEE_I2S is not set
# CONFIG_REALTEK_BEE_IR is not set
CONFIG_REALTEK_BEE_NVIC=y
# CONFIG_REALTEK_BEE_KEYSCAN is not set
# CONFIG_REALTEK_BEE_MAC_802154 is not set
# CONFIG_REALTEK_BEE_PINMUX is not set
# CONFIG_REALTEK_BEE_PWM is not set
# CONFIG_REALTEK_BEE_QDEC is not set
# CONFIG_REALTEK_BEE_AON_QDEC is not set
# CONFIG_REALTEK_BEE_LPQDEC is not set
# CONFIG_REALTEK_BEE_RCC is not set
# CONFIG_REALTEK_BEE_RTC is not set
# CONFIG_REALTEK_BEE_GRTC is not set
# CONFIG_REALTEK_BEE_SDHC is not set
# CONFIG_REALTEK_BEE_SPI is not set
# CONFIG_REALTEK_BEE_TIMER is not set
# CONFIG_REALTEK_BEE_ENHTIMER is not set
# CONFIG_REALTEK_BEE_UART is not set
# CONFIG_REALTEK_BEE_USB is not set
# CONFIG_REALTEK_BEE_USING_USB_HAL is not set
# CONFIG_REALTEK_BEE_AON_WDT is not set
# CONFIG_REALTEK_BEE_CORE_WDT is not set
# end of HAL Realtek Bee Drivers
CONFIG_REALTEK_BEE_COMMON_DRIVER=y
CONFIG_WRAP_REALTEK_BEE_NVIC=y
# CONFIG_USE_REALTEK_BEE_OS_INTERFACE is not set
# end of hal_realtek (/home/nashif/zephyrproject/modules/hal/realtek)
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for pinctrl to R-Car X5H SoC. Like for other Renesas SoCs,
a node approach is implemented (no grouping approach).
Pin configuration operations can optionally be performed through SCMI
(System Control and Management Interface).
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Select the MCUX LPTMR system timer on MCXE24x only when PM is enabled
and an application or test chooses an enabled nxp,lptmr system timer
node through devicetree. This keeps non-PM applications on SysTick
while allowing PM workloads to opt in to LPTMR through their overlays.
Remove the frdm_mcxe247 power_mgmt_soc override that forced the LPTMR
timer directly so the SoC default controls the selection.
Tested on frdm_mcxe247 with tests/subsys/pm/power_mgmt_soc over
MCU-Link on COM9. The test booted once using LPTMR and reported
PROJECT EXECUTION SUCCESSFUL.
Also built tests/subsys/pm/power_mgmt_soc for frdm_mcxe247/mcxe247
after tightening the SoC default condition. The generated configuration
kept CONFIG_MCUX_LPTMR_TIMER=y and left CONFIG_CORTEX_M_SYSTICK unset.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
CMSIS SystemInit() disables the internal hardware watchdog by default
(DISABLE_WDOG defaults to 1). MCXE24x previously forced DISABLE_WDOG=0
as a global compile definition from the SoC CMakeLists, leaving the
watchdog running even when no driver was responsible for servicing it.
On frdm_mcxe247 this made every application reset-loop.
Scope the bridge to the MCUX HAL library instead of the whole build and
drive it from Kconfig, so a SoC opts in only when its CMSIS SystemInit
honors DISABLE_WDOG:
- HAS_MCUX_SYSINIT_DISABLE_WDOG: capability selected by the SoC.
- MCUX_SYSINIT_KEEP_WATCHDOG: enabled only when an enabled watchdog
driver supports the boot-time disable policy and the application asks
to keep the watchdog running (WATCHDOG && HAS_WDT_DISABLE_AT_BOOT &&
!WDT_DISABLE_AT_BOOT).
The MCUX HAL CMake then applies DISABLE_WDOG=0 to the hal_nxp library
only; MCXE24x selects the capability and the SoC CMakeLists no longer
defines the macro globally.
Tested on frdm_mcxe247 over MCU-Link: tests/kernel/common (the reset
loop reproducer from #109911) boots once and runs to PROJECT EXECUTION
SUCCESSFUL, and samples/hello_world boots cleanly. Confirmed that
DISABLE_WDOG=0, when active, is applied only to the hal_nxp library
sources (including system_MCXE247.c) and to no kernel or application
source.
Fixes#109911
Signed-off-by: Holt Sun <holt.sun@nxp.com>
PIC32CX SG has a 0x400 byte alignment requirement for the vector table.
The default ROM_START_OFFSET of 0x200 from Kconfig.zephyr causes a
mismatch between where MCUboot jumps and where the vector table is
located.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Add set_sai_clock() to configure the full SAI clock chain:
- AUDIOPLL1_VCO: 3932.16 MHz
- AUDIOPLL1: 393.216 MHz
- SAI (per instance): parent = AUDIOPLL1, rate = 12.288 MHz
The AUDIOPLL1 chain is initialized only once via set_audiopll1_clock()
using a static flag, regardless of how many SAI instances are enabled.
The clock ID for each SAI instance is read from the DTS clocks property
via DT_CLOCKS_CELL_BY_IDX. DT_FOREACH_STATUS_OKAY with SAI_CLOCK_SETUP
macro automatically applies the configuration for all enabled SAI
instances, following the same pattern as FLEXCAN_CLOCK_SETUP.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
Add a new SoC variant SOC_V8A_AARCH32 with the Cortex-A32 as the
default processor to the fvp_aem series for the FVP AEM running in
ARMv8-A AArch32 execution state. Add AArch32 specific MMU region
configuration and linker script selection to support this.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Move the SOC_FAMILY_ARM64 selection from the series-level
SOC_SERIES_FVP_AEM to each individual AArch64 SoC variant
(SOC_V8A, SOC_V9A, SOC_A320). This allows an AArch32 SoC
from the same series to select SOC_FAMILY_ARM independently.
No functional change for existing AArch64 builds.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
This commit disables usb host/device on gpio pins by default during
early soc initialization.
Also update uart initialization to be devicetree-aware. uart1 and
uart2 configuration is now conditionally enabled based on dt node
status, instead of unconditionally configuring both.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Enable PLIC and RISC-V interrupt support for the Nitrogen platform.
Add offset of 2nd level interrupts (PLIC) and total number of IRQs.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add a "silabs nwp_version" shell command that prints the NWP firmware
version (chip_id, rom_id, major, minor, security, patch, customer_id,
build_num).
With the optional -c flag, the command also checks the version against
siwx91x_nwp_fw_expected_version and returns -EINVAL if major, minor or
security_version do not match.
The command is controlled by CONFIG_SIWX91X_VERSION_SHELL (default y)
which depends on SILABS_SIWX91X_NWP and SHELL.
Assisted-by: Copilot:claude-sonnet-4.6
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add silabs_shell.c which owns the SHELL_SUBCMD_SET_CREATE and
SHELL_CMD_REGISTER for the "silabs" top-level shell command. This
allows multiple SoC-specific files to register subcommands independently
using SHELL_SUBCMD_ADD without duplicating the namespace registration.
Add a hidden Kconfig symbol SOC_SILABS_SHELL (selected by any feature
that registers a subcommand) that controls compilation of silabs_shell.c.
Convert siwx91x_fota_shell.c to use SHELL_SUBCMD_ADD, and make
SIWX91X_FIRMWARE_UPGRADE select SOC_SILABS_SHELL.
Assisted-by: Copilot:claude-sonnet-4.6
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Wire the on-chip Ethernet MAC and MDIO controller on the ESP32-P4
into the eth_esp32 driver. Includes the DT nodes (eth, mdio),
espressif,esp32-eth binding refresh, board pinctrl entries for
RMII and SMI, board defconfig and Kconfig fragment enabling
NET_L2_ETHERNET, and the SoC P4 Kconfig options for buffer count
and size. Adds the related pinctrl table entries and GPIO signal
map values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
For i.MX95 M7 MCUX_LPTMR_TIMER defaults to y if COUNTER_MCUX_LPTMR
not enabled.
This prevents us on enabling CORTEX_M_SYSTICK. So refine the condition
so that MCUX_LPTMR_TIMER only defaults to enabled if COUNTER_MCUX_LPTMR
not set (as it is now) and also add condition that zephyr,system-timer
is actually set.
This also moves DT_CHOSEN_ZEPHYR_SYSTEM_TIMER,
DT_CHOSEN_ZEPHYR_SYSTEM_TIMER_PATH definitions at the top of the file.
Fixes: 0c4382ae5e ("drivers: timer: keep mcux_lptmr policy explicit")
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Specifically configure IFX_UART_ENABLED as OFF for
Zephyr's integration of tf-m for pse84.
Additionally move the pse84 specific configuration
from the tf-m CMakeLists to the soc level one.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Update common AIA coordinator shared by IMSIC and direct mode to
initialize based on which APLIC mode is configured in DT.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
- enable MONOLITHIC_NBU for NXP_IEEE802154_MAC for rw61x
- update hal_nxp ieee_802_15_4 module to 26.06.00-pvw2
Signed-off-by: Laurent Clementine <laurent.clementine@nxp.com>
Signed-off-by: George Stefan <george.stefan@nxp.com>
Replace LOG_MODULE_DECLARE with LOG_MODULE_REGISTER to properly
initialize the 'soc' log module and prevent missing log output.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
It is not called during usage and blob shall not be allowed to do that,
as it is already calibrated at boot.
Signed-off-by: Camille BAUD <mail@massdriver.space>
UART_NS16550 already defaults to y,
if it is enabled in the dt. no need to add a soc
specific default.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add internal API header for the HPPASS_CSG_MFD sub-driver. Handles
registering individual slice callbacks for the comparator to the shared
handler in the MFD.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
This defines a custom MPU memory types according to memory being
used.
Also fix the length of vec_helpers section.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes xtensa_soc_mpu_ranges[]. SoC or board needing their
own memory regions should override xtensa_mpu_ranges[] in their
own layer.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
All cores should be flashed before reset is applied.
This avoids situations where appprotect is enabled
before flashing is completed.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Enable the Wakeup Controller (WUC) subsystem for MCXW7xx SoCs when the
WUU (Wakeup Unit) device tree node is enabled.
Drop the SoC-local mcxw7xx_set_wakeup() shim and the
NXP_ENABLE_WAKEUP_SIGNAL() override: LPTMR0 wakeup is now configured by
the LPTMR timer driver via wuc_enable_wakeup_source_dt(), and NBU
wakeup is configured by the common NBU init code from the new
"wakeup-ctrls" property.
Add test overlay for frdm_mcxw72 board to validate WUC API.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Allow nodes with compatible "nxp,nbu" to declare a "wakeup-ctrls"
property by including wuc-device.yaml in the binding, and consume it
from the common NBU init code via wuc_enable_wakeup_source_dt().
When the property is absent, the existing NXP_ENABLE_WAKEUP_SIGNAL()
fallback path is preserved, so no in-tree user changes behavior here.
A failure from wuc_enable_wakeup_source_dt() is now logged and
propagates as an early return, which previously would have been
silently swallowed.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Currently, CONFIG_WIFI_SILABS_SIWX91X_ROAMING_USE_DEAUTH simply enables
the SL_SI91X_CUSTOM_FEAT_ROAM_WITH_DEAUTH_OR_NULL_DATA bit in
custom_feature_bit_map. However, setting that bit in the opermode
configures roaming to send a null data packet when roaming.
To configure sending a deauth, that bit must be unset.
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
These SoCs are provided with:
- Arm Cortex-A720AE application cores (8 clusters x 4 cores)
- Arm Cortex-R52 real-time cores (3 clusters x 4 cores)
- Arm Cortex-M33 system control processor
Signed-off-by: Julien Panis <jpanis@baylibre.com>
- Adapt to new MCXW7x clock control
- disable HDI pins
- use flw on non secure range
- enable lpuart1 and use it for uart-pipe, bt-c2h-uart and shell-uart
- configure sys clock to 96MHz for core0 and 48MHz for core1
- use PTA18 for LPUART0 RX pin as workaround for board issue
- fix LPTMR clock source to 32K
- place main stack at beginning of the RAM to workaround boot issue
- move shared memory to third bank (instead of the second) - last 8K
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
WiseConnect zeros the BT half of its cached coex performance profile
on every Wi-Fi disconnect, leaving BT out of power save and preventing
the NWP from sleeping after re-association.
Delegate Wi-Fi power-save to siwx91x_nwp_apply_power_profile(), which
already owns both BT and Wi-Fi halves of the coex profile. Extend the
helper to accept an optional sl_wifi_performance_profile_v2_t override
so the Wi-Fi driver can pass its tailored profile (listen_interval,
dtim_aligned_type, monitor_interval); BT-only and init call sites pass
NULL to keep their current behaviour.
Signed-off-by: Tejus Subramanya <ters@silabs.com>
Adding missing comp3 & comp4 node to g4 (all g4 have 4 comparators).
Adding missing comp5, comp6 & comp7 to stm32g473 (all g473 and derived
types have 7 comparators).
Add configdefaults for SHARED_IRQ_MAX_NUM_CLIENTS and SHARED_INTERRUPTS
to the soc's Kconfig.defconfig.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Add support for NXP i.MX952 SoC Cortex-M7 core:
- Add SoC configuration and Kconfig files
- Add M7 core specific initialization code
- Add pinctrl definitions for i.MX952
- Add SCMI CPU management support
- Update imx9 CMakeLists to include imx952 subdirectory
- Register imx952 series in soc.yml
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
Add HP-core and LP-core support for the ESP32-P4 SoC: boot
init, PMP regions, IRQ and vector tables for both cores,
linker scripts (default, mcuboot, LP-core), memory map and
pinctrl SoC layer.
Register the SoC family in soc.yml with hpcore and lpcore
cpuclusters and plug it into the existing common Kconfig
fragments (ULP, console, esptool, spiram, defconfig) and the
shared bootloader loader.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the ESP32-P4 specific sleep configuration on top of the
common power-down support: the DCM sleep voltage and the flash
ready extra delay options, plus the clock ICG retention init and
LP clock (FOSC) narrowing in the shared sleep_retention_init().
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
