SoC series such as AM62x and AM62Lx use the GIC500 module. This module
supports up to 16 SGIs, 16 PPIs and 960 SPIs. This comes to a total of 992
interrupts. Hence, update the NUM_IRQ to match this number.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
- Added autanalog MFD support in PSE84 DTS files
- Refactored autanalog ADC in PSE84 to use a common
MFD for handling the global AC configuration
- Constructed AC to use phandle in the overlay
for a better the user experience.
- Added support for a basic and advanced mode
with custom AC
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Convert three NXP drivers from raw DT_REG_ADDR() register access
to the Zephyr device MMIO API (DEVICE_MMIO_ROM / DEVICE_MMIO_RAM /
DEVICE_MMIO_MAP):
With the MMIO API, the drivers create their own mapping at init time via
DEVICE_MMIO_MAP() thus the corresponding mmu_regions entries are removed
from the five NXP SoC files that carried them.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit introduces the CONFIG_ESP_SPIRAM_BSS_RELOC_LIBS_AND_OBJS
parameter that when filled in with a list of library and/or object file
names and having the parameter CONFIG_ESP_SPIRAM enabled will allow that
.bss segments of such files be placed in .ext_ram.data section
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Now that CPU_CORTEX_A selects KERNEL_DIRECT_MAP when MMU is enabled,
there is no need for individual ARM64 board defconfigs or SoC Kconfig
files to enable it explicitly.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The STM32F777 is a variant of the STM32F767 that adds a hardware
crypto accelerator (CRYP). Add SoC support by including the
stm32f767.dtsi and extending with the CRYP peripheral node.
Fixes: #105976
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
Add targets to the UICR generator image that validates and/or prints
the register configurations in the generated PERIPHCONF blob:
* periphconf_validate (only check for errors)
* periphconf_dump (print entire blob, also prints errors)
* periphconf_dump_raw (same as periphconf_dump but with hex values)
Equivalent targets exist for SECONDARY PERIPHCONF:
* secondary_periphconf_validate
* secondary_periphconf_dump
* secondary_periphconf_dump_raw
The new validation replaces the old conflict detection
("PERIPHCONF has conflicting registers") and adds more checks.
PERIPHCONF registers are now also by default printed out in a human
readable format instead of by raw hex address and value.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
The cm33 defaults to a secure state and we don't enable the MPC,
PPC, SAU, etc which all stay in their default states. To support
the HWINFO driver, we need the SAU enabled so the cm33_s can access
the device UID which is stored in non-secure memory.
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Used Zephyr inline register access functions (sys_read/write)
instead of CMSIS register structure.
Used soc helper api to access/configure girq registers.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add an RT118x ARM PLL binding wrapper that reuses the shared
loop-div/post-div schema and derive CLOCK_InitArmPll() directly
from devicetree.
RT118x keeps the new loop-div/post-div properties only and removes
the hard-coded loop and post divider values from the SoC init path
while retaining the HAL loop divider range check.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace the fixed-factor-clock compatible with an RT11xx ARM PLL
binding that shares the loop-div/post-div schema through a common
include.
The RT11xx wrapper keeps the deprecated clock-mult/clock-div
properties and the SoC code falls back per property so existing
definitions keep working while new overlays can switch to
loop-div/post-div.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace WAIT_FOR macro with a simple do-while loop in is_memory_ready()
used by the SMIF PM callback.
WAIT_FOR uses kernel timing functions which reside in flash.
During CY_SYSPM_AFTER_DS_WFI_TRANSITION callback
execution, the flash (SMIF) is being re-enabled and the external memory
may not be ready yet. Calling flash-resident kernel functions at this
point causes a hardfault.
The do-while loop uses only:
- Cy_SMIF_Memslot_IsBusy() - relocated to RAM
- Cy_SysLib_DelayUs() - located in RAM
This avoids any flash access during the early wake-up phase when flash
is not yet accessible.
Signed-off-by: Merin George <merin.george@infineon.com>
This is a direct copy from arch/xtensa/core/mem_manage.c.
It is moved here as the checks are really SoC specific and
should not be in the architecture code at all.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When AES is activated in the DT, configure it's register region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add shared interrupt support for STM32 UART on SoC families where
multiple USART/LPUART peripherals share a single IRQ line (F0, G0,
L0, U0, C0).
Add a compile-time BUILD_ASSERT in the STM32 UART driver that detects
when two or more enabled UART instances share an IRQ and
CONFIG_SHARED_INTERRUPTS is not set.
Add configdefault SHARED_INTERRUPTS and SHARED_IRQ_MAX_NUM_CLIENTS
to the SoC Kconfig for STM32F0x, STM32L0x, STM32U0x, and STM32C0x.
Update DTS comments in the F0 family that previously stated shared
UART IRQs are unsupported.
The SHARED_IRQ_MAX_NUM_CLIENTS combinations in the F0x Kconfig were
generated with:
from itertools import combinations
usarts = ['usart3','usart4','usart5','usart6','usart7','usart8']
for n in range(6, 2, -1):
for combo in combinations(usarts, n):
conds = ' && '.join(
f'$(dt_nodelabel_enabled,{u})'
for u in combo)
print(f'\tdefault {n} if {conds}')
Fixes zephyrproject-rtos#39565
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
Check for secondary RV32 support by way of devicetree checks, not enabling
explicitly for each SoC in Kconfig.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add Kconfig options to allocate OpenThread dynamic memory and message
pool buffer from external memory on ESP platforms:
- OPENTHREAD_EXTERNAL_HEAP_SHARED_MULTI_HEAPOPENTHREAD_HEAP_EXTERNAL:
routes otPlatCAlloc/otPlatFree through shared multi-heap to allocate
from external memory.
- OPENTHREAD_MESSAGE_POOL_CUSTOM_SECTION: places the message pool
buffer in a custom .ot_msg_pool linker section.
- Add .ot_msg_pool section to external RAM in the linker
script for ESP32, ESP32-C5, ESP32-S3, ESP32-S3
This allows offloading large OpenThread buffers to PSRAM, freeing
internal SRAM for other uses.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
In 7579ccc68e (modules: hal_nordic: nrfs: Fix initialization priority)
used wrong priority as it assumed that NRFS is using IPC service init
priority. Priorities are fixed now and static assert is added to ensure
that NRFS init priority is higher than IPC service.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
sys_clock_set_timeout() and sys_clock_elapsed() are now documented
as requiring the system clock lock to be held by the caller. Wrap
the calls in subsys/pm/pm.c, soc/nxp/rw/power.c and the kernel
shell thread list command with sys_clock_lock()/sys_clock_unlock().
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
runtime_idle, also called standby in SiWx91x HAL power manager
did not need to check if it can go to sleep, reconfigure wireless
control after standby, or generate a synchronization event with
the NWP (network coprocessor) when the SoC exits runtime_idle.
This fixes a bug where the shell application is not responsive
with PM enabled. Since the system stays in runtime_idle due to
UART activity for the shell, interrupt information from the NWP
can be lost due to reconfiguration when exiting standby.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Previously, the purpose of disabling AVPLL and TDDR is to save power
consumption in low power. But all examples of RW612 use clock_init()
and disable AVPLL and TDDR without condition check is not proper.
Move disable AVPLL and TDDR to condition when they are not in use.
The ethernet uses TDDR clock and enet is enabled by default for RW612.
Add CONFIG_ETH_DRIVER along with enet and CONFIG_NET_L2_ETHERNET in
clock_init(). If any of the condition is not match, the TDDR clock
will be disabled.
Signed-off-by: Hui Bai <hui.bai@nxp.com>
After commit b1afb494b0, zephyr,flash points to the
soc-nv-flash child node instead of the
nxp,imx-flexspi-nor controller. This shifts the DTS
hierarchy by one level, so
DT_PARENT(DT_CHOSEN(zephyr_flash)) now returns the
flash controller node, not the FlexSPI bus node.
Use DT_CHOSEN(zephyr_flash_controller) to directly
reference the flash controller, and DT_PARENT of it
to reach the FlexSPI bus where needed.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Having a differing number of ACL buffers available between the host
and controller causes unnecessary "impedance" when communicating over HCI.
The Zephyr Bluetooth host also warns about this during initialization:
Num of Controller's ACL packets != ACL bt_conn_tx contexts (15 != 3)
Update the default for BT_BUF_ACL_TX_COUNT to match the controller. Also
update BT_BUF_EVT_RX_COUNT and BT_CONN_TX_MAX appropriately. The latter
should generally match TX_COUNT, while the former needs to be at least as
large to deal with Number of Completed Packets events from the controller.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The syslib delay function are implemented in an assembly file.
Even with the relocation done in CMakeLists.txt this file does not
properly get copied because gen_relocate_app.py does not keep
in consideration plain regions (e.g. just .text rather than .text.xyz).
Therefore force the relocation using the ramfunc and itcm linker
section for cm33 and cm55 respectively.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
The linker region rwdata was including sections ramfunc
and itcm which should instead be placed in a code region.
Created itcm_mem.ld and ramfunc_mem.ld for cm55 and
cm33 respectfully to place the section accordingly.
Added the linker sources in cmakelists.txt
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Now that the cores have dedicated executable regions
for the code relocation, give executable permissions only
to those rather than the entire RAM region.
Additionally, removed the rwdata exception for the assembly
file given that it now gets properly placed in the correct region
by the relocate script.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Change 'select ARM_MPU' to 'imply ARM_MPU' so that tests and
applications can override it with CONFIG_ARM_MPU=n. The previous
'select' caused a prefetch abort in the LLEXT module_build sample,
which disables MPU to allow execution from heap-allocated memory.
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
The SPI SRAM memory test runs on the entire mapped PSRAM
region during boot. At lower clock speeds (e.g. 40MHz),
this can take over 10 seconds for a 4MB device, delaying
startup significantly.
Remove the default y so the memtest is opt-in. Users can
still enable it with CONFIG_ESP_SPIRAM_MEMTEST=y when
needed for hardware validation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The SPIRAM heap address was set from the linker symbol
_ext_ram_heap_start, which may not match the actual MMU
mapping at runtime. On SoCs with unified cache (C5, C6,
H2), the virtual address depends on MMU page allocation
and can differ from the linker estimate.
Use esp_psram_get_mapped_region() to obtain the actual
mapped address and size at runtime.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The ext_dram_seg was placed at DROM_SEG_ORG + DROM_SEG_LEN
(0x43000000), but the MMU maps PSRAM into the first free
pages in the unified cache address space (0x42000000+).
This mismatch caused the SPIRAM heap to point to unmapped
memory, resulting in data corruption and crashes.
Move ext_dram_seg origin to IROM_SEG_ORG and add an
.ext_ram.dummy section that skips past both IROM and DROM
MMU page reservations, matching the runtime behavior of
esp_mmu_map_reserve_block_with_caps().
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
soc_random_enable() was called inside hardware_init() which
only runs for CONFIG_MCUBOOT and CONFIG_ESP_SIMPLE_BOOT. For
MCUboot-loaded apps (CONFIG_BOOTLOADER_MCUBOOT), hardware_init
is skipped, so soc_random_enable() never ran. However,
soc_random_disable() was called unconditionally in loader.c,
causing periph_module_disable() to decrement the peripheral
clock reference counter below zero. This prevented
periph_module_enable() from actually enabling the hardware
clock for any peripheral touched by soc_random_disable(),
such as I2S0 on ESP32, breaking drivers that depend on it.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Move to the post kernel. Set priority which is higher than the
IPC service and NRFS.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Wrap BT controller initialization with CONFIG_BT to prevent its
background thread from starting in non-Bluetooth applications.
This avoids unexpected preemption that causes kernel scheduler tests
like `priority_preemptible_wait_prio` to fail.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Setting NUM_IRQS on RISC-V core to only the IRQ's used (up to GPIOTE30_1)
where VREGUSB, LFXO, LFRC, HFXO64M, AUXPLL interrupts aren't
used in drivers.
This is because on RISC-V with CONFIG_RISCV_GP, the linker may relax
accesses to some globals into gp-relative instructions; the offset from
__global_pointer$ to each such symbol must fit in a 12-bit signed range
(+/-2 KiB). _sw_isr_table in RAM is NUM_IRQS × 8 bytes and sits between
small data and much of .bss, so a smaller NUM_IRQS shortens that gap
and can keep symbols such as _kernel within gp-relative range, avoiding
R_RISCV_GPREL_I relocation truncation at link time.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Prevent unused function warning that comes from having a control module
node but no ti,unlock-offsets property. Do this by checking for the
aforementioned property alongside already present compat string.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
RT1166 and RT1176 CM4 parts use the MCUX LMEM cache block
and expose both code and system-bus cache in their HAL
feature headers.
Select the LMEM cache driver path, advertise both ICACHE
and DCACHE, and default these CM4 builds to
CACHE_MANAGEMENT with the external cache driver.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
This commit introduces 2 changes:
- cleans up the mpu initialziation, the old function is not
required because the initialziation is done properly via
mpu_regions.c for all cores
- defaults to using SystemCoreClockSetup instead of
SystemCoreClockUpdate because the former takes the
input from DT whereas the latter would read the info
from the HF clocks which in case of TF-M are secured
and not directly accessible from the cm33/ns (if SRF is
not set up)
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
71aa3be37b removed the directive which used
to source these files but forgot to delete them - do so now.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
