Cosmetic change to align code style when initializing DSP registers. The
code in intel_is_ace() branch was moved as-is from acetool.py when the
two tools were merged to make reviewing easier. Fix the code style to be
coherent in the merged cavstool.py. No functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Use the correct register to read ROM status on intel_adsp_ace20.
Without this this fix, firmware load is successful but
boot takes extra 2 seconds and following warning was emitted:
WARNING:cavs-fw:Load failed? ROM_STATUS = 0x0
The log-only mode (-l) was not working at all and is fixed
by this commit.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This adds support for the local APIC in one-shot mode as the timeout
event source for those cases where the CPU supports invariant TSC but
no TSC deadline capability. It is presented as another timer choice.
Existing Kconfig symbols were preserved to minimize board config
disturbance.
This hybrid approach was implemented kind of backward in the apic_timer
driver but it is far cleaner to carry this here.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Added ADI MAX series soc, first partnumber is MAX32690
The family structure will be
ADI_MAX
MAX32xxx
MAX32655
MAX32655EVKIT
MAX32655FTHR
MAX32666
MAX32666FTHR
MAX32666FTHR2
MAX32690
MAX32690EVKIT
MAX78xxx
MAX78000
MAX78002
...
When MAX32 MCUs goes to sleep mode debugger could not access it
and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent
the CPU from actually entering sleep
by skipping the WFE/WFI instruction.
Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user
space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK.
If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y)
devicei will not goes to sleep mode in idle state.
To disable it add below line in your configuration file
CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n
MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core
support.
Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The software protocol to write status value of 0x05 (FW_ENTERED)
into memory window 0 at Zephyr boot, is not needed in the ace1.x
boot flow and does not match the semantics host systems are expecting
at this location in the memory window (e.g. write of 0x05 is not
expected).
Make this logic specific to intel_adsp_cavs platforms and move the code
out from common intel_adsp code.
This commit depends on update to cavstool.py to use correct
ROM status register to observe boot state.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Starting with ace1.x, the boot status is no longer reported by
the boot ROM in the SRAM status window as it was done in older
platforms. The current cavstool.py code works on these newer platforms,
as Zephyr soc bootcode writes to same location, but this is not
the recommended boot flow.
Modify boot flow to use a dedicated register to observe boot
state. This change improves usability of cavstool.py on ace1.x
platforms as:
- it is possible to start cavstool.py (e.g. in log-only or shell mode)
while DSP has been already been booted, but is currently in
low-power mode (and SRAM window is not accessible from host)
- more reliable boot and better error reporting as actual ROM
status is observed
Furthermore, this change allows to remove the memory window
writes from Zephyr intel_adsp boot_complete(). This IPC interface
is application and IPC revision specific and the write should not
be done in generic Zephyr SoC code. However, to keep cavstool.py
working, the tool has to be updated first.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit defines the bt-hci subnode under the bleif node on
Ambiq Apollo3 Blue and Apollo3 Blue Plus SOC.
Also add the default configurations for Bluetooth feature on Ambiq
apollo3_evb and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.
Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
k_sem_init() is called for every IPC message sent in
intel_adsp_ipc_send_message(). This has not had any side-effects
in upstream configurations, but has been linked to a failing
run of test_obj_tracking_sanity test case in downstream Zephyr
use.
Replace k_sem_init() with k_sem_reset() as this is more appropriate
API to reset the semaphore count, and ensure deterministic
behaviour in case a thread is waiting on the semaphore at time
of reset.
Suggested-by: Peter Mitsis <peter.mitsis@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Adding supporting soc files for the ke1xz platforms
updating soc.yaml and kinetis soc files
to support ke1xz.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Pavel Krenek <pavel.krenek@nxp.com>
Remove all the hard-configured absolute addresses and zillions of tiny
ELF segments in favor of the auto-generated vector region, which is
guaranteed correct as long as core-isa.h is matched to the target.
Signed-off-by: Andy Ross <andyross@google.com>
Add header file for flash configuration blocks
which is an image header consumed by the RW bootrom.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add new Microchip MEC chips using the new MEC5 HAL and
add a HAL version of a legacy chip named MECH172x.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Corrected virtual memory size to match the range supported by the
Translation Lookup Buffer. The TLB size is 16 MB, however the first 128 KB
is dedicated to LPSRAM and bypasses the TLB. This was taken into account in
KERNEL_VM_BASE, so KERNEL_VM_SIZE was reduced accordingly.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The script runs as part of the build now. Use that feature and
remove the old static file from the manually-run script.
Signed-off-by: Andy Ross <andyross@google.com>
Merge codebases of cavstool.py and acetool.py as the two have
a lot of duplicated code.
To ease with transition, keep acetool.py around with implementation
imported from cavstool.py. This will help to keep any automated
testing flows working that assume both tools exist.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The nRF54H20 EXMIF peripheral requires word accesses. Doing accesses of
byte or half-word sizes results in bus fault.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
RC32K and RCX low power clocks require runtime calibration to work
correctly.
Frequency of those clock can differ from chip to chip, one constant
value from Kconfig may not be best when low power clock (sourced
from RCX or RC32K) is used for system tick.
This code modifies global z_clock_hw_cycles_per_sec variable that
is used when TIMER_READS_ITS_FREQUENCY_AT_RUNTIME is enabled
in Kconfig.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
In preparation for simulated nRF54L targets,
let's add kconfig options aking to the ones
we have for the nRF52 and 53 devices.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add the Kconfig options and use the aliased
addresses for the bootcode regions of the IMX7D
and IMX6SX SOCs to allow the Linux rproc
framework to load the irq-vectors into
the correct memory areas.
Activating this option might enlarge the bin
file if the zephyr,flash and rom_start chosen
region addresses are not matching.
It is up to the user to enable this feature
based on code location choices (OCRAM, DDR, TCM...).
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
Align SYS_CLOCK_HW_CYCLES_PER_SEC with other SMP nSIM
configurations and set it to 1000000.
This significantly reduce verification time on HS5x platforms.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Add DT node entries to RW for DAC and ADC.
Support the SOC required initialization of the DAC and ADC on RW.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
