Commit graph

6301 commits

Author SHA1 Message Date
Marek Maškarinec
64984bb618 soc: st: Add stm32l083xx
Add stm32l083xx SoC variants that are similar to stm32l073xx with an added
AES accelerator.

Signed-off-by: Marek Maškarinec <marek.maskarinec@hardwario.com>
2025-09-12 18:31:55 +02:00
Vit Stanicek
84373c4c64 soc: mimxrt685s/hifi4: Fix HW cycle count
Change hardware cycle count (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) to 594
MHz. Move that value to the SoC layer's DT.

Validated with the amp_blinky example - the period of the blinking LED
is exactly 2 seconds, like was programmed.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-09-12 13:21:24 +02:00
Marek Matej
3476212f72 soc: espressif: esp32h2: remove kernel include
Remove unnecessary include from ESP32-H2 SoC sources.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-09-12 13:21:02 +02:00
Tim Lin
24de607380 drivers/i2c: it8xxx2: Allow I2C target entry power saving mode
Add I2C_TARGET_ALLOW_POWER_SAVING config. Enable this config makes I2C
target device can enter Doze/Deep doze states while the bus is idle.
Ongoing transfers will block low-power entry until they are completed,
ensuring correct communication while still reducing overall power
consumption.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-09-12 13:20:51 +02:00
Thomas Stranger
0414683260 soc: st: stm32: add stm32c051 support
Add STM32C051 to the STM32C0 series

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2025-09-12 08:20:07 +01:00
Sylvio Alves
9b16701f8e soc: espressif: place arch_common in IRAM for proper boot
Ensure sw_isr_common, dynamic_isr, and init routines are executed from IRAM
by relocating libarch__common.a section.

Running these from flash prevents the board from booting properly, as flash
access is not available during early initialization.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-09-11 18:09:32 +01:00
Ayush Singh
881cc72183 soc: ti: k3: Add support for AM6254 A53 cores
- AM6254 is a variant of AM6234 with GPU.
- Used in rev A1 of PocketBeagle 2

Signed-off-by: Ayush Singh <ayush@beagleboard.org>
2025-09-11 18:07:17 +01:00
Ayush Singh
a60167c7f7 soc: ti: k3: Add support for AM6254 m4f
- AM6254 is a variant of AM6234 with GPU.
- Used in the rev A1 of PocketBeagle 2

Signed-off-by: Ayush Singh <ayush@beagleboard.org>
2025-09-11 18:07:17 +01:00
Adam Kondraciuk
8a5365c26c soc: nordic: nrf54h: s2ram: Add FPU retention
Add FPU power management for suspend to RAM procedures.
Add FPU save/restore procedures when `FPU_SHARING` feature
is disabled.

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
2025-09-11 06:26:49 -04:00
Khoa Nguyen
7ea7e13b9c soc: renesas: ra: Update init flow to start second core
- Add ``R_BSP_SecondaryCoreStart`` for the primary core to start
the secondary core
- Disable ``clock_init`` for the secondary core

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2025-09-11 09:53:13 +02:00
Khoa Nguyen
614889b32b soc: renesas: ra: Add configs to enable building second core app
Add configs to enable building the second core app

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2025-09-11 09:53:13 +02:00
Khoa Nguyen
8a1118f03c soc: renesas: ra: Correct the duplicate section for ek_ra8p1
Correct the duplicate section for Renesas ek_ra8p1

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2025-09-11 09:53:13 +02:00
Clark Kim
4f948f15af soc: nxp: imxrt7xx: Add pmic interrupt APIs
Add pmic interrupt enable/disable/clear APIs

Signed-off-by: Clark Kim <clark.kim@nxp.com>
2025-09-10 22:44:33 -04:00
Muhammad Waleed Badar
7601db8e4e soc: esp32: Enable ESP32_REGION_1_NOINIT by default
Use DRAM region 1 as the default spill area for the `.noinit`
section if appcpu is not present

Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
2025-09-10 22:39:04 -04:00
Sanjay Vallimanalan
199017fa94 soc: mspm0: add poweroff support
add support for SHUTDOWN operating mode in TI MSPM0 series for power-off
operation. Uses HWINFO for reset cause detection to handle shutdown IO
release on low power wakeup.

Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2025-09-10 18:37:11 +02:00
Sanjay Vallimanalan
0c7edef7ad soc: mspm0: add power management support
TI MSPM0 series supports range of power modes (RUN/SLEEP, STOP, STANDBY)
supporting low power operations. Provides automatic restoration to
RUN mode on wakeup from any low power state.

Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2025-09-10 18:37:11 +02:00
Luca Burelli
26fd9a691e soc/ambiq/apollo5x: fix ARMV8_1_M_PMU_EVENTCNT being globally set
Other targets that define this symbol do it in the Kconfig file, and
gate it with a SOC_ model or series symbol. Defining a default in the
Kconfig.soc instead applies it on every build, which is not desired.

Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
2025-09-10 16:40:27 +02:00
Sebastian Bøe
50d7308473 soc: nordic: nrf54h: Add support for CPURAD DEBUG_WAIT
Add support for halting the Radio core immediately after reset. This
ensures that a debugger can attach and take control from the very
first instruction.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-09-10 16:40:19 +02:00
Bjarki Arge Andreasen
00afc18985 soc: nordic: nrf54h20: enable PM_DEVICE_RUNTIME if PM by default
PM on the nrf54h20 has minimal utility if power domains and devices
are not managed at runtime, as these prevent the soc from entering
sleep states in the first place. Enable PM_DEVICE by default if PM,
which in turn enables PM_DEVICE_RUNTIME for devices and power
domains.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2025-09-10 16:40:11 +02:00
Danny Oerndrup
912ffe27df soc_native: Fix missing include of stdbool.h
The header posix_soc.h was missing include of stdbool.h as bool is used
as a function parameter.

Signed-off-by: Danny Oerndrup <daor@demant.com>
2025-09-10 13:02:58 +02:00
Aksel Skauge Mellbye
188627f61d soc: silabs: Support image properties for Series 2
Add image properties data structure to Series 2 binaries.
This data structure is used by the SE or bootloader to enforce
secure boot, and by other tools to extract image information.

Use the app version if set, or fall back to the kernel version
for the image version field. Set image type based on Kconfig
options.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-09-10 13:02:48 +02:00
Sebastian Bøe
363bad0705 soc: nordic: ironside: Clean up error code docs
Clean up error code docs.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-09-09 19:05:47 -04:00
Sebastian Bøe
377a18caee soc: nordic: ironside: Add bootmode service
Added support for the IronSide bootmode service which allows requesting
a reboot into secondary firmware boot mode. In this mode, the secondary
configuration defined in UICR is applied instead of the primary one.

The service provides the ironside_bootmode_secondary_reboot() function
that can pass message data to the boot report of the CPU booted in the
secondary boot mode.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-09-09 19:05:47 -04:00
Anas Nashif
f5d7081710 kernel: do not include ksched.h in subsys/soc code
Do not directly include and use APIs from ksched.h outside of the
kernel. For now do this using more suitable (ipi.h and
kernel_internal.h) internal APIs until more cleanup is done.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-09-09 11:45:06 +02:00
Yongxu Wang
cfb1ae4efe soc: nxp: imx95: set and restore wakeup irq mask in pm context
The CMC interface controls the entry and exit of the
CPU's low-power mode and the identification of the wake-up source.
To ensure the normal operation of the system's low-power timing sequence,
when transfer IDLE_RUN to IDLE_SLEEP, it is necessary to ensure
that the system is not awakened by the wake-up source during this stage.
Therefore, an IRQ MASK needs to be set on the CMC

Before the CPU enters the low power mode, a wake up mask needs to be set
according to the situation where the interrupt controller is enabled
at that time.
After the cpu exits the low power mode, resume needs to be performed

Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
2025-09-09 10:31:22 +02:00
Andre Heinemans
1282481654 soc: nxp: imx95: increase ROM_START_OFFSET in case of BOOTLOADER_MCUBOOT
The insertion of MCUBOOT header will shift the rom code ahead with
0x800 bytes because of memory alignment

Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
2025-09-09 07:35:15 +02:00
Sebastian Bøe
3648cd87d4 soc: nordic: gen_uicr: Support secondary firmware
Add support for secondary firmware in gen_uicr.py.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-09-08 15:52:20 -04:00
Sebastian Bøe
67b0e045eb soc: nordic: Update UICR format
Update the C struct for UICR to the latest revision.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-09-08 15:52:20 -04:00
Sebastian Bøe
180f1f8917 soc: noric: nrf54h20: Fix custom CONFIG_KERNEL_BIN_NAME bug
Fix bug where users were unable to name their binary Bøe when building
for nrf54h20.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-09-08 15:52:20 -04:00
Anas Nashif
5e6e3a6de3 arch: mark z_prep_c as FUNC_NORETURN
z_prep_c does not return, mark it as such consistently across
architectures.  We had some arches do that, others not. This resolves a
few coding guideline violations in arch code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-09-08 15:51:07 -04:00
Anas Nashif
6ad396344d soc: espressif: declare z_cstart
Declare z_cstart as extern as otherwise we will need to pull in
kernel_internal.h.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-09-08 15:51:07 -04:00
Anas Nashif
6b46c826aa arch: init: z_bss_zero -> arch_bss_zero
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-09-08 15:51:07 -04:00
Anas Nashif
53a51b9287 kernel/arch: Move early init/boot code out of init/kernel headers
Cleanup init.c code and move early boot code into arch/ and make it
accessible outside of the boot process/kernel.

All of this code is not related to the 'kernel' and is mostly used
within the architecture boot / setup process.

The way it was done, some soc code was including kernel_internal.h
directly, which shouldn't be done.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-09-08 15:51:07 -04:00
Sebastian Bøe
789f3cea8c soc: nordic: ironside: Update boot report structures and error codes
Restructure the IronSide boot report interface with enhanced error
reporting and boot context information.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-09-08 16:01:46 +02:00
Tomáš Juřena
e4e666b951 soc: st: stm32: stm32c0x: Add stop mode support
Enables low power stop mode for C0.

Code is taken from F4 family, tested on nucleo-c71rb with
samples/basic/blinky.

Power consumption in run mode 3.7 mA, in stop mode ~87 uA.

Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
2025-09-08 09:48:12 +02:00
Ivynya Lu
41a7f95f35 soc: nordic: nrf53: assign pin xl1,xl2 to app core if lfxo disabled
Fixes zephyrproject-rtos/zephyr#92663

Disabled LFXO via devicetree allows pin 0.00 and 0.01 to work correctly
as gpio by assigning it to the app core instead of peripheral. Removed
deprecated Kconfig options so DT is the only config path now.

Signed-off-by: Ivynya Lu <ivy.lu@level.co>
2025-09-05 16:49:38 -04:00
Appana Durga Kedareswara rao
687e081dfc soc: amd: Add initial support for Versal Net SoC APU (Cortex-A78)
Add initial support for the Versal Net SoC APU, which is based on
the Arm Cortex-A78 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.

The versalnet_apu.dtsi file defines peripherals shared across the SoC,
while versalnet_a78.dtsi captures peripherals private to the Cortex-A78
processor. These device trees lay the groundwork for further APU-based
development on the Versal Net platform.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
2025-09-05 16:48:38 -04:00
Sean Kyer
3b60bb91e9 native: cpu_freq: Add CPU freq support to native_sim
Define P-states for native_sim and add mock cpu_freq
driver.

Signed-off-by: Sean Kyer <Sean.Kyer@analog.com>
2025-09-05 07:43:56 +02:00
Jiafei Pan
13268e37b6 soc: imx943: a55: add netc power and clock init in soc.c
Power up NETCMIX and configure netc clock in soc_init().

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-09-05 07:43:28 +02:00
Jiafei Pan
22fe1ec2e3 soc: imx943_a55: enable gic v3 its and LPI interrupts
Added dts node for GIC v3 ITS, enabled LPI interrupts, and enabled
GIC ITS driver on the SoC.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-09-05 07:43:28 +02:00
Alessandro Manganaro
299a189508 soc: st: stm32: stm32wbax pm enhancements
soc power management rework to support power states
removing dependency on ST system clock manager (SCM).

Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
2025-09-04 21:03:19 +02:00
Declan Snyder
10e379c7fb soc: mcx: Add mcx cmc hwinfo binding
Add a stupid binding for doc purposes. Terrible coupling when we have to
configure DT in order to generate documentation properly. At least we
get rid of one of the stupid HAS_MCUX_ kconfigs in the process.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-09-04 08:11:43 +02:00
Benjamin Cabé
0132ea07fb doc: fix spelling errors tree-wide
fix some spelling errors in code comments and Kconfig helps

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-09-03 17:04:13 +02:00
Camille BAUD
abbeab9773 soc: bflb: Add sysmap configuration
Memory region configuration: Configure the flags of each memory
regions present on the device using the mechanism provided by
the xuantie core (chapter 9.2 of E907 manual).
This enables matching more closely the real memory space of
the device than the defaults.

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-09-03 14:58:16 +01:00
Camille BAUD
c146af8e6a soc: bflb: BL61x tmpVal -> tmp
Variable is snakecase when it shouldnt

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-09-03 14:58:16 +01:00
Camille BAUD
b13ec9ab54 soc: bflb: address e24 boot failures
This should fix e24 failing to boot by ensuring
interrupts are disabled at startup

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-09-03 14:56:23 +01:00
Camille BAUD
1d6dd89987 soc: bflb: Remove Extraneous code
Remove unecessary unused code and Kconfig

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-09-03 14:56:23 +01:00
Łukasz Stępnicki
621d793726 soc: nordic: nrf54h: turn off NRFS DVFS service
DVFS is supported with IronSide call. NRFS DVFS
will be not enabled by default.

Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
2025-09-03 13:48:59 +03:00
Ajay Neeli
8231941414 boards: amd: kv260_r5: update ttc0 clock frequency
- Update TTC0 clock frequency to 100MHz to align with the Configurable
Example Designs (CED) for kv260 board as used in Vivado.
- Add support for deriving SYS_CLOCK_HW_CYCLES_PER_SEC from Device Tree

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
2025-09-03 11:03:58 +02:00
Elmo Lan
6a98a11b66 soc : realtek: ec: rts5912: fix waiting time not enough
For the ULPM set, it asks for a 10ms ready time for the module.
Use k_busy_wait instead of k_msleep to ensure we wait enough clock cycles.

Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
2025-09-02 15:54:31 +02:00