Fix devicetree coding style regarding whitespaces through the tree.
This affects code snippets inside documentation, comments, error messages
as to encourage a style that passes CI. Follow-up of #101619
Signed-off-by: Josuah Demangeon <me@josuah.net>
Fix systimer object linking (currently wrong name) for ESP32-C2,
ESP32-C3 and ESP32-H2, to correctly place it in IRAM.
Follows #109434.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Unlike the GIC distributor/redistributor, the GICv3 ITS is accessed
through a base mapped by its own driver via device_map() when the node
is enabled, so it never needs a static MMU entry. The agilex5 ITS node
is disabled and never accessed, making this mapping dead. Remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The GIC register banks are accessed by the interrupt controller driver
through flat physical addresses before any driver can map them via the
device MMIO API, so they must be present in the page tables as soon as
the MMU is enabled. Until now every arm64 SoC had to repeat the same GIC
entries in its own mmu_regions.c to achieve this.
Map all the GIC reg banks in the arch core, generated from devicetree
and guarded by the presence of an arm,gic node, and provide a weak empty
mmu_config so a SoC that only needs the GIC no longer requires an
mmu_regions.c. Drop the now-redundant GIC entries from every arm64 SoC.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Problem:
- When CONFIG_LTO is enabled, the boot ROM fails to recognize the
image because .image_id field in img_header is corrupted.
- LTO optimization causes the const struct img_header contents to
be modified incorrectly, breaking the image header that must be
placed at the beginning of the flash.
Fix:
- Add __attribute__((used)) to img_header to prevent LTO from
optimizing away or modifying the structure contents.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Added support for autanalog PRB for PSE84.
This implementation uses the shared autonomous controller (AC) MFD
with the other autanalog drivers.
The PRB is a programmable reference block inside the autonomous
(aut) analog subsystem. It is controlled using the autonomous
controller (AC), which is a programmable state machine. The AC is
shared across all autonomous analog peripherals including the
SAR, PRB, PTComp, CTB, and CTDAC.
The PRB contains two variable voltage references derived from
either VDDA(1.8V) or VGBR(0.9V). These need to be configured
together and accessed using the AC. A PRB MFD is used to bring
together the two voltage reference configurations. AC MFD then
references the combined PRB MFD configuration, and brings together
all other autanalog peripherals into a single AC setup for the
application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add Power Down mode wakeup handling in soc_early_init_hook.
Check km4_aon_boot_done flag to distinguish between normal boot
and wakeup from Power Down mode, and call appropriate PM exit
sequences.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
ESP32 cache has no per-address invalidate primitive, so
cache_hal_invalidate_addr() aborts. Skip the flash IROM/DROM
invalidate step on ESP32 only.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disambiguate the boot-log segment label on socs where the irom and
drom hardware address ranges overlap (esp32c5, esp32c6, esp32h2,
esp32p4). Match against the linker-provided map vaddrs first so the
correct "IROM" or "DROM" string is printed, falling back to the
range-based macros for any other mapped segment.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
These pin are currently managed by the HAL. However, for the consistency,
this patch enforces their declaration in the Device Tree.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The Zephyr implementation (and more importantly, the version of WiseConnect
SDK used in the HAL) strictly depends on a specific version of the NWP
firmware.
However, the current check prevents the user from running a newer release
of the NWP firmware. Let's relax this test to only check if the patch
number is older than what we expect.
In addition, since we bundle a copy of the NWP firmware with Zephyr (via
west blob), there are fewer risks of mismatch than when we introduced this
restriction.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
WIFI_SILABS_SIWX91X_FEAT_HIDE_PSK_CREDENTIALS impacted the way the NWp
print the log message. However, these logs are not available on production
firmware. So, it does not make sense to expose this parameter.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Defining a Kconfig symbol several times is dangerous. It is better to use
configdefault for the CMSIS related symbols.
Bluetooth configdefault depends on NWP driver. It is more accurate to
depend on the Si91x Bluetooth driver.
Finally, configdefault is supposed to be only used in Kconfig.defconfig
files. So, relocate BT_HCI_ACL_FLOW_CONTROL.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
A flash manager thread is created and allocated to
process Flash Manager Process.
Definition of KConfigs STM32WBA_FLASH_MNGR_THREAD_STACK_SIZE,
and STM32WBA_FLASH_MNGR_THREAD_PRIO to configure the
flash manager thread.
STM32WBA_FLASH_MNGR_THREAD_STACK_SIZE is setting by default
to 768 bytes. This value was chosen empirically since reasonable
to cover generic cases.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Force users to explicitly opt-in to the deprecated platform symbols,
instead of enabling `DEPRECATED` symbols by default for all nRF54, nRF71
and nRF92 builds.
Fixes#109802.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Added autonomous analog CTDAC for PSE84 device.
This implementation uses the autonomous controller (MFD)
that is shared with other autanalog drivers.
The CTDAC stands for Continuous Time DAC. It is a programmable DAC
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
The DAC output can either be software controlled or be driven
through the AC hardware by loading through an internal LUT memory.
AC MFD references the DAC configuration, and brings together all
other autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
The MCXE31x SoC requires ECC-protected SRAM and TCM to be initialised
by a 64-bit master on destructive reset before any 32-bit master access
is allowed. The init routine is currently wired to soc_reset_hook,
which runs after the early portion of z_arm_reset that may already
touch SRAM.
Wire the init routine to soc_early_reset_hook instead, which is the
arch-defined hook that fires before any RAM access is performed by
reset.S. This matches what the S32K3 series does in
soc/nxp/s32/s32k3/s32k3xx_startup.S for the same hardware constraint.
The hook body itself only uses registers (no stack), as required by
the soc_early_reset_hook contract. The previous 'bl SystemInit' tail
call is moved out of this ASM hook into soc_early_init_hook in soc.c,
where the full C environment (.bss zeroed, .data copied) is guaranteed
to be ready. SystemInit comes from the NXP SDK and may touch globals,
so it must run after C startup is complete, not from within the early
reset hook.
Reported in zephyrproject-rtos/zephyr#107699.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Linker script pulls libdrivers__timer.a:esp32c6_sys_timer into
IRAM but the actual driver object is esp32_sys_timer, so the
match fails and the timer code stays in flash. Update the
pattern to esp32_sys_timer.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Handle GAMC register with device memory-mapped input/output management.
As the MMIO is used, remove the MMU configurations for GMAC accordingly.
Signed-off-by: Tony Han <tony.han@microchip.com>
Wi-Fi on PSRAM-enabled builds was failing because the shared multi
heap overlapped relocated .ext_ram.data noinit content. Anchor the
heap on the linker-reserved window, size esp32c5 and esp32s3 ext
segments to the cache window and bump the Wi-Fi SPIRAM heap floor.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The STM32Cube HAL2 uses different hooks for assertion failures.
Attempting to enable HAL assertions on series using HAL2 right now
results in a build failure because we don't provide these hooks.
For example:
west build samples/net/dhcpv4_client/ -b nucleo_c5a3zg
-DCONFIG_ASSERT=y -DCONFIG_USE_STM32_ASSERT=y -p
results in the following messages (shortened for clarity):
[293/298] Linking C executable zephyr/zephyr_pre0.elf
FAILED: zephyr/zephyr_pre0.elf zephyr/zephyr_pre0.map
ld.bfd: in function `HAL_RCC_PSI_GetConfig':
.../stm32c5xx/drivers/hal/stm32c5xx_hal_rcc.c:1596:
undefined reference to `assert_dbg_param_failed'
ld.bfd: in function `HAL_ETH_SetConfig':
.../stm32c5xx/drivers/hal/stm32c5xx_hal_eth.c:1465:
undefined reference to `assert_dbg_state_failed'
Add glue code needed for compatibility with HAL2 and, while at it, also
clean up the HAL1-specific hook.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add initial support for nuvoton numaker m031x SoC series
including basic init and device tree source include.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
ESP32-S2, S3 and C5 select CPU_HAS_DCACHE so CONFIG_DCACHE is
always y on these series. Gating CACHE_MANAGEMENT on ESP_SPIRAM
left CONFIG_DCACHE_LINE_SIZE undefined when PSRAM was disabled,
which broke any driver that reads it under CONFIG_DCACHE such as
the USB device controller buffer macros.
Drop the ESP_SPIRAM condition so CACHE_MANAGEMENT defaults to y
whenever the series is selected, matching the ESP32-P4 defconfig.
The cache line size is a CPU property that exists regardless of
PSRAM, and internal SRAM DMA paths also benefit from coherent
sys_cache_data_* operations.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Added autanalog CTB support for PSE84 device.
This implementation uses the autnonomous controller (MFD)
that is shared with other autanalog drivers.
The CTB stands for Continuous Time Block. It is a set of opamps
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
Each CTB block contains two opamps, which need to be configured
together and accessed using the AC. A CTB MFD is used to bring
together the two opamp configurations. AC MFD then references the
combined CTB MFD configuration, and brings together all other
autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
In AP mode, there is not enough heap memory in NWP for a WPA2 connection's
crypto operations. This issue was reported earlier and was fixed in NWP
by reserving 5kB extra memory in TCP/IP bypass mode. However this was
pushed as a hotfix and the fix was lost in the next release.
The NWP code is frozen now and the workaround to fix this issue is to
enable a feature which reserves ~5kB memory.
Removing this macro enables WPS and reserves an 5k extra memory in NWP.
It does not affect any other functionality (such as Wi-Fi IEs).
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Migrate NXP MCXC, MCXA, MCXN and KE1xZ system PM hooks to the
idle-owned IRQ restore contract.
Select PM_STATE_SET_IRQ_LOCKED for the migrated SoCs. Their pm_state_set()
and pm_state_exit_post_ops() no longer dispatch wake-source IRQs before PM
resume bookkeeping completes.
Remove SoC-side irq_unlock(0) calls. Use the arch PM helpers next to the
low-power instruction in implementations that execute WFI directly.
Keep power_mgmt_soc coverage enabled for the migrated MCXC boards.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Select CPU_HAS_DCACHE on ESP32-S2, S3 and C5 and auto-enable
CACHE_MANAGEMENT in each defconfig when ESP_SPIRAM is selected.
This activates the cache_esp32 driver where it is useful, so
portable sys_cache_data_* calls keep PSRAM and DMA buffers
coherent.
The L1 dcache line size is declared via the cpu@0 devicetree
node so the generic DCACHE_LINE_SIZE Kconfig default picks it
up automatically. SoCs without writeback cache (ESP32, C2, C3,
C6 and H2) are left untouched.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Renamed power states to use runtime-idle
for sleep, and suspend-to-idle for deepsleep
- Added soft-off for hibernate
- Added poweroff support mapping to hibernate
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Added PTComp support to PSE84.
This implementation uses the shared autonomous controller (MFD)
with other autanalog drivers.
The PTComp is a programmable threshold comparator inside the
autonomous (aut) analog subsystem. It is controlled using the
autonomous controller (AC), which is a programmable state machine.
The AC is shared across all autonomous analog peripherals including
the SAR, PRB, PTComp, CTB, and CTDAC.
The PTComp block contains two comparators for edge detection and
with a capability for boolean post-processing. These two comparator
instances need to be configured together and accessed using the AC.
A PTComp MFD is used to bring together the two comparator
configurations. AC MFD then references the combined PTComp MFD
configuration, and brings together all other autanalog peripherals
into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add CPU clock-frequency to the bcm2711 device tree and use it to
derive SYS_CLOCK_HW_CYCLES_PER_SEC instead of relying on a
hard-coded value.
Also enable cache management by default for the BCM2711 SoC.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Following the removal of the internal Haltium and Lumos platform
abstractions in favor of explicit SOC_SERIES_* checks, add
backward-compatibility aliases so out-of-tree code that still
references the old names keeps building during the deprecation
period, with a clear warning pointing to the new names.
All aliases are tagged [DEPRECATED] and slated for removal in a
future release.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
This commit introduces a new clock control driver for NXP MCXW series
microcontrollers, replacing the previous hardcoded clock initialization
in soc.c with a devicetree-based approach.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Add support for CONFIG_PM_CUSTOM_TICKS_HOOK.
Enable CONFIG_PM_CUSTOM_TICKS_HOOK if CONFIG_PM and CONFIG_BT are set.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Edited help text for Kconfig options related to AP-Protect.
NCSDK-38220 and sdk-nrf#28677.
Follow-up to NCSDK-36611 and sdk-nrf#27088.
Signed-off-by: Grzegorz Ferenc <Grzegorz.Ferenc@nordicsemi.no>
Insert an explicit `. = ALIGN(0x10)` at the end of the flash
text region in every Espressif SoC linker script. The flash MMU
maps code in fixed-size segments and image headers record each
segment with a 16-byte-multiple length, so the boundary between
the text region and whatever follows must land on a clean 16-byte
address. Relying on the preceding `. += 16` padding or `ALIGN(4)`
only guaranteed 4-byte alignment, which left the segment size
off-grid on builds where prior input sections happened to end at
an unaligned offset.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Set DROM_SEG_ORG equal to IROM_SEG_ORG and add a NOLOAD dummy
section in drom0_0_seg that advances past the end of .text.
The MMU allocator advances free_head by irom_len + drom_len
assuming the two segments are adjacent. The previous 8MB gap
left the rodata virtual range unreserved, causing 8MB PSRAM
mapping to overrun .rodata.
Place the esp_psram object in IRAM so PSRAM init does not
depend on flash reads while MSPI clock and tuning registers
are transitioning. Split esp_init_psram into chip-init plus
mmu-map steps and invalidate the flash IROM/DROM ranges in
between so the next flash fetch reloads with the final MSPI
settings.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add power management support for MCXE24x SoC series with
four power states defined in device tree (runtime-idle and
three suspend-to-idle substates: STOP, PSTOP1, PSTOP2).
Implement pm_state_set() to handle state transitions using
the SMC (System Mode Controller) for STOP mode configuration.
When CONFIG_XIP=y, the WFI is executed from a __ramfunc so the
core does not fetch instructions from internal program flash
across the low power entry boundary.
Implement pm_state_exit_post_ops() to restore normal operation
after wakeup. No wake-up controller is required to wake the
core from these substates on this part.
Enable HAS_PM capability for the SoC series. Applications that
opt in to PM should also designate lptmr0 as the system timer
via the 'zephyr,system-timer' chosen property and enable the
node, so the LPTMR tickless driver keeps time across
STOP/PSTOPx without needing a SysTick + LPTMR companion-timer
arrangement.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
