\MTL SOF is not compiling when
8d0eb6ce10
(devicetree: remove deprecated DT_CHOSEN_*_LABEL macros)
is applied
Fix - zephyr/toolchain used to be included by
devicetree/zephyr.h. The file has been removed by 8d0eb6ce10
Include is needed for ALWAYS_INLINE macro
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Move regs configuration from previous pinmux.c to soc layer.
This involves the debug interface, configuring the GPIO bank power
and the test clock out pin.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Only include fsl_flexspi_nor_boot when a boot header is present,
as this is the only case where the boot header data will be required.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use spisc_it8xxx2_regs instead of IT83XX_SPI_*** registers declaration
to fix in cros_shi_it8xxx2.c
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.
There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
The `mps2_an521_remote` and `mps2_an521_ns` targets have the same
memory layout for code and ram, meaning that you can't use TF-M
(`mps2_an521_ns`) and the second core (`mps2_an521_remote`) at the
same time.
This commit updates the memory map of the `_ns` build targets as
follows:
- Reduces the code memory region from 1 MB to 512 KB, maintaining the
existing base memory address of `0x0010 0000`
- Maintains the existing 512 KB ram memory at `0x2810 0000`
It updates the `_remote` target as follows:
- Reserves 468 KB code memory at address `0x0038 B000`
- Reserves 512 KB ram memory at address `0x2818 0000`
This ensures that the code region for the `_remote` target doesn't
overlap with the code region used by the single flash image layout
defined upstream in TF-M, which the `_ns` target is based upon.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
When CONFIG_MP_MAX_NUM_CPUS=1, which it does for some tests, we will
get compiler warnings with soc_adsp_halt_cpu(), so only build it
when CONFIG_MP_MAX_NUM_CPUS > 1.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Some SAM0 contains revisions with separated includes for example
SAMC21 and SAMC21N.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
We look at the Intra DSP communications capability register (DFIDCCP)
to determine the number of cores. There might be a better way to
determine the number of cores, but this works for now.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add Kconfig SOC_HAS_RUNTIME_NUM_CPUS symbol that an SoC can
set to specify that it supports determining the number of CPUs
at runtime.
On xtensa add support for SOC_HAS_RUNTIME_NUM_CPUS and expose
soc_num_cpus that the SoC code should set early in boot as the
means to expose the number of cpus.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Basically:
- Name RAMABLE_REGION as "RAM";
- Insert the relocation hooks for gen_relocate_app.py.
Also, to help with "rimage" peculiarities, `fix_elf_addrs.py` changed to
not copy empty sections to output, as this would prevent someone trying
to move all of some section (such as BSS) to a different location and
reuse the platform linker script - which would generate an empty section
anyway.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.
As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.
Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Xtensa is the odd one out by using _data_start/_data_end instead. Using
the Zephyr standard helps avoid ifdefs for common code, like tests.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Fix a bug where an IPC message is sent while the peer/host ack for
the previous message has not yet been processed. There is existing
logic to check 'idr' INTEL_ADSP_IPC_BUSY bit, but this leaves
the following race:
- DSP: msg A sent by DSP to host
- HOST: IRQ, msg A acked, host sets DONE bit -> ADSP_IPC_BUSY cleared
- DSP: msg B sent by DSP to host, IPC_BUSY is clear so proceeding to send
-> e.g. 'devdata->sem' is reset --> BUG!
- DSP: IRQ, msg A done
-> e.g. call to 'sem_give(&devdata->sem)' which is wrong as
the semaphore was just reset in previous step for msg B
Add additional state to track handling of the acks. This allows
to postpone sending message B (in above example), until message A
is fully processed.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
STM32WB Controller supports application to initiate the "PHY Update
Procedure" (BT_USER_PHY_UPDATE) while it doesn't support it to be
automatically triggered on connection establishment (BT_AUTO_PHY_UPDATE).
Default BT_USER_PHY_UPDATE to true, which automatically defaults
BT_AUTO_PHY_UPDATE to false.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update Intel ADSP timer driver to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove setting 'default y' for the timer driver in
Kconfig.defconfig.series as that is now handled in the driver Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Now that IPM drivers are enabled based on devicetree we can
remove any cases of them getting enabled by Kconfig, *defconfig*,
and *.conf files.
We need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x eSPI SAF has significant hardware changes
requiring a new SAF configuration structure. In preparation
for the MEC172x we move the current SAF header out of common
to the MEC1501 subfolder, remove an unused and empty common
header and remove includes of the moved headers from MEC172x.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus(). This is to allow
runtime determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add #ifdef CONFIG_SMP around code that only needs to exist when
SMP is enabled.
Also include ksched.h to get decleration of z_sched_ipi.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Cleanup CMakeLists fixing error message:
...
No SOURCES given to Zephyr library: soc__x86__raptor_lake
...
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
IT8xxx2 uses a relatively slow SPI flash for ROM with a small 4k
I-cache. As a result in large or busy applications, instruction fetch
can be very costly due to I-cache misses. Since exception handling code
is some of the hottest code in most applications, add an option (enabled
by default) causing that code to execute out of RAM in order to improve
performance.
This is very similar to exception section placement on XIP niosii
platforms (which has similar motivation), but can still be disabled by
configuration.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
These functions are small and may be very hot depending on the workload,
so are usually a good choice to execute from RAM.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
The chip I2C driver uses chip_get_pll_freq(), so that function needs to
be built even when the PLL configuration is not changed at boot.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change for loops of the form:
for (i = 0; i < CONFIG_MP_NUM_CPUS; i++)
...
to
unsigned int num_cpus = arch_num_cpus();
for (i = 0; i < num_cpus; i++)
...
We do the call outside of the for loop so that it only happens once,
rather than on every iteration.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Fixes boot failure on CAVS platforms with
CONFIG_NO_OPTIMIZATIONS=y by moving z_soc_mp_asm_entry
into .text linker section to ensure it is copied to
SRAM.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Sometimes IPC message acknowledgement should be done by external
code to provide sufficient timing (example assemble code related
to powering down). Added bool return type to ipc message done handler
that if callback function returns true, IPC API skips writing
IPC message completion bits.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
The restore vector after power gating was configuring the MEMCTL register
incorrectly. This caused an FW crash during the cache prefetch.
Additionally, since lp sram cache issue was fixed, xtensa hal function
can be replace with zephyr equivalent.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
eSPI PUT_IOWR_SHORT protocol can send 1/2/4 bytes of data in a single
transaction. This allows the host to send max 32-bits Port80 code
at one time. This CL sets bits OFS0_SEL~OFS3_SEL in the DPAR1 register
to let the EC hardware put the full Port80 code to DP80BUF FIFO.
It also groups the N-byte code into a single 32-bits variable when
necessary by analyzing the offset field in the DP80BUF register.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Allows applications to use other frequencies than 60 MHz.
For example 48 MHz for USB communication with usbserial driver.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
Continue to phase out MP_NUM_CPUS, change Kconfig to be
MP_MAX_NUM_CPUS and make MP_MAX_NUM_CPUS the main Kconfig symbol.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Include the correct header file. This was uncovered due to
a recent change where zephyr/kernel.h include was removed
from init.h
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The soc.h from the espressif HAL module provides register definitions
like APB_CLK_FREQ, which are required for the Zephyr TWAI driver.
Signed-off-by: Martin Jäger <martin@libre.solar>
Introduce support for Pinctrl driver on NXP S32Z/E SoC's.
The NXP S32 pin controller is a singleton node responsible for
controlling the pin function selection and pin properties, based on the
pin node group approach. The pinmux configuration is encoded in a
32-bit value.
Each S32 SoC implementing Pinctrl must create a `pinctrl_soc.h` header
which define SoC-specific macros to initialize the pinctrl structure.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 devices, specifically for
S32Z27 from S32Z/E family.
NXP S32Z27 processors are composed of two Real-Time Units (RTU)
containing each four ARM Cortex-R52 cores with flexible split/lock
configuration, and dedicated internal SRAM.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
The commit boot code does not call hp_sram_pm_banks() so there is
no need to do an extern declare.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The functions to get memory bank counts are simple enough that
they can be always inlined. This mostly helps with debugging,
especially with NO optimizations, as inlining is being done only
if the inline keyword is specified. This creates a chicken and
egg problem where the SRAM init functions need to call these
before code copying can be done. However, these functions are
not in memory before code copying, resulting in jumping into
memory with random bits.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is a "load" flag associated with segment to be copied
into Xtensa attached memory during manifest parsing. So only
copy those segment if indicated so. There may be some segments
in the struct with NULL destination address. So this is
to avoid memcpy into NULL.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is an assumption in parse_module() during code/data copying
that the memory has already been zero-ed, and hence no need to
clear memory when a BSS segment is encountered. In CAVS ram
initialization code, bbzero() is called. However, in ACE code,
there is no such call. So add them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Now that VMPIDR_EL2 will be initialized in z_arm64_el2_init, the code
that I wrote for initializing VMPIDR_EL2 on fvp_baser_aemv8r can be
removed.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
The `ARCH` init level was added to solve a specific problem, call init
code (SYS_INIT/devices) before `z_cstart` in the `intel_adsp` platform.
The documentation claims it runs before `z_cstart`, but this is only
true if the SoC/arch takes care of calling:
```c
z_sys_init_run_level(_SYS_INIT_LEVEL_ARCH);
```
Which is only true for `intel_adsp` nowadays. So in practice, we now
have a platform specific init level. This patch proposes to do things in
a slightly different way. First, level name is renamed to `EARLY`, to
emphasize it runs in the early stage of the boot process. Then, it is
handled by the Kernel (inside `z_cstart()` before calling
`arch_kernel_init()`). This means that any platform can now use this
level. For `intel_adsp`, there should be no changes, other than
`gcov_static_init()` will be called before (I assume this will allow to
obtain coverage for code called in EARLY?).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
MTL is just one platform and this code is going to be used in multiple
platforms currently under development, so reduce the confusion and move
to a common namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
File still not being removed due to out-of-tree usage. We will drop it
once the external code has stopped referencing it.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Split the defines based on domain and cleanup ace_v1x-regs.h so we can
finally remove it and stop include soc specific headers across the tree.
Future generations of this family will be able to use the same naming
scheme without having to use the version name in the file name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Now that we have shim defined for each platform, no need to support all
platforms within the same struct. This change exposes some bugs where we
were relying on the old structure and calling into unused register space
for example for SRAM initialization on some SoC generations.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup soc.h and move interrupt defines into own headers. Rename some
of the defines for ACE to have a unified namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The DW register block was duplicated into the ACE header while we had
the same thing in the driver. Move everything to the driver as the first
step with further improvements planned on top of this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The file uses architecture specific IRQ calls without including
appropriate headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
sys/util.h is not needed by soc.h, and was causing troubles with
redefinitions of ARRAY_SIZE (from HAL) in CI.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files were using macros defined in sys/util.h without including it,
e.g. for MHZ().
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some SoCs define stuff in soc.h, used in drivers or SoC code. Note that
soc.h is not introduced here as a catch-all header. soc.h optimizations
or removal is out of the scope of this patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files make use of NMI API (NMI_INIT()) without including the
appropriate headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
With the incoming removal of kernel.h/types.h from init.h, lots of files
start to show compile errors because they relied on indirect
definitions, including errno.h.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files make use of CMSIS APIs/definitions without explicitely
including CMSIS headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Do FW communication outside of memory window setup to accomodate for
additional IPC commands and headers.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is not guaranteed to match the physical layout of the memory, so
get them individually based on node label.
For initialization, use bbzero.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some windows might need to be set as writtable, so add a flag read-only
to DTS bindings which is set to true for all windows right now. This can
be set to false where needed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This was all done as part of the soc and called from the soc. Define
this type of console under drivers/console and use it in the SoCs
supporting that via SYS_INIT instead of calling the console code
directly.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of just declaring the memory window register in DTS and have
everything else all over the place (headers, Kconfig, etc.) this change
defines the memory window instances in DTS and uses the device model to
initialize the windows. Code is still part of the SoC, given that we do
not have a driver subsystem suitable for this type of device yet.
Move FW status to own workflow and separate from window setup.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clean up and refactor x86 SoC headers in preparation of adding
new platforms in the future.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
add common mec_gpio.h to allow access to common gpio_regs
structure for both mec15xx and mec17xx, used in pinctrl driver
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This is an AArch64 board. We also add RK3399 SoC support,
as well as a very simple Synopsys 8250dw UART driver.
Signed-off-by: Henri Xavier <datacomos@huawei.com>
The Inter-DSP Communication (IDC) is being used to send
sched IPI to other CPU cores. When a core receives an IDC,
it needs to ACK it by clearing the BUSY bit in TDR, and also
needs to the BUSY bit in TDA to signal done after processing.
These two steps are needed to complete one IDC message.
If we do only one (and not both), the other side will not be
able to send another IDC message as the hardware still thinks
the core is processing the IDC message (and thus will not send
another one). So add the step to clear the BUSY bit in TDA so
we can have multiple sched IPIs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit updates the intel_adsp build script to invoke the
`fix_elf_addrs.py` Python script using the Python executable detected
by the build system.
This ensures that the script is run using the same Python installation
used by the Zephyr build system.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
The platform has support for pinctrl, but it is selecting both pinmux
and pinctrl. Legacy applications requiring pinmux should enable it
manually.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
() The check for whether the CPU is already active before halting
was incorrect. It should only fail if the CPU is not active,
but the CHECKIF() conditional was inverted. So invert it.
() Also need to set the entry in the bookkeeping array to false
once a CPU is considered powered down.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The conditionals to check if the CPA bit is already set or cleared
are incorrect. This results in the code always asserting. So fix
those.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add options about Internal RC(IRC) oscillator.
- GD32_HAS_IRC_32K/40K indicates IRC types.
- GD32_LOW_SPEED_IRC_FREQUENCY is the numeric value of frequency
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Linker scripts contains a `.last_section` section that is placed in rom
region as NOLOAD for the purpose of retrieve the actual number of bytes
contained in the image. See d85efe0b10
However, a previous section may cause the location counter to be
incremented for alignment purposes. This can result in the size of the
image to be 0x10FA but location counter to be 0x1100 because it has been
aligned for next section placement.
Therefore, two new Kconfig settings are introduced.
Those settings request the linker to will write a pattern in
`.last_section`. Together with removing NOLOAD and writing a patten to
the section then we ensure that data is written after alignment of
location counter, and thereby forces the image size to be in sync with
the location counter.
The default pattern used will be 0xE015 (end of last section).
Some systems may fill up the flash completely, or simply write data at
the end of the flash, which in both cases can result in overflow.
Therefore, the new settings can be disabled.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Allow building for nRF non-secure and TF-M enabled without having the
platform partition enabled.
In this configuration the soc_secure functions have no valid
implementation, leave it as a compilation error if the application
includes the functions.
Add missing dependency on soc_secure functions being available for
SOC_HFXO_CAP_INTERNAL configuration.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Make Kconfig produce an error when GPIOs cannot be forwarded in the
current configuration instead of silently excluding the forwarding.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
This will trigger link commit immediately after start
to fix hda start flow.
Applies to link out only.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
On ACE, there is another layer of interrupt masking where
this masks, in addition to the DesignWare controllers.
So we need to un-mask during IPC init or else we are not
going to get any host IPCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Zephyr encodes multi-level interrupts in a certain way, and
the driver is not utilizing the encoding correctly. So fix
it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit removes the `k_mem_pool` section for the memory pool API,
which was removed in the v2.5.0 release.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
console can't handle the amount of data coming from many tests, so
introduce a delay beween testcases.
Use ZTEST_TEST_DELAY_MS to delay test execution.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
...Z_THREAD_STACK_BUFFER.
This is currently a symbolic change as Z_THREAD_STACK_BUFFER
is simply an alias to Z_KERNEL_STACK_BUFFER without userspace,
and Xtensa does not support userspace at the moment.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
...Z_THREAD_STACK_BUFFER.
This is currently a symbolic change as Z_THREAD_STACK_BUFFER
is simply an alias to Z_KERNEL_STACK_BUFFER without userspace,
and Xtensa does not support userspace at the moment.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In commit c75e6cfcb9
("soc: intel_adsp_ace1x: Added IPC/IDC implementation")
definition for INTEL_ADSP_IPC_DONE was modified for ace1x platforms.
This change was not correct as the new definition was also used to
program the IDA register.
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
1) HDA logging seems to be using some padding like '\x00'. Such
string can print well on a terminal but corrupt the string match.
And this can cause false failure if RunID matching is affected.
Remove such padding before checking RunID.
An affected RunID example:
'7aa9ba3c6db12\x00\...\x00\x00\x00\x00d0c7fcf382a4af40ec6'
Expected:
'7aa9ba3c6db12d0c7fcf382a4af40ec6'
2) Use non-displayable chars for live connection check. Otherwise
the log output will have subtle garbage like extra spaces which
locate randomly.
This solution comes from the PR #50071, the author is smrtos.
Signed-off-by: Ming Shao <ming.shao@intel.com>
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Remove the remote service logic in the FW loader, now
the FW loader is a pure FW loader as it used to be.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Spilt the cavs server and FW loader, to make the cavstool.py
a pure FW loader and runner as it used to be. The reasons is
try to keep the FW loader won't be affected by the client-
server-based HW service as possible, and more easy to debug.
After splitting them, the service program spawns another
process to run the FW loader. The advantage is no matter when
the FW loader is stuck, the service can detect and stop it,
then continue to next test.
Fixes#47652.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Copy cavstool.py to remote-fw-service.py in order to track changes
for following splitting work of cavstool.py.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
If the target is built without CONFIG_PM this stack is not
used and does not need to be defined.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The tool has caused some hard to detect failures when used
concurrently with the SOF Linux driver to observe logs. This
has been rootcaused to the code to handle and send IPC messages
that has been active even in logs-only mode. In vast majority
of cases, the SOF kernel driver is faster to act and handles
the IPC interrupts. But occasionally the cavstool.py timing was
just right and it managed to ack a message before Linux driver.
Fix the problem by not handling IPC messages when the tool
is run in logs-only mode.
Reported-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Interrupt vectors level 5 and 6 are not available in ACE. Just remove
them from the linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In ace15_mtpm the debug exception vector address is mapped to INTLEVEL4
and not INTLEVEL 6. This can be checked in the core-isa header:
"""
define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
"""
in
modules/hal/xtensa/zephyr/soc/intel_ace15_mtpm/xtensa/config/core-isa.h
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In normal operation the clock for peripheral devices is derived from
the PLL clock.
During sleep, the xmc4xxx can switch its system clock source (f_sys)
from the PLL clock to an f_ofi clock. Switching to the f_ofi clock
is the default behaviour which breaks UART comms.
Use the PLL clock source during sleep instead to fix the issue.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
1. Add USB_STACK_USE_DEDICATED_RAM=1 define that is
used by the SDK USB driver
2. Delete unused "config USB_DEDICATED_MEMORY"
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
