The PSE84 static MPU region table is shared between the Cortex-M33 and
Cortex-M55 cores, but several of the regions only belong to one core.
Instantiating every region on both cores wastes scarce hardware MPU
slots, and on the CM33 (which only exposes 8 data regions) it leaves no
room for memory-domain partitions: the default domain can no longer
allocate its libc/malloc partitions and initialization fails with
-ENOSPC, which breaks the userspace / memory-protection tests at boot.
Scope each core-specific region to the core that actually owns it:
- m55_allocatable_shared is a CM55-only nocache window; it is unused on
the CM33.
- m33s_code / m33_code hold the CM33 secure / non-secure code images.
The CM55 never executes from them. m33s_code is the secure code image,
so it is gated on the secure CM33 (CPU_CORTEX_M33 &&
TRUSTED_EXECUTION_SECURE); the node is also visible to a non-secure
CM33 build, so gating on !CPU_CORTEX_M55 alone would still map it on
the non-secure CM33. m33_code is the non-secure image and is gated on
the non-secure CM33 for the same reason.
- itcm / dtcm are the CM55 tightly-coupled memories; the CM33 cores
never access them.
The CM33 allocatable shared window (m33_allocatable_shared) is kept on
both cores since it backs shared-memory consumers and is not specific to
a single core.
With this change the secure CM33 static set is reduced to {FLASH, SRAM,
SHARED_MEMORY_33, M33S_CODE}, restoring the partition slots the default
memory domain needs, while the CM55 keeps only the windows it uses.
Assisted-by: GitHub Copilot
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Add devicetree pinctrl binding header for the NXP LPC84x
series, defining SWM function indices, port pin identifiers,
and helper macros for pinmux encoding.
Also add the LPC84x SoC-specific pinctrl header implementing
the pin descriptor type and configuration helpers used by
the generic pinctrl subsystem.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
Add SoC support for the NXP LPC84x (LPC845) series microcontroller.
This commit introduces:
- SoC device tree binding (nxp_lpc845.dtsi & nxp_lpc84x.dtsi)
- Kconfig configuration for LPC84x series
- Minimal SoC initialization (soc.c/soc.h)
- Build system integration (CMakeLists.txt)
Signed-off-by: Vignesh Pandian <vignesh@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
Keep the normal MCXE31x default on Cortex-M SysTick, but make the
SysTick driver default off when an MCUX timer driver is explicitly
selected as the system timer.
This preserves the existing board default while allowing test or board
overlays to opt in to LPTMR, OS timer, or STM without ending up with
two system timer drivers.
Validated by building zephyr/samples/hello_world for frdm_mcxe31b and
checking CONFIG_CORTEX_M_SYSTICK=y in the default configuration.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The main goal of this change is being able to use counter_gecko_rtcc.c and
leuart_gecko.c on boards without an LFXO. This is the case for tyzs3.
The main changes are in soc/silabs/common, the rest is just to migrate all
of the boards.
This uses the device tree for clock-initialization only. I did not
implement a clock_control driver, because I don't see a need for that. The
drivers use CMU_ClockEnable, which abstracts away SoC differences already.
The config SOC_GECKO_HAS_HFRCO_FREQRANGE was removed, because:
- This can be detected via macros provided by gecko_sdk.
- There is an alternative to that API which wasn't implemented previously,
but is now (cmuHFRCOBand_*).
I don't own any of the boards except for tuya tyzs3, but did my best to
avoid mistakes. That being said, I found several issues, which were present
in some of the boards already:
- sltb004a: This board has a 38.4MHz HFXO crystal, but it was configured to
40MHz. I fixed that.
- tomu: This board uses HFRCO as it's HF clock, even though the SoC does
not support SOC_GECKO_HAS_HFRCO_FREQRANGE. So it was probably running at
the initial 14MHz instead.
- Many boards enabled leuart and rtcc (counter) peripherals, which need(ed)
LFXO, without ever enabling LFXO. These peripherals were probably not
working before this change.
Noteworthy finds:
- slwrb4321a: This board uses HFRCO as it's HF clock, but has a board.c
where it enables HFXO to use it as the RMII reference clock. I'm not sure
if it's okay to do that without calling CMU_HFXOInit first. I did not
modify that code to not change behavior that I don't understand.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
When TRUSTED_EXECUTION_NONSECURE is false, configure IPCT for
secure access, since peripheral is ns by default.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, I/DCACHE_LINE_SIZE are redefined and set to the given
default value even if the dependency D/ICACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
MCXE31B standby powers down the run domain and wakes through a
functional reset. Expose that mode through sys_poweroff instead
of a resumable PM state.
Add the SoC z_sys_poweroff implementation, select HAS_POWEROFF,
and build the file when CONFIG_POWEROFF is enabled. The entry
sequence enables SIRC standby operation, configures WKPU source 1,
prepares the PMC regulator state with HAL helpers, and enters
MC_ME standby.
Restore the standby IO latch from the MCXE31X late init hook when
the previous mode was standby. Keeping both entry and restoration
in the SoC layer avoids board-specific follow-up requirements for
future MCXE31X boards that enable CONFIG_POWEROFF.
Validated with west build on frdm_mcxe31b/mcxe31b. Hardware
validation showed Cold boot followed by Woke from standby.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Flash and PSRAM line modes are independent, so do not force octal
flash when octal PSRAM is selected. Most octal-PSRAM modules pair
octal PSRAM with quad flash, and the implicit default produced an
OPI flash image that fails to boot on those boards. Make octal flash
an explicit opt-in and add a build-only sample variant to keep the
octal flash path under CI coverage.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The Cortex-R cores on the J721e don't have a fixed frequency and are
instead running at the frequency of the external oscillator. The retrieval
logic has been moved from boards using their _defconfig files to instead
needing to define a "fixed-clock" devicetree node with the nodelabel
"onboard_osc" whose frequency is then retrieved in the general J721e SoC
series defconfig
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
In the J721e and J722s Kconfig.soc fiels there was a mistake that resulted
in both series being wrongfully selected instead of only the own one. This
has been fixed by removing the wrong Kconfig lines.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Select CLOCK_CONTROL and CLOCK_CONTROL_FIXED_RATE_CLOCK for the
VersalNet APU so that the fixed-clock reference used by the
ADMA driver is available.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Select CLOCK_CONTROL and CLOCK_CONTROL_FIXED_RATE_CLOCK for the
Versal Gen 2 APU so that the fixed-clock reference used by the
ADMA driver is available.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Select CLOCK_CONTROL and CLOCK_CONTROL_FIXED_RATE_CLOCK to meet the
Xilinx ADMA driver dependencies for proper clock management.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Select CLOCK_CONTROL and CLOCK_CONTROL_FIXED_RATE_CLOCK to meet
the Xilinx ADMA driver dependencies for proper clock management.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
While most of the XMClib was enabled for all xmc4xxx parts, ethercat was
completely ommitted. Enable it for the xmc4500 and xmc4800, the two
variants that support ethercat.
Signed-off-by: Karl Palsson <karl.palsson@marel.com>
This adds the XMC4800 BGA196 in 1M/200k and 2M/352k flash/ram variants.
Interrupt controller is untouched at present, the existing XMC4700 and
XMC4800 share a reference manual, and are identical in this regard.
Primary difference to the existing XMC4xxx in the smaller packages is the
addition of extra gpio ports 7, 8 and 9.
Pin control file is added, with basic usic and can pins only. Ports
7/8/9 are mostly for ethercat, but that is out of scope at this point.
Tested with private boards using leds on port 9.
Signed-off-by: Karl Palsson <karl.palsson@marel.com>
Update existing XMC4xxx kconfig to use device tree for clock frequency
instead of hardcoding numbers.
Signed-off-by: Karl Palsson <karl.palsson@marel.com>
Add WWDT (Windowed WatchDog Timer) support for all LPC55Sxx variants
(LPC55S06/S16/S28/S36/S69):
DTS / board changes:
- Add wwdt0 node (compatible = "nxp,lpc-wwdt", reg = 0xc000) and
watchdog0 alias to nxp_lpc55S0x/S1x/S3x_common.dtsi
- Enable wwdt0 and add watchdog to supported features on
lpcxpresso55s06, lpcxpresso55s16, lpcxpresso55s36 boards
SoC / clock:
- soc.c: call CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 1U, true) when
wwdt0 is enabled, alongside the existing FRO1MHz enable
Driver hardening (per hakehuang review):
- Add `bool started` flag to mcux_wwdt_data to track post-setup state
- Set started=true in mcux_wwdt_setup(), clear in mcux_wwdt_disable()
and PM_DEVICE_ACTION_TURN_OFF
- Guard mcux_wwdt_isr() with early return when !started, preventing
spurious callbacks from warm-reset stale WWDT status on LPC55S36
- Clear WWDT status flags + NVIC pending bit before irq_enable() in
the IRQ init macro
Tests:
- Add per-board .conf files for wdt_basic_api; lpcxpresso55s06/s16
use SRAMX noinit section to survive TrustZone NS Boot ROM clears;
all boards enable WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG=10
- Update testcase.yaml filter to allow SOC_SERIES_LPC55XXX and
exclude lpcxpresso55s69 NS variant
Tested with tests/drivers/watchdog/wdt_basic_api on lpcxpresso55s36:
SUITE PASS 100% [wdt_basic_test_suite]: pass=1, fail=0, skip=0
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Add single-core and SMP RISC-V AIA APLIC+IMSIC board variants as
nested variants of the qemu_virt_riscv32 SoC, mirroring the
qemu_riscv64 'smode' variant precedent.
The APLIC+IMSIC variants:
qemu_riscv32/qemu_virt_riscv32/aia-imsic
qemu_riscv32/qemu_virt_riscv32/aia-imsic/smp
These variants select a common APLIC topology include and add the IMSIC
nodes and properties needed for MSI delivery. They override the per-cpu
riscv,isa-extensions list to advertise smcsrind, which the RISC-V
indirect-CSR (Smcsrind) extension uses to access AIA external-interrupt
CSRs.
The board Kconfig selects RISCV_HAS_AIA on the APLIC+IMSIC variants,
which flips the SoC-level PLIC default off (see the prior commit). The
QEMU command line gates -machine virt,aia=aplic-imsic on the same flag.
The bare qemu_riscv32 identifier is preserved unchanged so existing
downstream platform_allow entries keep resolving.
The APLIC+IMSIC variant yamls intentionally do not set
testing.default=true: interrupt-driven UART through APLIC+IMSIC is not
yet routed for the generic shell/perf/pytest samples, so leaving them as
default would schedule those samples onto a target where they cannot
reach the shell prompt. Tests that explicitly cover the AIA path opt in
via platform_allow / integration_platforms.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Assisted-by: Codex:GPT-5.5
Assisted-by: Claude:Fable-5
The qemu_virt_riscv32 SoC unconditionally selected RISCV_HAS_PLIC, which
made it impossible to introduce a board variant that uses the AIA
APLIC+IMSIC controllers instead of PLIC.
Move the PLIC enable into a defconfig default keyed on !RISCV_HAS_AIA
so non-AIA builds continue to get PLIC enabled while AIA board variants
can simply select RISCV_HAS_AIA and the default flips off.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Assisted-by: Codex:GPT-5.5
Add and modify nodes to feature the new SF controller
Update boards to use the new controller,
significantly increase performance for a lot of them
Allow effectively truly representing the flash,
Allow setting the flash offset via ranges
use ranges properly
Signed-off-by: Camille BAUD <mail@massdriver.space>
Handle necessary code relocation better,
clearly delimiting what is required and what is not
Also group RAM together
Signed-off-by: Camille BAUD <mail@massdriver.space>
With the xtensa_mpu_mem_type_ranges[] array, the SoC or board
should be the one dictating memory types of various memory
regions. There is no need for this kconfig to be there and
we can use the defaults for the architecture.
Note that the previous P_NA_U_NA access rights are replaced
with the default one, as it should reflect the background map
where it is be used.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move all BUILD_OUTPUT_UF2_FAMILY_ID defaults for STM32 series from
the top-level Kconfig.zephyr into the respective per-series
Kconfig.defconfig files in the ST SoC layer.
Covers: STM32F0, F1, F2, F3, F4, F7, G0, G4, H7, L0, L1, L4, L5,
and WBX series. Per-SoC variants (STM32F407XE, F407XG, F103XE) are
handled with conditions in the series-level defconfig.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the BUILD_OUTPUT_UF2_FAMILY_ID defaults for SOC_SERIES_SAMD21
and SOC_SERIES_SAMD51 from the top-level Kconfig.zephyr into the
Atmel SAM0 SoC layer Kconfig.defconfig files.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the BUILD_OUTPUT_UF2_FAMILY_ID defaults for SOC_SERIES_RP2040
and SOC_SERIES_RP2350 from the top-level Kconfig.zephyr into the
Raspberry Pi SoC layer Kconfig.defconfig files.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the BUILD_OUTPUT_UF2_FAMILY_ID defaults for SOC_SERIES_IMXRT10XX,
SOC_SERIES_IMXRT11XX and SOC_SERIES_LPC55XXX from the top-level
Kconfig.zephyr into the NXP SoC layer Kconfig.defconfig files.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the BUILD_OUTPUT_UF2_FAMILY_ID default for the BL70X SoC series
from the top-level Kconfig.zephyr into the SoC layer where it belongs.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the BUILD_OUTPUT_UF2_FAMILY_ID defaults for SOC_NRF52833_QIAA
and SOC_NRF52840_QIAA from the top-level Kconfig.zephyr into their
respective per-SoC Kconfig.defconfig files in the SoC layer.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the BUILD_OUTPUT_UF2_FAMILY_ID default for the ESP32 SoC series
from the top-level Kconfig.zephyr into the SoC layer where it belongs.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
CONFIG_LINKER_USE_PINNED_SECTION is the second half of the selective
kernel-pinning model removed in issue #108773. With the kernel image
now always resident at boot (previous commit), the __pinned_*
attribute family is a no-op: every page they would have segregated is
already pinned by z_mem_manage_init()'s whole-image loop, so the
tagging contract neither adds safety nor remains maintainable.
Drop it.
Mechanical removals:
* All ~219 in-tree uses of __pinned_text, __pinned_rodata,
__pinned_data, __pinned_bss, __pinned_noinit, and __pinned_func
across arch/x86, drivers/interrupt_controller, drivers/timer,
arch/common, kernel, lib/libc, subsys/portability/posix, tests, and
the syscall code generator (scripts/build/gen_syscalls.py).
* The assembly aliases PINNED_TEXT/RODATA/DATA/BSS/NOINIT used in
arch/x86/core/ia32/*.S and drivers/interrupt_controller/
intc_loapic_spurious.S become plain TEXT/RODATA/DATA/BSS/NOINIT.
* K_KERNEL_PINNED_STACK_DEFINE, K_KERNEL_PINNED_STACK_ARRAY_DEFINE,
K_KERNEL_PINNED_STACK_ARRAY_DECLARE, K_THREAD_PINNED_STACK_DEFINE,
and K_THREAD_PINNED_STACK_ARRAY_DEFINE are removed. The few
in-tree callers (kernel/init.c, arch/arm/core/cortex_a_r/smp.c,
arch/arm64/core/fatal.c, arch/rx/core/prep_c.c,
arch/x86/core/prep_c.c, kernel/include/kernel_internal.h,
tests/bluetooth/hci_uart_async) move to the corresponding
non-pinned macros.
Machinery removals:
* Kconfig.zephyr drops CONFIG_LINKER_USE_PINNED_SECTION.
qemu_x86_tiny and qemu_x86_atom_virt drop their =y overrides.
* include/zephyr/linker/section_tags.h drops the __pinned_* macro
definitions (both arms). __isr collapses to an empty macro since
its only purpose was to alias __pinned_func.
* include/zephyr/linker/sections.h drops PINNED_TEXT_SECTION_NAME,
PINNED_BSS_SECTION_NAME, etc. and the bare PINNED_TEXT/RODATA/etc.
forwarders, plus the _APP_SMEM_PINNED_SECTION_NAME constant.
* include/zephyr/linker/linker-defs.h drops the lnkr_pinned_*
externs, the _app_smem_pinned_* externs, and the lnkr_is_pinned()
/ lnkr_is_region_pinned() inline helpers.
* include/zephyr/linker/utils.h drops the lnkr_pinned_rodata branch
in linker_is_in_rodata().
* include/zephyr/linker/app_smem_pinned{,_aligned,_unaligned}.ld
are deleted; cmake/linker/ld/target_configure.cmake stops
configuring them.
* boards/qemu/x86/qemu_x86_tiny.ld and
include/zephyr/arch/x86/ia32/linker.ld drop their pinned-section
blocks and the now-redundant #ifndef CONFIG_LINKER_USE_PINNED_SECTION
conditionals throughout the body. The
LIB_KERNEL_IN_SECT / LIB_ARCH_X86_IN_SECT / LIB_ZEPHYR_IN_SECT /
LIB_C_IN_SECT / LIB_DRIVERS_IN_SECT / LIB_SUBSYS_LOGGING_IN_SECT /
LIB_ZEPHYR_OBJECT_FILE_IN_SECT / ZEPHYR_KERNEL_FUNCS_IN_SECT macros
in qemu_x86_tiny.ld are deleted; they existed only to feed the
pinned text/rodata/data/bss/noinit sections.
* kernel/mmu.c drops the mark_linker_section_pinned(lnkr_pinned_start,
...) call. The mark_linker_section_pinned() helper survives but is
now gated only on CONFIG_LINKER_USE_BOOT_SECTION.
* arch/common/init.c and include/zephyr/arch/common/init.h drop
arch_bss_zero_pinned(); arch/x86/core/ia32/crt0.S drops the call
to it.
* arch/x86/core/userspace.c drops the eager k_mem_page_in() of the
thread's privileged stack on user-mode entry. With the kernel
image fully resident the stack is already mapped.
* arch/x86/gen_mmu.py drops map_region("lnkr_pinned") and the
set_region_perms() calls for lnkr_pinned_text / lnkr_pinned_rodata.
* CMakeLists.txt drops the LINKER_USE_PINNED_SECTION block that
generated APP_SMEM_PINNED_* variables and the
pinned_partitions target property feeding gen_app_partitions.py.
cmake/modules/extensions.cmake removes the PINNED_RODATA /
PINNED_RAM_SECTIONS / PINNED_DATA_SECTIONS zephyr_linker_sources()
location keywords and their snippet files.
scripts/build/gen_app_partitions.py drops --pinoutput /
--pinpartitions arguments and the pinned-output branch.
subsys/testsuite/coverage/CMakeLists.txt drops its
CONFIG_DEMAND_PAGING-conditional fork.
* scripts/build/gen_kobject_list.py drops the
app_smem_pinned_start / _end fallback for kobject placement
validation.
* tests/arch/x86/pagetables and tests/kernel/mem_protect/userspace
drop their lnkr_pinned_text / lnkr_pinned_rodata branches.
* include/zephyr/arch/x86/ia32/arch.h folds IRQSTUBS_TEXT_SECTION
to the unconditional ".text.irqstubs" form.
* tests/subsys/llext/src/syscalls_ext.c drops a stale comment about
syscalls landing in .pinned_text.
Targeted retentions:
* arch/x86/core/bootargs.c keeps multiboot_cmdline and efi_bootargs
in .noinit (was __pinned_noinit, which decayed to __noinit when
LINKER_USE_PINNED_SECTION was unset). The multiboot and zefi loader
paths write these buffers before Zephyr's BSS-zero step, so
zeroing them at boot loses the cmdline.
* arch/x86/core/ia32/fatal.c keeps _df_esf and _df_stack in .noinit.
They are scratch space written by the double-fault handler and have
no zero-init requirement; keeping them in .noinit also preserves
the historical post-noinit alignment that gen_mmu.py relies on
(z_mapped_size is computed before CMake-injected iterable sections
are appended to the linker script, so the post-noinit page padding
is what keeps those sections within the mapped region).
* include/zephyr/arch/x86/ia32/syscall.h and
include/zephyr/arch/x86/arch.h wrap the per-arch
arch_syscall_invoke* / arch_is_user_context / arch_k_cycle_get_*
implementations in @cond INTERNAL_HIDDEN. The public Doxygen
contract lives on the prototypes in
include/zephyr/arch/arch_interface.h; the per-arch implementations
are internal. Without this, removing the __pinned_func attribute
exposes the implementations to the doxygen-coverage delta check
as 10 newly-undocumented APIs.
Documentation updates are deferred to a separate commit.
Issue: #108773
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Replace the raw APM register writes with the apm_ll helpers when
clearing the access-path filters on c5, c6 and h2. On c5 also put both
cores in TEE mode so LP-core accesses to the PMU and LP_AON window are
granted, which the LP->HP wakeup path relies on. Drop the redundant
pmu_init() and stall/reset tweaks from the c5 lp-core loader now that
hardware_init() covers them.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Cache-disabling routines and any code reachable while the flash cache
is off must execute from internal RAM. Move the affected sections into
iram across all espressif socs so they remain valid when the cache is
suspended.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Updated soc_common_irq to use mieh/miph and sieh/siph
registers when handling interrupts in AIA mode.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Add LVGL config valid for all STM32 SoCs as well as
configs necessary to properly use the DMA2D accelerator.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The nocache window scheme captured _nocache_window_end_noncached from a
trailing (DSECT) marker section placed after the .nocache* sections. When
those sections are empty (no symbols land in .nocache*, e.g. the amp_blinky
and amp_mbox samples), nothing pins the location counter forward and the
marker's '.' collapses back to the nocache region origin. The resulting
zero offset placed .bss on top of .rodata, producing non-monotonic LMAs
that ld 2.43.1 rejects under --fatal-warnings, breaking the HiFi4 remote
image link for both samples.
Derive _nocache_window_end_noncached directly from _nocache_ram_end, which
is captured inside the real _NOCACHE_SECTION_NAME output section and is
therefore correct even when the section is empty, then align it to a cache
line to preserve the original intent. This keeps the non-empty case
unchanged while fixing the empty case.
Fixes: b5060050b9 ("soc: mimxrt685s/hifi4: Add nocache memory region")
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The SiWx91x SoC features an external AHB instruction cache for the QSPI
flash. It has no data cache.
There is no dedicated hardware invalidate command. Invalidation is
performed by toggling the clock gate (disable then re-enable), which
implicitly clears all cached lines. An ISB barrier follows to flush the
Cortex-M4 instruction pipeline.
The driver selects EXTERNAL_CACHE (not ARCH_CACHE) because the siwx91x
Cortex-M4 core does not define __ICACHE_PRESENT in the CMSIS device
header, so the ARM architecture cache implementation (SCB_EnableICache)
cannot be used.
Note this commit has not functional impact. Instruction cache was already
automatically start by the hal.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
DATA_NOCACHE_SIZE used the nocache region address instead of its size,
which broke linker section placement for the HiFi4 remote image and
caused amp_blinky and amp_mbox builds to fail on mimxrt685_evk.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
- add clocks and resets to MCXA CRC nodes.
- crc_nxp: deassert in init if a dt reset is given.
On MCXA SoCs the CRC peripheral boots held in reset, so enabling its
clock is not enough. Deassert the reset during driver init.
- nxp,crc.yaml: include reset-device.yaml for the resets property.
- mcxa Kconfig.defconfig: enable CONFIG_RESET
when MRCC reset is present.
- clock_control_mcux_syscon: enable the CRC clock gate.
- mcxa344: fix reset controller compatible to nxp,mrcc-reset.
Tested on frdm_mcxa344, frdm_mcxa156, frdm_mcxa266.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
These drivers were used by Series 2 SoCs before they were migrated from
gecko_sdk to simplicity_sdk. Currently, Series 2 SoCs don't use them
anymore. In fact, their Kconfig dependencies don't even allow using them
for simplicity_sdk based SoCs.
Removing the leftovers simplifies the code and is a preparation for larger
changes in soc.c.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Wrap the ambiq_dma_buff section address expression in
parentheses so the generated linker script is accepted
by ld.lld.
Without the extra parentheses, the expanded
SECTION_PROLOGUE output produces invalid section
address syntax for LLVM's linker.
Assisted-by: GitHub Copilot:GPT-5.4 [apply_patch] [run_in_terminal]
Signed-off-by: Evan Chen <bugena123@gmail.com>
On MCXW23 the OS event timer is reserved as the low-power companion
to SysTick and could not be used as the kernel system timer:
selecting CONFIG_MCUX_OS_TIMER left CORTEX_M_SYSTICK enabled, which
fails to link (duplicate sys_clock_* symbols), and no OS-timer clock
rate was defined for it.
Disable CORTEX_M_SYSTICK by default when MCUX_OS_TIMER is selected
(as already done for MCUX_LPTMR_TIMER) so only one system timer is
active, and define the OS timer clock rate. The MCXW23 OS event
timer is clocked from the 32.768 kHz RTC oscillator: PMC
OSTIMERCLKSEL resets to 32.768 kHz and is left at reset, and the
HAL only enables (never reselects) the clock. The rate is taken from
a clk_32k fixed-clock devicetree node rather than a hardcoded Kconfig
literal: SYS_CLOCK_HW_CYCLES_PER_SEC = 32768 and
SYS_CLOCK_TICKS_PER_SEC = 1024 (exactly 32 cycles per tick), unlike
other NXP parts where the OS timer runs at 1 MHz.
Selecting OSTIMER trades timing precision (~1 ms tick, ~30 us
resolution) for low-power always-on operation, so SysTick stays the
default where fine-grained timing is needed.
The default SysTick configuration is unchanged: both defaults are
gated on MCUX_OS_TIMER, which is off by default. A before/after
defconfig diff on frdm_mcxw23 is byte-identical (OSTIMER resolves to
HZ=32768/TICKS=1024, SysTick to HZ=32000000/TICKS=10000).
Link: MCXW23 RM section 45.4.11.2.24 (PMC OS timer control register)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
