This change removes underscore charaters from the PSE84 memory region
names. The zephyr_code_relocate CMake function uses underscore
characters as a delimiter for different properties in the target
region, so it is problematic to have underscores in the base name of
the memory region.
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
This API was never intended to be "public" in the sense now documented
in the Glossary, as said in 559c72d7a6:
"Introduce public functions for GPIO pins configuration [...] in
stm32 drivers & routines such gpio_stm32 & poweroff."
Remove the header from the public API directory and move the definitions
to a private header in SoC-specific includes. Update all previous users
of the header (which are as expected only those documented in the commit
message quoted above: gpio_stm32 and SoC poweroff.c).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
UNUSED() is provided by the HAL so it shouldn't be used from Zephyr.
Replace its usage in the STM32 Wakeup Pins driver with the standard
__maybe_unused annotation.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Group all I/O cell-related options in a menu by using menuconfig on
option `STM32_IOCELL`. While at it, also fix the driver configuration
options which were not gated by `STM32_IOCELL` and could thus leak.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Set NUM_IRQS to 32 for MCXL25x CM0+ targets. The CM0+ IRQ table uses
external IRQs 0 through 31, while 161 is the CM33 interrupt range.
Signed-off-by: Samuel Slesar <samuel.slesar@nxp.com>
Commit 0e49186c8c ("include: zephyr: arch: Rename header file guard
macros for Common") renamed the include guard in
include/zephyr/arch/xtensa/gdbstub.h from
ZEPHYR_INCLUDE_ARCH_XTENSA_GDBSTUB_SYS_H_ to
ZEPHYR_INCLUDE_ARCH_XTENSA_GDBSTUB_H_, but did not update the sentinel
check in the intel_adsp SoC gdbstub header.
As a result, when CONFIG_GDBSTUB=y the SoC header still tests the old
macro name, which is never defined, and the build fails with:
#error "Must be included after arch/xtensa/gdbstub.h"
Update the guard check to the current macro name so the SoC header
matches arch/xtensa/gdbstub.h again.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adds SoC support for SHAKTI Ganga, a 64-bit
RISCV SoC from SHAKTI processor initiative at
RISE Lab, IIT Madras. Ganga is commonly ran as
soft core on FPGA boards.
This commit adds SoC family Kconfig and
the base devicetree.
Signed-off-by: Vedant Malkar <vedantitsme@gmail.com>
arch/xtensa/core/irq_manage.c still defines the dynamic IRQ connect
routine under its pre-2019 z_arch_ name, which nothing references
since the z_arch_* to arch_* interface rename. The __weak
arch_irq_connect_dynamic() fallback in arch/common/dynamic_isr.c
silently took over, so the multi-level variant that routes to
z_soc_irq_connect_dynamic() never runs, and the only implementation
of that SoC hook (intel_adsp cavs) has had no caller ever since.
The common weak fallback is functionally equivalent on cavs: the
cavs intc driver registers IRQ_PARENT_ENTRY_DEFINE and
CAVS_ISR_TBL_OFFSET defaults to 2ND_LVL_ISR_TBL_OFFSET, so the
generic z_get_sw_isr_table_idx() computes the same table slot the
hand-rolled SoC hook did. Reviving the routing would also break
other multi-level Xtensa SoCs (ace, mt8xxx, imx8 DSPs) that never
provided the hook. Remove the dead functions, the hook declaration
and its cavs implementation instead.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The sy1xx SoC init ran as a SYS_INIT at PRE_KERNEL_1 priority 0, before
any device initialization. Convert it to the SoC early init hook, which
runs at the same point, and select SOC_EARLY_INIT_HOOK for the series.
No functional change; this aligns the sy1xx series with the SoC hook
convention already used across the tree.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The CAT1A PSOC6 and PSOC6 legacy SoC init (SystemInit) ran as a
SYS_INIT at PRE_KERNEL_1 priority 0, before any device initialization.
Convert both to the SoC early init hook, which runs at the same point,
and select SOC_EARLY_INIT_HOOK for the PSOC6 and PSOC6 legacy families.
No functional change; this aligns these families with the SoC hook
convention already used across the tree.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add non-cacheable memory support on the esp32p4 by reserving a
power-of-two window at the top of HP SRAM and marking it
non-cacheable with a PMA NAPOT entry at boot. The window keeps its
normal cached address so it stays reachable by the DMA engine,
while CPU accesses bypass the cache, so both masters see coherent
data through one address.
The region size comes from the sramhp_nocache devicetree node and
the base is derived per silicon revision, whose SRAM and cache
layouts differ. The PMA entry is re-applied on wake from standby
because the PMA CSRs are volatile across CPU power-down sleep.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When LTO is enabled, inlining of functions is more likely. Enable
SOC_IT8XXX2_RAM_CODE_NOINLINE by default when LTO is enabled.
Tested RAM resident flash routines (ramcode_flash_write, etc.)
on ITE EC.
Signed-off-by: Keith Short <keithshort@google.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/microchip/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add default configuration for Coordinated Sampled Listening
(CSL) features to Silabs S2 defconfig.
Signed-off-by: David Boullie <David.Boullie@silabs.com>
Enable am62l_evm board support for rtc sample as a counter.
Set default init priority greater than counter driver for RTC to be
used as counter.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
- Add power management support for Infineon PSOC4 for Deepsleep.
- Configure Watchdog Timer as the wakeup source.
Signed-off-by: Deepika R <deepika@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Niranjan M <niranjan@aerlync.com>
The commit 06dd00c340 changed how the tfm_api library is
build which is now only build when !CONFIG_TFM_USE_NS_APP.
Since the tfm_api includes the ioctl NS API calls the soc_secure.c
implementation fails with unresolved references when the TF-M
tests are being build (since only the TF-M tests use
CONFIG_TFM_USE_NS_APP as for now).
This adds a dummy implementation of the soc_secure functions for
this use case. The dummy functions allow us to build and only
affect the TF-M tests which don't use these services anyway.
The alternative will be to remove the soc_secure.c from building
but then we will have to ifdef the references to it which is more
intrusive.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
The clock tree reference-clock setup gates the flash MSPI clock during
early boot, which stalls the bootloader on esp32c5 and esp32p4. Remove
the call from both hw_init paths so the flash bus stays clocked.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Deep-sleep-only builds (CONFIG_PM disabled) lack the sleep
retention init path that normally sets up the REGDMA clock ICG
context on ESP32-P4. Call sleep_clock_icg_startup_init before
entering deep sleep so the required clock gating is configured.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Sleep support code linked into the bootloader keeps its state in
RTC-retained sections, but the bootloader linker script has no place
for them, leaving them orphaned. Collect the force_slow and force_fast
sections into the data segment so the symbols stay defined.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Sleep support code linked into the bootloader keeps its state in
RTC-retained sections, but the bootloader linker script has no place
for them, leaving them orphaned. Collect the force_slow and force_fast
sections into the data segment so the symbols stay defined.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Pre-v3 P4 puts the 2nd-stage bootloader in low SRAM (below 0x4ff3abd0),
not at the top of the app region like v3.x. Anchor MCUboot and the segment
floor by revision, while freeing full sram_high range for the
application. Fixes MCUboot startup crash on rev 1.3.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add TDM FIFO offset macros, ACP_PDM_2_Enable register offset, and
the acp_tdm_context struct with a frame_fmt field for per-instance
sample format tracking.
Remove ACP_DEFAULT_SAMPLE_RATE from chip_offsets.h as it is now
defined in the TDM DAI driver to avoid duplication.
Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Signed-off-by: Sneha Voona <sneha.voona@amd.com>
Enable split TCM/OCM images on Versal RPU: rom_start (boot stub plus
arch vector table) is linked at TCM address 0 while the Zephyr image
runs from on-chip memory (OCM, typically 0xFFFC0000).
Add versal_rpu_ocm_boot, a TCM-resident assembly stub placed at the
start of rom_start via rpu_ocm_boot.ld. On reset it programs a minimal
MPU map (TCM, 2 GB device window, OCM SRAM), clears VINITHI, enables
the MPU and caches, then branches to z_arm_reset in OCM.
SOC_VERSAL_RPU_OCM_BOOT is selected when ROMSTART_RELOCATION_ROM is
enabled and zephyr,sram lies in OCM (address >= 0xFF000000). It sets
KERNEL_ENTRY to the boot stub, selects ARM_MPU_BOOT_CONFIGURED, and
relies on z_arm_relocate_vector_table() to copy the vector table to
address 0 once OCM is reachable.
Provide relocate_vector_table() in rpu_ocm_mpu_init.c to copy vectors
and perform D-cache clean/invalidate plus I-cache invalidate so
exception dispatch at 0x0 remains executable with caches enabled.
Expand the vectors MPU region to 256 B so the relocated table and its
literal pool remain executable.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Zephyr driver and soc code referenced five CONFIG symbols that were
only declared in the hal module, so a compliance run without the
module in place flagged them as undefined.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
On ESP32-P4 the PSRAM and MPLL share an internal LDO rail that
is owned by the devicetree regulator driver, which powers it at
PRE_KERNEL_1. The PSRAM chip init used to run in the pre-kernel
platform entry, before that regulator came up, so the chip was
unpowered during detection and failed with "PSRAM chip is not
connected" on v3.x silicon.
Move the ESP32-P4 PSRAM init to a PRE_KERNEL_1 SYS_INIT at the
default priority, which runs after the regulator has enabled the
rail and before any consumer of the external RAM heap. Other
Espressif SoCs keep their existing pre-kernel init and are
unaffected.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
On some MAX32 SoCs, leaving the instruction cache enabled when entering
standby mode can result in a HardFault. Disable the instruction cache
before entering standby as a workaround.
Signed-off-by: Kevin Gillespie <Kevin.Gillespie@analog.com>
The esp32-s2 and esp32-s3 provide the instr_mem devicetree
node and arch_is_instr_mem but did not select the word
granular access path. Without it the loader issues narrow,
unaligned stores to IRAM and faults while loading relocatable
extensions.
Select ARCH_HAS_WORD_GRANULAR_ACCESS_INSTR_MEM on both
series, as already done for the esp32.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The MCWDT used as a low power kernel timer is a bit of an odd ball
IP block with cascading counters cascade on match rather than
overflow. This means we cannot treat counter0/counter1 as a 32bit
counter and compare.
Trying to have a kernel tick rate that matches the low frequency clock
means we are trying to set the compare value too close to the current
time to allow for single tick timeouts as the kernel sleep test validates.
The best tick rate we can actually achieve is a fraction of the low
frequency clock.
Per the architecture docs "it may take up to 2 CLK_LF cycles for a new
match compare to take effect". Meaning at best we can set a new compare
for 2 cycles away from the current one. Setting the tick rate to 1/4
of the low frequency clock guarantees this.
Reduce the kernel tick rate to 1/4 the low frequency clock rate which
allows us to sleep for the correct, if imprecise, amount of time without
inadvertently rolling over and sleeping much longer than expected.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
Commit 63f80e82d5 ("soc: silabs: Make Series 1 SoCs use power manager")
replaced the "if(S0 OR S1)" gate around soc_power.c with an unconditional
"else" branch. As a result, soc_power.c (the Gecko emlib implementation
using EMU_EnterEM1..4 from em_emu.h) was compiled for every family that is
not (S1+power-manager) or S2 -- including the SIWX91X family.
The SiWx917 has no emlib and provides its own PM backend in
soc/silabs/silabs_siwx91x/siwg917/power.c, so pulling in soc_power.c both
fails to compile ("implicit declaration of function 'EMU_EnterEM1'") and
would duplicate pm_state_set().
Restrict the soc_power.c branch to the Gecko S0/S1 families via elseif so
non-Gecko Silabs families are excluded again.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This allows for more secure entropy, which is useful for e.g. Bluetooth or
OpenThread. The changes were adapted from xg12.dtsi.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
This is needed to integrate nicely with librail, the closed source radio
library for silabs SoCs. It also integrates nicely with sleeptimer, which
Zephyrs silabs_sleeptimer_timer.c uses internally.
While this might also work with Series 0, I don't have the hardware to test
that, so it stays disabled for now.
Adjustments I made to soc_power_pmgr.c:
- gecko_sdk doesn't have hfxo manager, so surround it by the relevant
ifdefs.
- gecko_sdks power manager doesn't support EM4, so call EMU_EnterEM4 for
that, like their SDK code does.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Adjust mcuboot.ld creating another segment from dram_seg,
dram_loader_seg, to place objects accessed by code in
iram_loader_seg as they must not be overlapped while loading
main application.
Reorganize the memory layout to improve these memory spaces
for MCUboot's Zephyr Port.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Enable STM32C5 PM integration in soc build and Kconfig, and add power
state definitions for STOP0 and STOP1 in stm32c5.dtsi.
Add soc-level PM implementation files for suspend-to-idle and poweroff
handling on STM32C5.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Espressif Xtensa platforms (ESP32, ESP32S2/3)
utilize a modified Harvard architecture.
Signal this so that LLEXT can make use of it,
and add heap definitions to linker script.
Also remove unneeded heap definitions from
appcpu targets which cannot run LLEXT.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Adds arch-level instruction memory API with functions
for memcpying / memsetting and determining whether a
region is in instruction memory. Implement API for
Xtensa and ESP32, with support for word granular access.
Adds definitions for instruction memory to
Xtensa ESP32 platforms.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/silabs/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The flash on the ch32v series starts at 0x8000000 and, depending on
the system configuration, is aliased to 0x0. PR #110383 fixed flashing
with minichlink by changing the flash Devicetree entry to point at the
flash base, not the alias, but this broke the boot.
Fix by updating the ch32v003 and ch32v00x vector.S to jump into flash.
This matches the behaviour of the other ch32v series startup code.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The previous table passed DT_CHOSEN_SRAM_ADDR directly as the MPU
region base with REGION_SRAM_SIZE derived from DT_CHOSEN_SRAM_SIZE
alone. This has two distinct failure modes:
1. Alignment fault: ARMv7-R requires base_address % region_size == 0.
With the ZynqMP RPU DDR alias at 0x100000 (1 MiB), the base is not
aligned to the 256 MiB REGION_SRAM_SIZE. The hardware silently
masks the low bits, so the effective region becomes 0x0-0x0FFFFFFF.
The linker places the stack at 0x10100000, outside that window,
causing Background Faults on every stack access near the top of RAM.
2. AMP isolation: in designs where the R5 application occupies a high
DDR partition (e.g. 0x50000000-0x7FEFFFFF), anchoring at 0x0 maps
Linux DDR (0x100000-0x4FFFFFFF) as R5-cacheable normal memory,
breaking cache coherency and AMP isolation.
Replace the fixed-base approach with a compile-time selection that,
for each candidate size (256M/512M/1G/2G), rounds DT_CHOSEN_SRAM_ADDR
down to the corresponding naturally-aligned boundary, then checks
whether base + size covers DDR_END = DT_CHOSEN_SRAM_ADDR +
DT_CHOSEN_SRAM_SIZE. The smallest fitting size is selected, giving
the tightest naturally-aligned single region.
Example outcomes:
SRAM=0x100000, SIZE=256M: base=0x00000000, REGION_512M (unchanged)
SRAM=0x50000000, SIZE=767M: base=0x40000000, REGION_1G
(vs old base=0x0, REGION_2G: 1 GiB of Linux DDR no longer mapped)
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Introduce SOC_XILINX_ZYNQMP_APU for ARM64 Cortex-A53 with MMU and
arm_arch_timer defaults. Build soc.c and arm_mpu_regions.c only for
the RPU variant; add ARM64 linker script for the APU.
Register zynqmp_apu in soc.yml and add dts/arm64/xilinx/zynqmp_a53.dtsi
with GIC-400 (GICD @ 0xf9010000, GICC @ 0xf9020000) and core PS
peripherals: UART0/1, TTC0-3 timers, and ARMv8 arch timer.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Create APLIC direct mode test cases to exercise APLIC with direct mode,
and include direct-mode QEMU in places where other qemu_riscv32 variants
are included.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Extend bflb_rf_init() to support WiFi mode (WL_API_MODE_ALL) with
TX power targets and country code configuration when CONFIG_BFLB_WIFI
is enabled.
Add WiFi platform glue: MAC ISR wiring, task creation, low-power
stubs, wl80211 RTOS primitives (heap, RNG, timers), and the linker
section for WiFi shared RAM.
Introduce CONFIG_BFLB_BL61X_WL_RMEM_SIZE for PHY/RF retention memory
sizing.
Signed-off-by: William Markezana <william.markezana@gmail.com>
