Commit graph

5973 commits

Author SHA1 Message Date
Tamas Jozsi
2c43a00f65 boards: fix Bluetooth LE support on the SparkFun ThingPlus Matter MGM240
Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.

Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
2025-06-21 15:31:36 +02:00
Tamas Jozsi
e4dc7c9fb1 soc: silabs: Add support for the MGM240SD22VNA
Also introduce the framework to support other
Silicon Labs modules.

Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
2025-06-21 15:31:36 +02:00
Camille BAUD
8c385be293 soc: bflb: enable clock_control for bl60x
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-21 10:40:20 +02:00
Sylvio Alves
db1fe6005a soc: espressif: align flashing address with DTS configuration
The current CMakeLists.txt uses hardcoded flash addresses for the
bootloader and application, which may not match the slot defined
in the DTS file. This can lead to inconsistencies when flashing
and running images.

This update introduces support for using CONFIG_FLASH_LOAD_OFFSET
and applies CONFIG_BUILD_OUTPUT_ADJUST_LMA if specified,
ensuring that the final image address aligns with the DTS
and runtime expectations.

Note: For ESP32-C6, a custom workaround is included since the
LPCORE does not support MCUboot images.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-06-21 08:19:47 +02:00
Mathieu Choplain
fcd30046cb drivers: pinctrl: stm32: add support for STM32N6 pinctrl
Modify the STM32 pinctrl driver and SoC-specific pinctrl macros
to introduce support of the st,stm32n6-pinctrl variant.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-20 13:21:55 -04:00
Alain Volmat
6274df7a0b soc: st: stm32: stm32n6: set 256 SMH buffer alignment for LTDC
Set the LTDC buffer alignment to 256 in order to avoid an
issue when accessing to PSRAM via XSPI.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-19 13:57:51 +02:00
Alain Volmat
d33f579684 soc: st: stm32: set default video buffer align to 16 for DCMIPP
Set the default video buffer alignment constraint to 16 when DCMIPP
is being used.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-19 13:57:51 +02:00
Alain Volmat
7640180e7c soc: st: stm32: set default SMH attribute for LTDC/video buffers
The SMH attribute when using the XSPI PSRAM is set to EXTERNAL (2)
within the driver hence set default for both LTDC and video
buffer SMH attribute to 2 if all conditions are validated.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-19 13:57:51 +02:00
Marek Matej
648bfe090c soc: espressif: Support large buffers in custom PSRAM sections
Several subsystems have configuration options that allow large buffers
to be placed in specialized memory sections. When PSRAM is enabled, the
MBEDTLS heap and LVGL heap and buffer can be relocated to custom sections
within the PSRAM segment.

Enabling `CONFIG_ESP_SPIRAM` together with any of the following options:
* `CONFIG_MBEDTLS_HEAP_CUSTOM_SECTION`
* `CONFIG_LV_Z_MEMORY_POOL_CUSTOM_SECTION`
* `CONFIG_LV_Z_VDB_CUSTOM_SECTION`

will place the corresponding buffers into the `.mbedtls_heap`,
`.lvgl_heap`, and `.lvgl_buf` sections, respectively.
If none of these custom section options are enabled, the buffers will
fall back to the `.ext_ram.bss` section.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-06-19 09:36:27 +02:00
Declan Snyder
877fa975cc spi_nxp_lpspi: Remove MCUX branding
Since the LPSPI drivers no long use MCUX at all, remove the MCUX
branding, to avoid confusion. In the future if an implementation uses
the MCUX SDK driver, it should specifically be called by MCUX in the
name.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Jori Rintahaka
0810fe3edb soc: silabs: fix too small BT_LONG_WQ_STACK_SIZE
Increase the long workqueue stack size to prevent it from being
overflown for example in the GATT database hashing. This leaves
us with a bit less than 200B of headroom as of today

Signed-off-by: Jori Rintahaka <jori.rintahaka@silabs.com>
2025-06-18 17:45:51 -04:00
Ella MA
3f58d49843 soc: mec172x: ecia: Adjust girq_regs to avoid flexible-array-like behaviors
Struct girq_regs has an array field of length 1 at its end. Since this
field is never used in the code base, we can replace it with a non-array
field of its original element type to remove the flexible-array-like
behaviors and avoid using a flexible array file in the middle of a
struct or defining an array of flexible array struct type.

Fixes zephyrproject-rtos#84251

Signed-off-by: Ella MA <xutong.ma@inria.fr>
2025-06-18 09:25:04 -04:00
Camille BAUD
eb06f11a8f soc: bflb: fix bl60x using wrong mtime freq
use new timebase-frequency to fix the timebase of this SoC

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-18 09:12:26 -04:00
Carles Cufi
d215f5efec soc: nordic: 54h20: bicr: Fix order of enum
The order of the enumNames array needs to match the actual enum values
array below it.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2025-06-18 09:08:25 -04:00
Abhinav Kulkarni
cb598a321a boards: shield: nxp_m2_wifi_bt: Updated reg domain
Set regulatory domain to default US for IW610 and RW610 socs
and WW for IW416 and IW612 socs.

Signed-off-by: Abhinav Kulkarni <abhinav.kulkarni@nxp.com>
2025-06-18 11:21:43 +01:00
Yangbo Lu
b8baa19a63 soc: nxp: imx943: support NETC initialization during soc_init
Added support for NETC initialization during soc_init.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2025-06-18 07:37:24 +02:00
Benjamin Cabé
acc1731410 soc: mediatek: fix typo in macro name
s/SOC_SERIES_MT8195/CONFIG_SOC_SERIES_MT8195/

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-17 17:45:47 +02:00
Keith Packard
d44f8065da soc/esp32c6: Discard .note.GNU-stack sections while linking
These sections are simple stack behavior annotations and are not
needed in the final executable.

Signed-off-by: Keith Packard <keithp@keithp.com>
2025-06-17 16:06:21 +02:00
Keith Packard
ce7bd57618 soc/sensry: Discard .note.GNU-stack sections while linking
These sections are simple stack behavior annotations and are not
needed in the final executable.

Signed-off-by: Keith Packard <keithp@keithp.com>
2025-06-17 16:06:21 +02:00
Keith Packard
246c8272cc soc/openisa: Discard .note.GNU-stack sections while linking
These sections are simple stack behavior annotations and are not
needed in the final executable.

Signed-off-by: Keith Packard <keithp@keithp.com>
2025-06-17 16:06:21 +02:00
Youssef Zini
c7d8e03ccf soc: linker.ld: add linker script for stm32mp2x
Add a linker script for the stm32mp2x soc series. It includes the
standard arm cortex-m linker and adds standard zephyr relocation
sections.
Replace the rom_start section name with .isr_vectors in the linker
script. This is necessary for the zephyr firmware to be started by the
remote proc driver which expects the section containing the vector table
to be named .isr_vectors.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
2025-06-17 08:20:33 +02:00
Youssef Zini
e3953f10ad soc: stm32: add initial soc support for stm32mp2x
Add initial soc support for the stm32mp2x series, including
initial Kconfig entries and default configuration files.
This enables Zephyr to recognize and build for the stm32mp2x series,
taking the stm32mp257f_ev1 as a baseline.

Includes:
- Kconfig and defconfig files for SoC selection and defaults
- soc.h for hal headers
- CMakeLists.txt for build system integration
- soc.yml update to register the new SoC

System Clock is configured statically from DTS. So no initialization
hook or soc.c needed.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
2025-06-17 08:20:33 +02:00
Jiafei Pan
dc68d1bb10 soc: imx943: a55: disable D-Cache when booting from el2
Enabled CONFIG_ARM64_BOOT_DISABLE_DCACHE to disable D-Cache when
booting from EL2.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-17 07:22:51 +02:00
Hao Luo
a54197b2f8 soc: ambiq: workaround for issue #90777
This commit workarounds issue #90777

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-06-17 07:22:44 +02:00
Hieu Nguyen
73c63f9ca6 soc: renesas: Add initial support for Renesas RZ/V2N
Add initial support for Renesas RZ/V2N

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2025-06-16 14:00:22 -04:00
Khaoula Bidani
85e6cc421e soc: st: stm32: Add series stm32u3
Add STM32U3 familly support

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-16 13:59:38 -04:00
Amneesh Singh
c7a21c3da5 soc: ti: k3: add AM2434 support
Add SoC support and device trees for Texas Instruments AM2434 SoC. Both R5
and M4 cores are supported here.

Signed-off-by: Amneesh Singh <a-singh7@ti.com>
2025-06-16 13:59:09 -04:00
Amneesh Singh
9814590eb3 drivers: pinctrl: make ti_k3 multi-instance
Some devices have multiple pinctrl regions; for instance, main pinctrl and
mcu pinctrl. Currently there can only be a single pinctrl instance picked
form a DT label. This patch makes the pinctrl driver initialise one
instance for each node with correct compatible string.

Signed-off-by: Amneesh Singh <a-singh7@ti.com>
2025-06-16 13:59:09 -04:00
Alvis Sun
d789d13ec0 soc: nuvoton: npcx: update default SYS_CLOCK_HW_CYCLES_PER_SEC
Added support for deriving `SYS_CLOCK_HW_CYCLES_PER_SEC` from the
Device Tree by reading the `clock-frequency` property in the `itim` node.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
2025-06-16 14:13:55 +02:00
Tim Lin
a62f157118 drivers/espi: ite: Add it51xxx compatibility with it8xxx2 support retained
The driver originally supported only it8xxx2 series. This updates
introduces compatibility allow it to also support it51xxx series
with minimal changes.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-06-16 14:12:44 +02:00
Sylvio Alves
213142db21 soc: espressif: riscv: disable local isr location
Disable support to local ISR declaration on Espressif SoCs.
Code relocation is not yet supported, causing build fail.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-06-13 15:40:09 -07:00
Aksel Skauge Mellbye
b3db3a3bda soc: silabs: s2: Only configure SMU and SAU once on boot
If a bootloader is used, it will configure the SMU and SAU.
The application cannot also configure it, since it can't know
what alias (S vs NS) to access the CMU through. Only connect
the interrupt to the application's vector table if a bootloader
is present.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-06-13 10:15:03 -07:00
S Mohamed Fiaz
aaf21a4c9e soc: silabs: siwx91x: Add configurable power profile support via DeviceTree
This commit adds support for configuring the power/performance
profile for the siwx91x device using a generic
'power-profile' property in DeviceTree.
The property is available for NWP nodes,
allowing flexible selection of power management
profiles per application or board via overlay.

Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
2025-06-13 10:08:38 -07:00
S Mohamed Fiaz
132247e2cd soc: silabs: siwx91x: Add siwx91x Power Manager driver
This commit enables the Power Manager driver
support for the siwx91x device.

Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
2025-06-13 10:08:38 -07:00
Sebastian Głąb
2b4f64522e modules: hal_nordic: nrfx: Add mising UARTE23/24 Kconfigs
Add UARTE23 and UARTE24 missing Kconfig options and their
translation to NRFX configuration macros.

Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
2025-06-13 10:31:17 -04:00
Sebastian Głąb
c0a28ab561 drivers: spi: Support spim23 and spim24 instances
Extend SPI driver with possibility to use
- spim23, spim24,
- spis23, spis24.

Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
2025-06-13 10:31:17 -04:00
Mathieu Choplain
1793934e61 soc: st: stm32n6: invoke signing tool in silent mode
The STM32 signing tool (STM32_SigningTool_CLI) is invoked as a post-build
command to generate a signed Zephyr binary, which is required to run from
flash on N6 series. If the file specified as output already exists, the
tool will by default prompt to confirm it should be overwritten. However,
when invoked from the build system rather than a terminal, this prompt
will break the build (freeze during the "Linking zephyr.elf" step). This
can be seen by building the same application twice in a row, as the second
build will not be different enough to make the build artifacts be deleted
and thus the (old) signed image will be seen by the tool.

Invoke the tool in silent mode such that user is never prompted. This fixes
build failures while still working as intended (if present, the existing
signed image will get overwritten properly).

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-13 14:29:18 +02:00
Benjamin Cabé
4cac6583f7 soc: sensry: fix irq enable/disable
SET/CLR registers are write-only so trying to
read/modify/write is inefficient & illegal

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-13 11:12:55 +02:00
Benjamin Cabé
a933fb7bcc soc: sensry: remove unnecessary parenthesis from macro
removed redundant parentheses

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-13 11:12:55 +02:00
Ali Hozhabri
529a8dd147 soc: stm32: stm32wb0x: Restore main stack size to the default value
Restore main stack size to the default value since fake entropy
implementation from mbedtls is replaced by STM32 entropy driver.

Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
2025-06-12 09:32:41 -07:00
Krzysztof Chruściński
1dc42fc227 soc: nordic: nrf54h: Allow using NFCT pins as gpios on cpurad
NFCT is by default assigned to application so DT node does
not need to be enabled or reserved in DT to have access to
NFCT registers. On cpurad NFCT must be reserved to enable
register access and then antenna pins can be configured as
gpios.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-06-12 11:46:21 +02:00
Krzysztof Chruściński
2d82970710 soc: nordic: common: Fix HAS_HW_NRF_NFCT condition
Include nordic,nrf-nfct-v2 compatible in the option.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-06-12 11:46:21 +02:00
Jakub Zymelka
f87f2dc9b2 soc: nordic: common: poweroff: Set VPR to remain in its reset state
CM33 must write MEMCONF.POWER[VPR].RET = 0 before entering System OFF.
This bit drives the vprSavedCtx input to VPR. Forcing it low will
disable the Hibernate wake feature in VPR, so that VPR will remain
in its reset state when waking from OFF.

Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
2025-06-12 11:34:10 +02:00
Tomasz Chyrowicz
5e54100551 boards: nrf54h20_iron: Allow radio updates
Add necessary changes to provide a simple, updateable radio image.

Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
2025-06-12 11:33:10 +02:00
Neil Chen
ab3d2dc830 boards: frdm_mcxa153,frdm_mcxa156: add hwinfo support
1. enable hwinfo support
   - device_id_get
   - get_reset_cause
   - get_supported_reset_cause
   - clear_reset_cause
2. verified tests/drivers/hwinfo

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2025-06-12 10:24:40 +02:00
TOKITA Hiroshi
344357a5b4 soc: raspberrrypi: rp2350: Add missing FPU support
Add CPU_HAS_FPU to make available the FPU feature.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2025-06-11 16:19:59 -07:00
Keith Packard
513e6ed5d2 arch/common: Mark interrupt tables const when !DYNAMIC_INTERRUPTS
When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.

This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.

Signed-off-by: Keith Packard <keithp@keithp.com>
2025-06-10 22:13:09 +02:00
Yangbo Lu
1d2e1787cb soc: nxp: imx9: add basic support for i.MX943 M33
Added basic support for i.MX943 M33.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2025-06-10 22:07:17 +02:00
Guennadi Liakhovetski
4de0c9abc0 SoC: Intel: ADSP: ACE30: add .imrdata to MMU definitions
On ACE30 platforms adding a section to the linker script isn't
enough, it should also be added to the xtensa_soc_mmu_ranges[] array.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2025-06-10 12:52:38 -04:00
Mathieu Choplain
4282d67ac2 soc: st: stm32h7: synchronize cores during boot properly
On dual-core STM32H7, the Cortex-M4 core is supposed to wait until the
Cortex-M7 initializes the system before starting to execute. CM7 should
signal this by locking a specific HSEM, which CM4 should poll until locked.
However, the logic on the Cortex-M4 side was reading the "RLR" register of
HSEM, which *locks the semaphore on read* - in turn, this makes the CM4
start directly since it sees that the semaphore is locked (by itself).

Use proper LL API to read HSEM status - which will read the "R" register
instead - to make sure CM4 doesn't begin execution earlier than it should.

Suggested-by: hglassdyb
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-10 12:08:35 +02:00