Add the description of NPU Cache (aka cacheaxi) to allow configuring
them in NPU Cache driver.
I intentionally chose this over creating a new dedicated node as
the exclusive user is NPU Cache and this could be done as part of
NPU driver initialization.
Update the NPU driver to take those into account as part of its init
routine.
Signed-off-by: Mickael Guene <mickael.guene@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add DMA nodes for MCXW7X SOC DTS.
This SOC used TRIGMUX instead of DMAMUX.
Enable EDMAv3 for the frdm_mcxw71 and frdm_mcxw72
platforms.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Co-authored-by: Declan Snyder <declan.snyder@nxp.com>
This commit adds the following functionality support:
1. More baudrate setting.
2. 7 bit data moded.
3. Tx (CR_SOUT) and Rx (CR_SIN) signal invert.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Some platforms do not have flash memory. The flash mpu region cannot
be created in case CONFIG_FLASH_SIZE is zero.
Signed-off-by: Yanqin Wei <yanqin.wei@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
Remove the possibility to configure the LPTIM timer clock source
through Kconfig. The deprecation warning was added 3 years ago in
Zephyr 3.2 by commit bbac316be7; more
than enough time has elapsed for this option to be removed.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Set different default value for NXP_FW_DUMP_FLASH_START_ADDR, based on
mimxrt1060_evk board and rw612 soc.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
Add --permit-permanently-transitioning-device-to-deployed safety flag
to gen_uicr.py, required when enabling both UICR.LOCK and
UICR.ERASEPROTECT together. This prevents accidental permanent locking
of devices since this combination makes the configuration irreversible.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add support for UICR.APPROTECT configuration, which controls debugger
and access-port permissions through the TAMPC peripheral.
This introduces three Kconfig options that allow independent control
over access port protection for different processor domains:
- GEN_UICR_APPROTECT_APPLICATION_PROTECTED: Controls debug access to
the application domain processor
- GEN_UICR_APPROTECT_RADIOCORE_PROTECTED: Controls debug access to
the radio core processor
- GEN_UICR_APPROTECT_CORESIGHT_PROTECTED: Controls access to the
CoreSight debug infrastructure
When enabled, each option sets the corresponding UICR.APPROTECT
register to PROTECTED (0xFFFFFFFF), which disables debug access for
that domain. When disabled, the registers remain at their erased value
(UNPROTECTED), allowing full debug access.
This feature is critical for production devices where debug access must
be restricted to prevent unauthorized access to sensitive code and data.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add support for UICR.ERASEPROTECT configuration, which blocks ERASEALL
operations to prevent bulk erasure of protected memory.
This introduces a Kconfig option GEN_UICR_ERASEPROTECT that enables
blocking of ERASEALL operations on NVR0, preserving UICR settings even
if an attacker attempts a full-chip erase.
This is a critical security feature for production devices. When enabled
together with UICR.LOCK, it becomes impossible to modify the UICR in
any way, establishing a permanent device protection scheme. Due to this
irreversibility, it should only be enabled during the final stages of
production.
When enabled, the gen_uicr.py script sets UICR.ERASEPROTECT to
0xFFFFFFFF, which prevents the ERASEALL command from affecting the
NVR0 page.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add support for UICR.LOCK configuration, which locks the entire UICR
configuration in NVR0 to prevent unauthorized modifications.
This introduces a Kconfig option GEN_UICR_LOCK that enables locking
of the UICR. Once locked, the UICR can only be modified by performing
an ERASEALL operation.
This is a critical security feature for production devices, typically
enabled alongside UICR.APPROTECT, UICR.PROTECTEDMEM, and
UICR.ERASEPROTECT to establish a complete device protection scheme.
When enabled, the gen_uicr.py script sets UICR.LOCK to 0xFFFFFFFF,
which configures the NVR0 page as read-only and enforces integrity
checks on the UICR content.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add support for UICR.SECONDARY.PROTECTEDMEM configuration, which enables
configuration of the protected memory region for secondary firmware.
This introduces Kconfig options for configuring:
- GEN_UICR_SECONDARY_PROTECTEDMEM - Enable/disable protected memory
for secondary firmware
- GEN_UICR_SECONDARY_PROTECTEDMEM_SIZE_BYTES - Size of the protected
memory region in bytes
The implementation validates that the configured size is divisible by
4096 bytes (4 KiB) as required by the hardware, and converts it to
4 KiB units when writing to UICR.SECONDARY.PROTECTEDMEM.SIZE4KB.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add support for UICR.SECONDARY.TRIGGER configuration, which enables
automatic booting of secondary firmware based on specific reset reasons.
This introduces Kconfig options for configuring:
- UICR.SECONDARY.TRIGGER.ENABLE - Enable/disable automatic triggers
- UICR.SECONDARY.TRIGGER.RESETREAS - Bitmask of reset reasons that
trigger secondary firmware boot
Individual Kconfig options are provided for each reset reason:
- APPLICATIONWDT0/1 - Application core watchdog timeouts
- APPLICATIONLOCKUP - Application core CPU lockup
- RADIOCOREWDT0/1 - Radio core watchdog timeouts
- RADIOCORELOCKUP - Radio core CPU lockup
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add support for UICR.WDTSTART.
UICR.WDTSTART configures the automatic start of a local watchdog timer
before the application core is booted. This provides early system
protection ensuring that the system can recover from early boot
failures.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Instantiate NRF_PLATFORM_LUMOS for all nrf lumos product,
Add NRF_SKIP_CLOCK_CONFIG kconfig to be a general kconfig
in nordic soc Kconfig, so that it can be used by other
lumos product.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
Enable TFM_BL2_NOT_SUPPORTED configuration for STM32WBA65x SoC since
TF-M does not implement the BL2 boot stage for this SoC series.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Move the RAIL interrupts installer from the Bluetooth HCI driver
to the SoC layer so that it can be used by other subsystems
as well.
Signed-off-by: David Boullie <David.Boullie@silabs.com>
- The UUID is the device unique identifier read from the
OTP and made available in boot report to avoid the repetitive
slow reads from OTP.
Signed-off-by: Aymen LAOUINI <aymen.laouini@nordicsemi.no>
Add explicit PMP_GRANULARITY default value of 8 to RMX SoC configuration.
This makes the PMP configuration more explicit and easier to understand.
No functional change as RISCV_PMP was already enabled and PMP_GRANULARITY
already defaulted to this value.
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
Uses shorter names for the RMX SOC configuration.
Changes:
- SOC_SERIES_NSIM_ARC_V_RMX -> SOC_SERIES_RMX
- SOC_NSIM_ARC_V_RMX100 -> SOC_RMX100
Also updates board Kconfig to use the shorter names.
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
Add device tree binding file for the Synopsys ARC-V RMX RISC-V
CPU core. This binding enables proper device tree property parsing by
the Enhanced Device Tree (EDT) system, allowing Kconfig device tree
macros to access CPU properties like clock-frequency.
The binding includes the standard RISC-V CPU properties by extending
riscv,cpus.yaml, which provides access to properties defined in cpu.yaml
such as clock-frequency.
Also removes hardcoded SYS_CLOCK_HW_CYCLES_PER_SEC from board level
and adds DT-derived value to RMX SoC level.
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
RX26T MCU support mapped interrupt features, add dependency config to
enable zephyr library source from hal
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Initial commit to support DTC driver on Renesas RX130.
* drivers: DTC: implementation for DTC driver on RX130.
* dts: rx: update dts node in SoC layer to support DTC on RX130.
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Move Xuantie supprot from arch/riscv/core/xuantie to the custom common
layer arch/riscv/custom/thead, with the following changes:
1. Rename Kconfig name
CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO
2. Split the original arch/riscv/core/xuantie/Kconfig to
a. arch/riscv/custom/thead/Kconfig: for T-Head extension
b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series
(e.g. Xuantie E907)
3. Move cache line size defaults to SoC devicetree
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Update OpenISA RI5CY and Zero-RISCY CSR handling to use RISC-V custom
CSR common code. Move these stuff to 'arch/riscv/custom/openisa':
1. Rename 'soc_ri5cy.h' to 'ri5cy_csr.h' for CSR definitions.
2. Rename 'soc_zero_riscy.h' to 'zero_riscy_csr.h' for CSR definitions.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move compiler option '-march=rv32imcxpulpv2' to common code.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h',
allowing other SoCs using the CVA6 core to reuse the same CSR definitions.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to
'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Egis ET171 implements Andes custom CSRs. Enable the following features:
1. Low level initialization of Andes CSRs
2. HWDSP and PowerBrake extensions with context save/restore
3. EXEC.IT extension
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
TLSR951x also supports Andes extended CSR. Reworks the following CSR
handling to use the RISC-V custom CSR common code:
1. Use common macros for HWDSP CSR context save/restore.
2. Use common macros for PFT CSR context save/restore.
3. Use common low-level CSR initialization via __reset hook.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Rework Andes-specific CSR to use RISC-V custom CSR common code.
Move these stuff to 'arch/riscv/custom/andes':
1. Rename 'soc_v5.h' to 'andes_csr.h' for CSR definitions.
2. Replace '_start' with '__reset' hook for low-level CSR initialization.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move 'EXECIT' CSR support to common code.
5. Move PMA CSR driver to common code.
6. Use RISC-V common linker.ld instead of SoC-specific linker.ld.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Apply the same CONFIG_ESPI_IT8XXX2 guard to the .h2ram_pool section
in the IT51XXX linker script, since the eSPI driver is compatible with
IT8XXX2. This keeps linker behavior consistent and avoids unused
memory allocation on non-eSPI platforms.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The .h2ram_pool linker section was previously always included, even on
platforms that do not enable eSPI. This caused unnecessary memory
reservation in the RAMABLE_REGION for non-eSPI configurations.
Add a CONFIG_ESPI_IT8XXX2 guard around the .h2ram_pool section definition
so that it is only included when eSPI support is enabled.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Limit the loop to the smaller of nvic_iser_nb and
GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT to ensure safe access.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
The CONFIG_BUILD_NO_GAP_FILL option became obsolete after commit
2e8868c16e and has since been deprecated.
Remove the unused Kconfig select from the CC23x0 SoC configuration.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Use cpuapp_slot_partition instead of slot0_partition, so it is possible
to add MCUboot header through --pad-header option.
In such cases, the FLASH_LOAD_OFFSET does not point to the begining of
the slot, but to the beginning of the executable area, thus the check
for the active slot should use ranges instead of exact values.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Use sleep mode instead of Low Power Mode (LPM). LPM is
similar to deep sleep, not intended to be used for general
idle.
Signed-off-by: Kevin Gillespie <Kevin.Gillespie@analog.com>
