Use PSCI CPU suspend to implement CPU idle for Cortex-A55 Core on i.MX 93.
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The RT1180 platform requires periodic communication with the EdgeLock
Enclave (ELE) to prevent system reset. According to RT1180 SRM section
3.11 "ELE active timer", the ELE must be pinged at least once every
24 hours.
This commit implements ELE ping functionality using Zephyr's software
timer API (k_timer). The timer is configured to ping the ELE every
23 hours (instead of 24) to account for potential clock inaccuracies.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
We will standardize how the I2C driver supporting MEC172x/4x/5x
and onwards gets the states of the SCL and SDA lines. For MEC172x we
use the Zephyr GPIO driver to get the pin states. For MEC174x/5x and
future parts based on v3.8 I2C hardware we can use a new feature
of the bit-bang control register allowing live reading of the pin
states without switching the internal MUX. The SoC common code
for MEC172x to read GPIO's using direct register access is
removed by this commit.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Resolved an issue where repeated flash/debug cycles
would fail, requiring the board to be placed in ISP
mode before it could be programmed again.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Allow unlocking partitions as part of early_init_hook if the device tree
contains an unlock configuration as part of ti,control-module.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Currently we maintain addresses and values as static configurations using
static configurations and macros in ctrl_partitions.c. Instead use the
new ti,control-module binding to get these values from the device tree and
unlock the partitions during early init.
Only compile and call `k3_unlock_all_ctrl_partitions` if at least one node
with status okay and compatible "ti,control-module" is present.
Also make sure to map and unmap the regions in case MMU is present.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Adjust the backup SRAM initialization to PRE_KERNEL_1 to ensure it's
initialized before any retained_mem instances placed into that area.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add support for the Ensemble E1C series and the AE1C1F4051920PH0
SoC within this series. The E1C (E1 Compact) series contains a
single Cortex-M55 core configured as RTSS-HE (High Efficiency
Real Time Subsystem) with a maximum frequency of 160 MHz.
The E1C series uses SOC_FAMILY_ENSEMBLE_RTSS helper symbol
introduced earlier to share the CPU architecture configuration
with the E4, E6, and E8 series.
Link: https://alifsemi.com/ensemble-e1c-series/
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Change ctr_drb random implementation to use PSA Crypto API.
Since name convention is very different and PSA abstracts the
algorithm used to generate CSPRNG, file and Kconfig options were
changed. Current symbols were deprecated and just select the new
one.
Signed-off-by: Flavio Ceolin <flavio@hubblenetwork.com>
For !TRACING, most arch_cpu_idle and arch_cpu_atomic_idle implementation
relies on the fact that there's weak stub implementations in
subsys/tracing/tracing_none.c, this works, but the arch_cpu_idle sits in
hot code path, so we'd better to make it as efficient as possible.
Take the riscv implementation for example,
Before the patch:
80000a66 <arch_cpu_idle>:
80000a66: 1141 addi sp,sp,-16
80000a68: c606 sw ra,12(sp)
80000a6a: 37c5 jal 80000a4a <sys_trace_idle>
80000a6c: 10500073 wfi
80000a70: 3ff1 jal 80000a4c <sys_trace_idle_exit>
80000a72: 47a1 li a5,8
80000a74: 3007a073 csrs mstatus,a5
80000a78: 40b2 lw ra,12(sp)
80000a7a: 0141 addi sp,sp,16
80000a7c: 8082 ret
NOTE: the sys_trace_idle and sys_trace_idle_exit are just stubs when
!TRACING
after the patch:
80000a62 <arch_cpu_idle>:
80000a62: 10500073 wfi
80000a66: 47a1 li a5,8
80000a68: 3007a073 csrs mstatus,a5
80000a6c: 8082 ret
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
When __soc_handle_irq is called inside _isr_wrapper, it actually expects
the function to return an IRQ number but the declaration of
__soc_handle_irq in the header has it returning `void` instead. Fix the
declaration to reflect that it actually returns an XLEN-length integer.
All existing implementations of __soc_handle_irq already follow this
behavior by either not modifying the a0 register or setting it to the
correct IRQ number, and follow the calling convention in all other
respects:
* soc/ite/ec/common/soc_irq.S: trampoline to
`uint8_t get_irq(void* unused)`
* soc/adi/max32/soc_irq_rv32.S: internally calls
`uint32_t max32_rv32_intc_get_next_source(void)` and doesn't modify
a0 afterwards
* soc/openisa/rv32m1/soc_irq.S: does not modify a0, and obliquely
refers to this issue in a comment explaining why the function isn't
implemented in C
* soc/common/riscv-privileged/soc_irq.S: does not modify a0
* all others: stub (just `ret`), which is a valid implementation of the
integer identity function
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
For adding metadata and verifying images on Infineon Edge devices
switch to using the mcuboot tool imgtool rather than depending on
the Infineon specific edgeprotecttools. For the purposes required
in the Zephyr environment this is more than enough.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Infineon PSOC4 parts share many ports with a single IRQ line. Using the
SHARED_INTERRUPT handler feature of Zephyr results in a very large IRQ
vector table. Instead structure in DT the idea that the ports are
sharing an interrupt with a sort of pseudo interrupt controller.
This also rectifies the need to ifdef on CAT1C/M0+. I added a note
making it clear that in those cases we likely need to rework the way
interrupts are done anyways as there's secondary interrupt
muxes/controllers involved.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
PR #103203 introduced a regression for mcxw70 builds by incorrectly
moving `HAS_PM` from MCXW72 to MCXW70.
This fix restores the correct configuration.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Add support for dynamic allocation and freeing of DPPI connections
on nrf54h20. It is not longer required to use devicetree to allocate
specific channels that will be used by the application. nrfx_gppi on
nrf54h20 cpuapp behaves in almost the same way as on other targets.
The main difference is that allocating PPI connection requires
communication with Ironside through IPC.
It means that:
- allocation and freeing can only be done from the thread context
- allocation and freeing is slower
Currently, there is no support for controlling PPI connections in
global domain on other cores. It is expected that cpuapp will
setup PPI for VPR (ppr, flpr) as such approach reduces the need for
nrfx_gppi driver being present on ppr/flpr and those cores are
memory constrained.
Regarding cpurad, it is expected that PPI connections are static so
they can be setup manually, using DT and HAL. During initialization
nrfx_gppi on cpuapp gets the information about all PPI resources that
are statically allocated (using the devicetree) and they are excluded
from the pool of available channels.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support for handling connections within the radio domain
using the new GPPI helper.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add initial support for Renesas R-Car V4H SoC.
Support Zephyr RTOS on Cortex R52, 1.4GHz core.
For more information and documentation, please visit the product page:
https://www.renesas.com/en/products/r-car-v4h
Signed-off-by: Duy Dang <duy.dang.yw@renesas.com>
For STM32H5 series, only the cell compensation can be configured,
as the HSLV configuration is controlled on a per pin basis and
not on a per domain basis as for other STM32 series.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add missing Kconfig selection to enable the Data Watch and Trace unit for
the PSOC6 family of devices using a Cortex-M4 core.
Signed-off-by: Alexander Roodt <alexander.roodt@deepgate.ai>
Fix implementation so that sleep start routine is called at
pm_state_set() (entry) instead of pm_state_exit_post_ops().
Add RTC timer wakeup management, as well as code for deep
sleep.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
When AES is activated in the DT, configure it's register region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
The litex bootloader doesn't support XIP by default,
so remove it. In the board it was already deactivated.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Switch from OS timer-only approach to dual-timer strategy for improved
low power timing precision, especially for connectivity applications.
The previous approach used OS timer for both system ticks and low power
wakeup. With low tick rates, sleep time calculations lacked
precision, causing premature wakeups before BLE events, increasing power
consumption.
This rework uses high-precision SYSTICK during operation and switches
to OS timer for low power wakeup and coordination with link layer
event scheduling.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Add PM support for nrf92 series products
by making power management implementation common
to all Haltium platform
Signed-off-by: Pasi Liimatainen <pasi.liimatainen@nordicsemi.no>
The function `z_isr_install()` is used during the rtl87x2g SoC init,
necessitating `GEN_ISR_TABLES`.
Enabling this config also correctly causes the `arch.arm.irq_vector_table`
testcase to be filtered out (skipped). This is expected behavior as that
test is intended for configurations without `GEN_ISR_TABLES`.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Integrate support for a minimal driver for IronSide SE IPC which is
thread-unsafe, uses busy waiting, and assumes that the IPC region
is uncached. The driver is included in the IronSide interface code
itself, and is enabled by defining IRONSIDE_SE_CALL_MINIMAL.
This is primarily intended to be used by MCUboot but can be used by
e.g. resource constrained single-threaded firmware.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Add support to the UICR generator image for the new features
in the IronSide support package:
Split blob generation options like GEN_UICR_PERIPHCONF
into GEN_UICR_PERIPHCONF and GEN_UICR_GENERATE_PERIPHCONF to
allow configuring the blob address independently from generating
the blob itself.
Add support for generating a UICR MPCCONF blob by extracting a table of
entries from an image ELF file. The mechanism works mostly the same
as the UICR PERIPHCONF blob generation. When the UICR generator image
finds another image that has CONFIG_NRF_MPCCONF_SECTION=y, it will
extract the data from the section named 'mpcconf_entry' and include it
in build/uicr/zephyr.hex and either build/uicr/mpcconf.hex
or build/uicr/secondary_mpcconf.hex.
Add support to the UICR generator image for setting the
POLICY_MPCCONFSTAGE field via Kconfig. Setting this to INIT is
required to make use of the new ironside_se_mpcconf_write() API
added with IronSide SE v23.4.0+27, which is used to configure
global domain MPCs.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Use the more appropriate KERNEL_DEVICE priority as default for the NPU
instead of KERNEL_DEFAULT. While at it, also clean up the NPU-specific
Kconfig file by using an `if` block to gate symbols.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Set DCACHE_LINE_SIZE and ICACHE_LINE_SIZE configdefaults to 64 bytes
for the APU (Cortex-A) configurations on Versal, Versal2, and
Versalnet SoCs.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Enable CACHE_MANAGEMENT for both RPU and APU configurations
on AMD Versal2 SoC.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
The Kconfig.defconfig file was using incorrect syntax for setting
default configuration values. Lines like "CONFIG_CACHE_MANAGEMENT=y"
are .config/prj.conf fragment syntax, not valid Kconfig language.
This caused the Kconfig parser to silently ignore these lines,
resulting in CACHE_MANAGEMENT not being enabled by default for
VersalNet APU builds.
Fix by using proper Kconfig syntax with "config" block and
"default y" statement. Also remove the duplicate CONFIG_CACHE_MANAGEMENT
line and the redundant ARM_ARCH_TIMER setting which is already enabled
by the top-level Kconfig.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
sys_cache_instr_enable() calls into the Zephyr cache driver
(cache_nrf.c), which is not compiled as part of the TF-M platform
build. When CONFIG_CACHE_MANAGEMENT and CONFIG_ICACHE are both
enabled, this produces an undefined reference at link time.
Use nrf_cache_enable() directly via the nrfx HAL for TF-M builds,
which is already available in the TF-M platform. Zephyr builds are
unaffected and continue to use the driver abstraction.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
- Fix lp_gpio Kconfig dependency to use proper
DT_HAS_ESPRESSIF_ESP32_LPGPIO_ENABLED symbol instead of
SOC_ESP32C6_LPCORE, and separate GPIO_ESP32 from LPGPIO_ESP32
- fix lp_gpio compatible string to espressif,esp32-lpgpio to
match the corrected Kconfig dependency
- enable global LP core interrupts at startup via
ulp_lp_core_intr_enable() in lp_core_startup(); the LP core
has no interrupt allocator so this must be done once for any
peripheral using the single interrupt vector
- enable lp_gpio in gpio_wakeup sample overlay
- fix ESP_CONSOLE_UART_NUM default for LP HP UART console
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
