dts/kconfig: stm32u5: add f9 and clean up dts node locations
Adds skeleton dtsi for u5f9 for u5g9 to inherit from Moves the peripheral nodes into dtsi's that actually has the peripheral and includes them for SoC's higher in the series where applicable. signed-off-by: Harris Tomy <harristomy@gmail.com>
This commit is contained in:
parent
97876b5d1e
commit
d280d89214
31 changed files with 292 additions and 296 deletions
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@ -7,6 +7,7 @@
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/dts-v1/;
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#include <st/u5/stm32u5g9Xj.dtsi>
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#include <st/u5/stm32u5g9zjtxq-pinctrl.dtsi>
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#include <zephyr/dt-bindings/display/panel.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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@ -3,6 +3,7 @@
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2023 PSICONTROL nv
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* Copyright (c) 2024 STMicroelectronics
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* Copyright (c) 2025 Harris Tomy
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -17,7 +18,6 @@
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#include <zephyr/dt-bindings/flash_controller/ospi.h>
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#include <zephyr/dt-bindings/reset/stm32u5_reset.h>
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#include <zephyr/dt-bindings/dma/stm32_dma.h>
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#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
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#include <zephyr/dt-bindings/adc/stm32u5_adc.h>
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#include <zephyr/dt-bindings/power/stm32_pwr.h>
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#include <freq.h>
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@ -253,14 +253,6 @@
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clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
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};
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gpiof: gpio@42021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021400 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
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};
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gpiog: gpio@42021800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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@ -276,14 +268,6 @@
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reg = <0x42021c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
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};
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gpioi: gpio@42022000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42022000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
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};
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};
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iwdg: watchdog@40003000 {
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@ -318,15 +302,6 @@
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
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resets = <&rctl STM32_RESET(APB1L, 17U)>;
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interrupts = <62 0>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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@ -731,28 +706,6 @@
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status = "disabled";
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};
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octospi2: spi@420d2400 {
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compatible = "st,stm32-ospi";
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reg = <0x420d2400 0x400>;
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interrupts = <120 0>;
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clock-names = "ospix", "ospi-ker", "ospi-mgr";
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clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>,
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<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
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<&rcc STM32_CLOCK(AHB2, 21U)>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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aes: aes@420c0000 {
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compatible = "st,stm32-aes";
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reg = <0x420c0000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
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resets = <&rctl STM32_RESET(AHB2L, 16U)>;
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interrupts = <93 0>;
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status = "disabled";
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};
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rng: rng@420c0800 {
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compatible = "st,stm32-rng";
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reg = <0x420c0800 0x400>;
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@ -782,16 +735,6 @@
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status = "disabled";
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};
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sdmmc2: sdmmc@420c8c00 {
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compatible = "st,stm32-sdmmc";
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reg = <0x420c8c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 28U)>,
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<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
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resets = <&rctl STM32_RESET(AHB2L, 28U)>;
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interrupts = <79 0>;
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status = "disabled";
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};
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dac1: dac@46021800 {
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compatible = "st,stm32-dac";
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reg = <0x46021800 0x400>;
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@ -848,14 +791,6 @@
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status = "disabled";
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};
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ucpd1: ucpd@4000dc00 {
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compatible = "st,stm32-ucpd";
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reg = <0x4000dc00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
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interrupts = <106 0>;
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status = "disabled";
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};
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gpdma1: dma@40020000 {
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compatible = "st,stm32u5-dma";
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#dma-cells = <3>;
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@ -869,20 +804,6 @@
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status = "disabled";
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};
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fmc: memory-controller@420d0400 {
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compatible = "st,stm32-fmc";
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reg = <0x420d0400 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2_2, 0U)>;
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status = "disabled";
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sram {
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compatible = "st,stm32-fmc-nor-psram";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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pwr: power@46020800 {
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compatible = "st,stm32-pwr";
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reg = <0x46020800 0x400>; /* PWR register bank */
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@ -4,35 +4,20 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u5.dtsi>
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#include <st/u5/stm32u5_usb_fs.dtsi>
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/ {
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soc {
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/* USB-C PD is not available on this part. */
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/delete-node/ ucpd@4000dc00;
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/* Advanced Encryption Standard HW accelerator is not available on this part. */
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/delete-node/ aes@420c0000;
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compatible = "st,stm32u535", "st,stm32u5", "simple-bus";
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usb: usb@40016000 {
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compatible = "st,stm32-usb";
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reg = <0x40016000 0x400>;
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interrupts = <73 0>;
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interrupt-names = "usb";
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num-bidir-endpoints = <8>;
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ram-size = <2048>;
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maximum-speed = "full-speed";
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clocks = <&rcc STM32_CLOCK(APB2, 24)>,
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<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
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phys = <&usb_fs_phy>;
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status = "disabled";
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};
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 */
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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usb_fs_phy: usb_fs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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sram1: memory@28000000 {
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/* SRAM4, low-power background autonomous mode */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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compatible = "st,stm32u535", "st,stm32u5", "simple-bus";
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};
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};
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@ -8,16 +8,6 @@
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#include <st/u5/stm32u535.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 */
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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sram1: memory@28000000 {
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/* SRAM4, low-power background autonomous mode */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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@ -8,16 +8,6 @@
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#include <st/u5/stm32u535.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 */
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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sram1: memory@28000000 {
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/* SRAM4, low-power background autonomous mode */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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@ -8,16 +8,6 @@
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#include <st/u5/stm32u535.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 */
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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sram1: memory@28000000 {
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/* SRAM4, low-power background autonomous mode */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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@ -4,33 +4,11 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u5.dtsi>
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#include <st/u5/stm32u535.dtsi>
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#include <st/u5/stm32u5_crypt.dtsi>
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/ {
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soc {
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/* USB-C PD is not available on this part. */
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/delete-node/ ucpd@4000dc00;
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compatible = "st,stm32u545", "st,stm32u5", "simple-bus";
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usb: usb@40006000 {
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compatible = "st,stm32-usb";
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reg = <0x40006000 0x400>;
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interrupts = <73 0>;
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interrupt-names = "usb";
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num-bidir-endpoints = <8>;
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ram-size = <1024>;
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maximum-speed = "full-speed";
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status = "disabled";
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clocks = <&rcc STM32_CLOCK(APB2, 24U)>,
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<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
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phys = <&usb_fs_phy>;
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};
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};
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usb_fs_phy: usb_fs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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@ -7,16 +7,6 @@
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#include <st/u5/stm32u545.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 */
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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sram1: memory@28000000 {
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/* SRAM4, low-power background autonomous mode */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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@ -1,33 +1,25 @@
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/*
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2025 Harris Tomy
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u5.dtsi>
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#include <st/u5/stm32u5_usbotg_fs.dtsi>
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#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 + SRAM3 */
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reg = <0x20000000 DT_SIZE_K(768)>;
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};
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sram1: memory@28000000 {
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/* SRAM4, low-power background autonomous mode */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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compatible = "st,stm32u575", "st,stm32u5", "simple-bus";
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usbotg_fs: otgfs@42040000 {
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compatible = "st,stm32-otgfs";
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reg = <0x42040000 0x80000>;
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interrupts = <73 0>;
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interrupt-names = "otgfs";
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num-bidir-endpoints = <6>;
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ram-size = <1280>;
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maximum-speed = "full-speed";
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clocks = <&rcc STM32_CLOCK(AHB2, 14U)>,
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<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
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phys = <&otgfs_phy>;
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status = "disabled";
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};
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};
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otgfs_phy: otgfs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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#include <st/u5/stm32u575.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 + SRAM3 */
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reg = <0x20000000 DT_SIZE_K(768)>;
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};
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sram1: memory@28000000 {
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/* SRAM4, low-power background autonomous mode */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2025 Harris Tomy
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u575.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 + SRAM3 */
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reg = <0x20000000 DT_SIZE_K(768)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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@ -1,10 +1,12 @@
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/*
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2025 Harris Tomy
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u575.dtsi>
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#include <st/u5/stm32u5_crypt.dtsi>
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/ {
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soc {
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2025 Harris Tomy
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u585.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 + SRAM3 */
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reg = <0x20000000 DT_SIZE_K(768)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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@ -1,14 +1,24 @@
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/*
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* Copyright (c) 2023 PSICONTROl nv
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* Copyright (c) 2023 STMicroelectronics
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* Copyright (c) 2025 Harris Tomy
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u5.dtsi>
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#include <st/u5/stm32u5_usbotg_hs.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
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reg = <0x20000000 DT_SIZE_K(2496)>;
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};
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sram1: memory@28000000 {
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/* SRAM4 */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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compatible = "st,stm32u595", "st,stm32u5", "simple-bus";
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st,adc-sequencer = "FULLY_CONFIGURABLE";
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st,adc-oversampler = "OVERSAMPLER_EXTENDED";
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};
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usbotg_hs: otghs@42040000 {
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compatible = "st,stm32-otghs";
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reg = <0x42040000 0x20000>;
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interrupts = <73 0>;
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interrupt-names = "otghs";
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num-bidir-endpoints = <9>;
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ram-size = <4096>;
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maximum-speed = "high-speed";
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clocks = <&rcc STM32_CLOCK(AHB2, 14)>;
|
||||
phys = <&otghs_phy>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
otghs_phy: otghs_phy {
|
||||
compatible = "st,stm32u5-otghs-phy";
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
|
||||
<&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
smbus5: smbus5 {
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2023 PSICONTROL nv
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
@ -9,5 +10,15 @@
|
|||
/ {
|
||||
soc {
|
||||
compatible = "st,stm32u599", "st,stm32u5", "simple-bus";
|
||||
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x40016800 0x400>;
|
||||
interrupts = <135 0>, <136 0>;
|
||||
interrupt-names = "ltdc", "ltdc_er";
|
||||
clocks = <&rcc STM32_CLOCK(APB2, 26)>;
|
||||
resets = <&rctl STM32_RESET(APB2, 26)>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -7,15 +7,6 @@
|
|||
#include <st/u5/stm32u599.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
|
||||
reg = <0x20000000 DT_SIZE_K(2496)>;
|
||||
};
|
||||
sram1: memory@28000000 {
|
||||
/* SRAM4 */
|
||||
reg = <0x28000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2023 PSICONTROL nv
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
@ -7,15 +8,6 @@
|
|||
#include <st/u5/stm32u599.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
|
||||
reg = <0x20000000 DT_SIZE_K(2496)>;
|
||||
};
|
||||
sram1: memory@28000000 {
|
||||
/* SRAM4 */
|
||||
reg = <0x28000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
|
|
18
dts/arm/st/u5/stm32u5_crypt.dtsi
Normal file
18
dts/arm/st/u5/stm32u5_crypt.dtsi
Normal file
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
aes: aes@420c0000 {
|
||||
compatible = "st,stm32-aes";
|
||||
reg = <0x420c0000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
|
||||
resets = <&rctl STM32_RESET(AHB2L, 16)>;
|
||||
interrupts = <93 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
79
dts/arm/st/u5/stm32u5_extra.dtsi
Normal file
79
dts/arm/st/u5/stm32u5_extra.dtsi
Normal file
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 17)>;
|
||||
interrupts = <62 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiof: gpio@42021400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x42021400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 5)>;
|
||||
};
|
||||
|
||||
gpioi: gpio@42022000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x42022000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 8)>;
|
||||
};
|
||||
|
||||
sdmmc2: sdmmc@420c8c00 {
|
||||
compatible = "st,stm32-sdmmc";
|
||||
reg = <0x420c8c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 28)>,
|
||||
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
|
||||
resets = <&rctl STM32_RESET(AHB2L, 28)>;
|
||||
interrupts = <79 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fmc: memory-controller@420d0400 {
|
||||
compatible = "st,stm32-fmc";
|
||||
reg = <0x420d0400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2_2, 0)>;
|
||||
status = "disabled";
|
||||
|
||||
sram {
|
||||
compatible = "st,stm32-fmc-nor-psram";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
octospi2: spi@420d2400 {
|
||||
compatible = "st,stm32-ospi";
|
||||
reg = <0x420d2400 0x400>;
|
||||
interrupts = <120 0>;
|
||||
clock-names = "ospix", "ospi-ker", "ospi-mgr";
|
||||
clocks = <&rcc STM32_CLOCK(AHB2_2, 8)>,
|
||||
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
|
||||
<&rcc STM32_CLOCK(AHB2, 21)>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ucpd1: ucpd@4000dc00 {
|
||||
compatible = "st,stm32-ucpd";
|
||||
reg = <0x4000dc00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
|
||||
interrupts = <106 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
30
dts/arm/st/u5/stm32u5_usb_fs.dtsi
Normal file
30
dts/arm/st/u5/stm32u5_usb_fs.dtsi
Normal file
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/u5/stm32u5.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
usb: usb@40016000 {
|
||||
compatible = "st,stm32-usb";
|
||||
reg = <0x40016000 0x400>;
|
||||
interrupts = <73 0>;
|
||||
interrupt-names = "usb";
|
||||
num-bidir-endpoints = <8>;
|
||||
ram-size = <2048>;
|
||||
maximum-speed = "full-speed";
|
||||
clocks = <&rcc STM32_CLOCK(APB2, 24)>,
|
||||
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
|
||||
phys = <&usb_fs_phy>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usb_fs_phy: usb_fs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
31
dts/arm/st/u5/stm32u5_usbotg_fs.dtsi
Normal file
31
dts/arm/st/u5/stm32u5_usbotg_fs.dtsi
Normal file
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/u5/stm32u5.dtsi>
|
||||
#include <st/u5/stm32u5_extra.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
usbotg_fs: otgfs@42040000 {
|
||||
compatible = "st,stm32-otgfs";
|
||||
reg = <0x42040000 0x80000>;
|
||||
interrupts = <73 0>;
|
||||
interrupt-names = "otgfs";
|
||||
num-bidir-endpoints = <6>;
|
||||
ram-size = <1280>;
|
||||
maximum-speed = "full-speed";
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 14)>,
|
||||
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
|
||||
phys = <&otgfs_phy>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
otgfs_phy: otgfs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
32
dts/arm/st/u5/stm32u5_usbotg_hs.dtsi
Normal file
32
dts/arm/st/u5/stm32u5_usbotg_hs.dtsi
Normal file
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/u5/stm32u5.dtsi>
|
||||
#include <st/u5/stm32u5_extra.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
usbotg_hs: otghs@42040000 {
|
||||
compatible = "st,stm32-otghs";
|
||||
reg = <0x42040000 0x20000>;
|
||||
interrupts = <73 0>;
|
||||
interrupt-names = "otghs";
|
||||
num-bidir-endpoints = <9>;
|
||||
ram-size = <4096>;
|
||||
maximum-speed = "high-speed";
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 14)>;
|
||||
phys = <&otghs_phy>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
otghs_phy: otghs_phy {
|
||||
compatible = "st,stm32u5-otghs-phy";
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 15)>,
|
||||
<&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
|
@ -1,10 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2023 STMicroelectronics
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/u5/stm32u595.dtsi>
|
||||
#include <st/u5/stm32u5_crypt.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2023 STMicroelectronics
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
@ -8,15 +9,6 @@
|
|||
#include <st/u5/stm32u5a5.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
|
||||
reg = <0x20000000 DT_SIZE_K(2496)>;
|
||||
};
|
||||
sram1: memory@28000000 {
|
||||
/* SRAM4 */
|
||||
reg = <0x28000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
|
|
|
@ -1,10 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2023 STMicroelectronics
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/u5/stm32u595.dtsi>
|
||||
#include <st/u5/stm32u599.dtsi>
|
||||
#include <st/u5/stm32u5_crypt.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2023 STMicroelectronics
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
@ -8,16 +9,6 @@
|
|||
#include <st/u5/stm32u5a9.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
|
||||
/* 768K + 64K + 832K + 832K */
|
||||
reg = <0x20000000 DT_SIZE_K(2496)>;
|
||||
};
|
||||
sram1: memory@28000000 {
|
||||
/* SRAM4, low-power background autonomous mode */
|
||||
reg = <0x28000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
|
|
19
dts/arm/st/u5/stm32u5f9.dtsi
Normal file
19
dts/arm/st/u5/stm32u5f9.dtsi
Normal file
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/u5/stm32u599.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
compatible = "st,stm32u5f9", "st,stm32u5", "simple-bus";
|
||||
};
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 + SRAM6 */
|
||||
/* 768K + 64K + 832K + 832K + 512K */
|
||||
reg = <0x20000000 DT_SIZE_K(3008)>;
|
||||
};
|
|
@ -1,26 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Charles Dias
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/u5/stm32u595.dtsi>
|
||||
#include <zephyr/dt-bindings/display/panel.h>
|
||||
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
|
||||
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
|
||||
#include <st/u5/stm32u5f9.dtsi>
|
||||
#include <st/u5/stm32u5_crypt.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
compatible = "st,stm32u5g9", "st,stm32u5", "simple-bus";
|
||||
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x40016800 0x400>;
|
||||
interrupts = <135 0>, <136 0>;
|
||||
interrupt-names = "ltdc", "ltdc_er";
|
||||
clocks = <&rcc STM32_CLOCK(APB2, 26)>;
|
||||
resets = <&rctl STM32_RESET(APB2, 26)>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Charles Dias
|
||||
* Copyright (c) 2025 Harris Tomy
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
@ -8,17 +9,6 @@
|
|||
#include <st/u5/stm32u5g9.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 + SRAM6 */
|
||||
/* 768K + 64K + 832K + 832K + 512K */
|
||||
reg = <0x20000000 DT_SIZE_K(3008)>;
|
||||
};
|
||||
|
||||
sram4: memory@28000000 {
|
||||
/* SRAM4, low-power background autonomous mode */
|
||||
reg = <0x28000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
|
|
11
soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5f9xx
Normal file
11
soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5f9xx
Normal file
|
@ -0,0 +1,11 @@
|
|||
# STMicroelectronics STM32U5GFXX MCU
|
||||
|
||||
# Copyright (c) 2025 Harris Tomy
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_STM32U5F9XX
|
||||
|
||||
config NUM_IRQS
|
||||
default 141
|
||||
|
||||
endif # SOC_STM32U5F9XX
|
|
@ -46,6 +46,10 @@ config SOC_STM32U5A9XX
|
|||
bool
|
||||
select SOC_SERIES_STM32U5X
|
||||
|
||||
config SOC_STM32U5F9XX
|
||||
bool
|
||||
select SOC_SERIES_STM32U5X
|
||||
|
||||
config SOC_STM32U5G9XX
|
||||
bool
|
||||
select SOC_SERIES_STM32U5X
|
||||
|
@ -53,6 +57,7 @@ config SOC_STM32U5G9XX
|
|||
config SOC
|
||||
default "stm32u5a5xx" if SOC_STM32U5A5XX
|
||||
default "stm32u5a9xx" if SOC_STM32U5A9XX
|
||||
default "stm32u5f9xx" if SOC_STM32U5F9XX
|
||||
default "stm32u5g9xx" if SOC_STM32U5G9XX
|
||||
default "stm32u535xx" if SOC_STM32U535XX
|
||||
default "stm32u545xx" if SOC_STM32U545XX
|
||||
|
|
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