dts/kconfig: stm32u5: add f9 and clean up dts node locations

Adds skeleton dtsi for u5f9 for u5g9 to inherit from

Moves the peripheral nodes into dtsi's that actually has the peripheral
and includes them for SoC's higher in the series where applicable.

signed-off-by: Harris Tomy <harristomy@gmail.com>
This commit is contained in:
Harris Tomy 2025-06-04 08:08:20 +00:00 committed by Dan Kalowsky
commit d280d89214
31 changed files with 292 additions and 296 deletions

View file

@ -7,6 +7,7 @@
/dts-v1/;
#include <st/u5/stm32u5g9Xj.dtsi>
#include <st/u5/stm32u5g9zjtxq-pinctrl.dtsi>
#include <zephyr/dt-bindings/display/panel.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {

View file

@ -3,6 +3,7 @@
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 PSICONTROL nv
* Copyright (c) 2024 STMicroelectronics
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -17,7 +18,6 @@
#include <zephyr/dt-bindings/flash_controller/ospi.h>
#include <zephyr/dt-bindings/reset/stm32u5_reset.h>
#include <zephyr/dt-bindings/dma/stm32_dma.h>
#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
#include <zephyr/dt-bindings/adc/stm32u5_adc.h>
#include <zephyr/dt-bindings/power/stm32_pwr.h>
#include <freq.h>
@ -253,14 +253,6 @@
clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
};
gpiof: gpio@42021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42021400 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
};
gpiog: gpio@42021800 {
compatible = "st,stm32-gpio";
gpio-controller;
@ -276,14 +268,6 @@
reg = <0x42021c00 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
};
gpioi: gpio@42022000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42022000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
};
};
iwdg: watchdog@40003000 {
@ -318,15 +302,6 @@
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <62 0>;
status = "disabled";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
@ -731,28 +706,6 @@
status = "disabled";
};
octospi2: spi@420d2400 {
compatible = "st,stm32-ospi";
reg = <0x420d2400 0x400>;
interrupts = <120 0>;
clock-names = "ospix", "ospi-ker", "ospi-mgr";
clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>,
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
<&rcc STM32_CLOCK(AHB2, 21U)>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
aes: aes@420c0000 {
compatible = "st,stm32-aes";
reg = <0x420c0000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
resets = <&rctl STM32_RESET(AHB2L, 16U)>;
interrupts = <93 0>;
status = "disabled";
};
rng: rng@420c0800 {
compatible = "st,stm32-rng";
reg = <0x420c0800 0x400>;
@ -782,16 +735,6 @@
status = "disabled";
};
sdmmc2: sdmmc@420c8c00 {
compatible = "st,stm32-sdmmc";
reg = <0x420c8c00 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 28U)>,
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
resets = <&rctl STM32_RESET(AHB2L, 28U)>;
interrupts = <79 0>;
status = "disabled";
};
dac1: dac@46021800 {
compatible = "st,stm32-dac";
reg = <0x46021800 0x400>;
@ -848,14 +791,6 @@
status = "disabled";
};
ucpd1: ucpd@4000dc00 {
compatible = "st,stm32-ucpd";
reg = <0x4000dc00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
interrupts = <106 0>;
status = "disabled";
};
gpdma1: dma@40020000 {
compatible = "st,stm32u5-dma";
#dma-cells = <3>;
@ -869,20 +804,6 @@
status = "disabled";
};
fmc: memory-controller@420d0400 {
compatible = "st,stm32-fmc";
reg = <0x420d0400 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2_2, 0U)>;
status = "disabled";
sram {
compatible = "st,stm32-fmc-nor-psram";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
pwr: power@46020800 {
compatible = "st,stm32-pwr";
reg = <0x46020800 0x400>; /* PWR register bank */

View file

@ -4,35 +4,20 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u5.dtsi>
#include <st/u5/stm32u5_usb_fs.dtsi>
/ {
soc {
/* USB-C PD is not available on this part. */
/delete-node/ ucpd@4000dc00;
/* Advanced Encryption Standard HW accelerator is not available on this part. */
/delete-node/ aes@420c0000;
compatible = "st,stm32u535", "st,stm32u5", "simple-bus";
usb: usb@40016000 {
compatible = "st,stm32-usb";
reg = <0x40016000 0x400>;
interrupts = <73 0>;
interrupt-names = "usb";
num-bidir-endpoints = <8>;
ram-size = <2048>;
maximum-speed = "full-speed";
clocks = <&rcc STM32_CLOCK(APB2, 24)>,
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
phys = <&usb_fs_phy>;
status = "disabled";
};
sram0: memory@20000000 {
/* SRAM1 + SRAM2 */
reg = <0x20000000 DT_SIZE_K(256)>;
};
usb_fs_phy: usb_fs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
sram1: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
compatible = "st,stm32u535", "st,stm32u5", "simple-bus";
};
};

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@ -8,16 +8,6 @@
#include <st/u5/stm32u535.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 */
reg = <0x20000000 DT_SIZE_K(256)>;
};
sram1: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

View file

@ -8,16 +8,6 @@
#include <st/u5/stm32u535.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 */
reg = <0x20000000 DT_SIZE_K(256)>;
};
sram1: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

View file

@ -8,16 +8,6 @@
#include <st/u5/stm32u535.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 */
reg = <0x20000000 DT_SIZE_K(256)>;
};
sram1: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -4,33 +4,11 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u5.dtsi>
#include <st/u5/stm32u535.dtsi>
#include <st/u5/stm32u5_crypt.dtsi>
/ {
soc {
/* USB-C PD is not available on this part. */
/delete-node/ ucpd@4000dc00;
compatible = "st,stm32u545", "st,stm32u5", "simple-bus";
usb: usb@40006000 {
compatible = "st,stm32-usb";
reg = <0x40006000 0x400>;
interrupts = <73 0>;
interrupt-names = "usb";
num-bidir-endpoints = <8>;
ram-size = <1024>;
maximum-speed = "full-speed";
status = "disabled";
clocks = <&rcc STM32_CLOCK(APB2, 24U)>,
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
phys = <&usb_fs_phy>;
};
};
usb_fs_phy: usb_fs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};

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@ -7,16 +7,6 @@
#include <st/u5/stm32u545.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 */
reg = <0x20000000 DT_SIZE_K(256)>;
};
sram1: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -1,33 +1,25 @@
/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u5.dtsi>
#include <st/u5/stm32u5_usbotg_fs.dtsi>
#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 */
reg = <0x20000000 DT_SIZE_K(768)>;
};
sram1: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
compatible = "st,stm32u575", "st,stm32u5", "simple-bus";
usbotg_fs: otgfs@42040000 {
compatible = "st,stm32-otgfs";
reg = <0x42040000 0x80000>;
interrupts = <73 0>;
interrupt-names = "otgfs";
num-bidir-endpoints = <6>;
ram-size = <1280>;
maximum-speed = "full-speed";
clocks = <&rcc STM32_CLOCK(AHB2, 14U)>,
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
phys = <&otgfs_phy>;
status = "disabled";
};
};
otgfs_phy: otgfs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};

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@ -7,16 +7,6 @@
#include <st/u5/stm32u575.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 */
reg = <0x20000000 DT_SIZE_K(768)>;
};
sram1: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,11 +8,6 @@
#include <st/u5/stm32u575.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 */
reg = <0x20000000 DT_SIZE_K(768)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -1,10 +1,12 @@
/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u575.dtsi>
#include <st/u5/stm32u5_crypt.dtsi>
/ {
soc {

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@ -1,5 +1,6 @@
/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,11 +8,6 @@
#include <st/u5/stm32u585.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 */
reg = <0x20000000 DT_SIZE_K(768)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -1,14 +1,24 @@
/*
* Copyright (c) 2023 PSICONTROl nv
* Copyright (c) 2023 STMicroelectronics
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u5.dtsi>
#include <st/u5/stm32u5_usbotg_hs.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
reg = <0x20000000 DT_SIZE_K(2496)>;
};
sram1: memory@28000000 {
/* SRAM4 */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
compatible = "st,stm32u595", "st,stm32u5", "simple-bus";
@ -99,26 +109,6 @@
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
};
usbotg_hs: otghs@42040000 {
compatible = "st,stm32-otghs";
reg = <0x42040000 0x20000>;
interrupts = <73 0>;
interrupt-names = "otghs";
num-bidir-endpoints = <9>;
ram-size = <4096>;
maximum-speed = "high-speed";
clocks = <&rcc STM32_CLOCK(AHB2, 14)>;
phys = <&otghs_phy>;
status = "disabled";
};
};
otghs_phy: otghs_phy {
compatible = "st,stm32u5-otghs-phy";
clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
<&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
#phy-cells = <0>;
};
smbus5: smbus5 {

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@ -1,5 +1,6 @@
/*
* Copyright (c) 2023 PSICONTROL nv
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,5 +10,15 @@
/ {
soc {
compatible = "st,stm32u599", "st,stm32u5", "simple-bus";
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x400>;
interrupts = <135 0>, <136 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK(APB2, 26)>;
resets = <&rctl STM32_RESET(APB2, 26)>;
status = "disabled";
};
};
};

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@ -7,15 +7,6 @@
#include <st/u5/stm32u599.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
reg = <0x20000000 DT_SIZE_K(2496)>;
};
sram1: memory@28000000 {
/* SRAM4 */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -1,5 +1,6 @@
/*
* Copyright (c) 2023 PSICONTROL nv
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,15 +8,6 @@
#include <st/u5/stm32u599.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
reg = <0x20000000 DT_SIZE_K(2496)>;
};
sram1: memory@28000000 {
/* SRAM4 */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -0,0 +1,18 @@
/*
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
aes: aes@420c0000 {
compatible = "st,stm32-aes";
reg = <0x420c0000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
resets = <&rctl STM32_RESET(AHB2L, 16)>;
interrupts = <93 0>;
status = "disabled";
};
};
};

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@ -0,0 +1,79 @@
/*
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
resets = <&rctl STM32_RESET(APB1L, 17)>;
interrupts = <62 0>;
status = "disabled";
};
gpiof: gpio@42021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42021400 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 5)>;
};
gpioi: gpio@42022000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42022000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 8)>;
};
sdmmc2: sdmmc@420c8c00 {
compatible = "st,stm32-sdmmc";
reg = <0x420c8c00 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 28)>,
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
resets = <&rctl STM32_RESET(AHB2L, 28)>;
interrupts = <79 0>;
status = "disabled";
};
fmc: memory-controller@420d0400 {
compatible = "st,stm32-fmc";
reg = <0x420d0400 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2_2, 0)>;
status = "disabled";
sram {
compatible = "st,stm32-fmc-nor-psram";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
octospi2: spi@420d2400 {
compatible = "st,stm32-ospi";
reg = <0x420d2400 0x400>;
interrupts = <120 0>;
clock-names = "ospix", "ospi-ker", "ospi-mgr";
clocks = <&rcc STM32_CLOCK(AHB2_2, 8)>,
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
<&rcc STM32_CLOCK(AHB2, 21)>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
ucpd1: ucpd@4000dc00 {
compatible = "st,stm32-ucpd";
reg = <0x4000dc00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
interrupts = <106 0>;
status = "disabled";
};
};
};

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@ -0,0 +1,30 @@
/*
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u5.dtsi>
/ {
soc {
usb: usb@40016000 {
compatible = "st,stm32-usb";
reg = <0x40016000 0x400>;
interrupts = <73 0>;
interrupt-names = "usb";
num-bidir-endpoints = <8>;
ram-size = <2048>;
maximum-speed = "full-speed";
clocks = <&rcc STM32_CLOCK(APB2, 24)>,
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
phys = <&usb_fs_phy>;
status = "disabled";
};
};
usb_fs_phy: usb_fs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};

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@ -0,0 +1,31 @@
/*
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u5.dtsi>
#include <st/u5/stm32u5_extra.dtsi>
/ {
soc {
usbotg_fs: otgfs@42040000 {
compatible = "st,stm32-otgfs";
reg = <0x42040000 0x80000>;
interrupts = <73 0>;
interrupt-names = "otgfs";
num-bidir-endpoints = <6>;
ram-size = <1280>;
maximum-speed = "full-speed";
clocks = <&rcc STM32_CLOCK(AHB2, 14)>,
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
phys = <&otgfs_phy>;
status = "disabled";
};
};
otgfs_phy: otgfs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};

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@ -0,0 +1,32 @@
/*
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u5.dtsi>
#include <st/u5/stm32u5_extra.dtsi>
/ {
soc {
usbotg_hs: otghs@42040000 {
compatible = "st,stm32-otghs";
reg = <0x42040000 0x20000>;
interrupts = <73 0>;
interrupt-names = "otghs";
num-bidir-endpoints = <9>;
ram-size = <4096>;
maximum-speed = "high-speed";
clocks = <&rcc STM32_CLOCK(AHB2, 14)>;
phys = <&otghs_phy>;
status = "disabled";
};
};
otghs_phy: otghs_phy {
compatible = "st,stm32u5-otghs-phy";
clocks = <&rcc STM32_CLOCK(AHB2, 15)>,
<&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
#phy-cells = <0>;
};
};

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@ -1,10 +1,12 @@
/*
* Copyright (c) 2023 STMicroelectronics
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u595.dtsi>
#include <st/u5/stm32u5_crypt.dtsi>
/ {
soc {

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@ -1,5 +1,6 @@
/*
* Copyright (c) 2023 STMicroelectronics
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,15 +9,6 @@
#include <st/u5/stm32u5a5.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
reg = <0x20000000 DT_SIZE_K(2496)>;
};
sram1: memory@28000000 {
/* SRAM4 */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -1,10 +1,12 @@
/*
* Copyright (c) 2023 STMicroelectronics
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u595.dtsi>
#include <st/u5/stm32u599.dtsi>
#include <st/u5/stm32u5_crypt.dtsi>
/ {
soc {

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@ -1,5 +1,6 @@
/*
* Copyright (c) 2023 STMicroelectronics
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,16 +9,6 @@
#include <st/u5/stm32u5a9.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
/* 768K + 64K + 832K + 832K */
reg = <0x20000000 DT_SIZE_K(2496)>;
};
sram1: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -0,0 +1,19 @@
/*
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u599.dtsi>
/ {
soc {
compatible = "st,stm32u5f9", "st,stm32u5", "simple-bus";
};
};
&sram0 {
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 + SRAM6 */
/* 768K + 64K + 832K + 832K + 512K */
reg = <0x20000000 DT_SIZE_K(3008)>;
};

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@ -1,26 +1,15 @@
/*
* Copyright (c) 2025 Charles Dias
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u595.dtsi>
#include <zephyr/dt-bindings/display/panel.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#include <st/u5/stm32u5f9.dtsi>
#include <st/u5/stm32u5_crypt.dtsi>
/ {
soc {
compatible = "st,stm32u5g9", "st,stm32u5", "simple-bus";
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x400>;
interrupts = <135 0>, <136 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK(APB2, 26)>;
resets = <&rctl STM32_RESET(APB2, 26)>;
status = "disabled";
};
};
};

View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2025 Charles Dias
* Copyright (c) 2025 Harris Tomy
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,17 +9,6 @@
#include <st/u5/stm32u5g9.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 + SRAM6 */
/* 768K + 64K + 832K + 832K + 512K */
reg = <0x20000000 DT_SIZE_K(3008)>;
};
sram4: memory@28000000 {
/* SRAM4, low-power background autonomous mode */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {

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@ -0,0 +1,11 @@
# STMicroelectronics STM32U5GFXX MCU
# Copyright (c) 2025 Harris Tomy
# SPDX-License-Identifier: Apache-2.0
if SOC_STM32U5F9XX
config NUM_IRQS
default 141
endif # SOC_STM32U5F9XX

View file

@ -46,6 +46,10 @@ config SOC_STM32U5A9XX
bool
select SOC_SERIES_STM32U5X
config SOC_STM32U5F9XX
bool
select SOC_SERIES_STM32U5X
config SOC_STM32U5G9XX
bool
select SOC_SERIES_STM32U5X
@ -53,6 +57,7 @@ config SOC_STM32U5G9XX
config SOC
default "stm32u5a5xx" if SOC_STM32U5A5XX
default "stm32u5a9xx" if SOC_STM32U5A9XX
default "stm32u5f9xx" if SOC_STM32U5F9XX
default "stm32u5g9xx" if SOC_STM32U5G9XX
default "stm32u535xx" if SOC_STM32U535XX
default "stm32u545xx" if SOC_STM32U545XX