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boards: nxp: add uhc support for frdm_k22f, rt1060, lpc55s69 and lpc55s28

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add uhc related items to dts.
add clock initialization
add BM4 if CONFIG_USB_UHC_NXP_KHCI is enabled
add pin mux
update board related CMakeLists.txt
update sdk-ng CMake to include NXP controller drivers
update west.yml to contain the hal_nxp pr

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
This commit is contained in:
Mark Wang 2024-09-02 22:09:54 +08:00 • committed by Benjamin Cabé
commit a8796ca6ee
23 changed files with 274 additions and 15 deletions
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4
boards/nxp/frdm_k22f/frdm_k22f.dts
View file

@ -178,6 +178,10 @@ zephyr_udc0: &usbotg {
num-bidir-endpoints = <8>;
};
zephyr_uhc0: &usbh {
status = "okay";
};
&gpioa {
status = "okay";
};

18
boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi
View file

@ -46,4 +46,22 @@
};
};
pinmux_usbhfs: pinmux_usbhfs {
group0 {
pinmux = <USB0_VBUS_PIO0_22>,
<USB0_OVERCURRENTN_PIO0_28>,
<USB0_PORTPWRN_PIO1_12>;
bias-pull-up;
slew-rate = "standard";
};
};
pinmux_usbhhs: pinmux_usbhhs {
group0 {
pinmux = <USB1_OVERCURRENTN_PIO1_30>,
<USB1_PORTPWRN_PIO1_29>;
bias-pull-up;
slew-rate = "standard";
};
};
};

20
boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts
View file

@ -127,3 +127,23 @@
zephyr_udc0: &usbhs {
status = "okay";
};
zephyr_uhc0: &usbhfs {
pinctrl-0 = <&pinmux_usbhfs>;
pinctrl-names = "default";
status = "okay";
};
zephyr_uhc1: &usbhhs {
pinctrl-0 = <&pinmux_usbhhs>;
pinctrl-names = "default";
status = "okay";
phy_handle = <&usbphy1>;
};
&usbphy1 {
status = "okay";
tx-d-cal = <5>;
tx-cal-45-dp-ohms = <10>;
tx-cal-45-dm-ohms = <10>;
};

21
boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi
View file

@ -2,7 +2,7 @@
* NOTE: File generated by gen_board_pinctrl.py
* from LPCXpresso55S69.mex
*
* Copyright 2022 NXP
* Copyright 2022,2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
@ -108,4 +108,23 @@
slew-rate = "standard";
};
};
pinmux_usbhfs: pinmux_usbhfs {
group0 {
pinmux = <USB0_VBUS_PIO0_22>,
<USB0_OVERCURRENTN_PIO0_28>,
<USB0_PORTPWRN_PIO1_12>;
bias-pull-up;
slew-rate = "standard";
};
};
pinmux_usbhhs: pinmux_usbhhs {
group0 {
pinmux = <USB1_OVERCURRENTN_PIO1_30>,
<USB1_PORTPWRN_PIO1_29>;
bias-pull-up;
slew-rate = "standard";
};
};
};

13
boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts
View file

@ -155,6 +155,19 @@ zephyr_udc0: &usbhs {
phy-handle = <&usbphy1>;
};
zephyr_uhc0: &usbhfs {
pinctrl-0 = <&pinmux_usbhfs>;
pinctrl-names = "default";
status = "okay";
};
zephyr_uhc1: &usbhhs {
pinctrl-0 = <&pinmux_usbhhs>;
pinctrl-names = "default";
status = "okay";
phy_handle = <&usbphy1>;
};
&usbphy1 {
status = "okay";
tx-d-cal = <5>;

17
boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi
View file

@ -188,6 +188,16 @@ zephyr_udc0: &usb1 {
phy-handle = <&usbphy1>;
};
zephyr_uhc0: &usbh1 {
status = "okay";
phy_handle = <&usbphy1>;
};
zephyr_uhc1: &usbh2 {
status = "okay";
phy_handle = <&usbphy2>;
};
&usbphy1 {
status = "okay";
tx-d-cal = <12>;
@ -195,6 +205,13 @@ zephyr_udc0: &usb1 {
tx-cal-45-dm-ohms = <6>;
};
&usbphy2 {
status = "okay";
tx-d-cal = <12>;
tx-cal-45-dp-ohms = <6>;
tx-cal-45-dm-ohms = <6>;
};
&csi {
pinctrl-0 = <&pinmux_csi>;
pinctrl-names = "default";

9
dts/arm/nxp/nxp_k2x.dtsi
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2018 Prevas A/S
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -375,6 +376,14 @@
status = "disabled";
};
usbh: usbh@40072000 {
compatible = "nxp,uhc-khci";
reg = <0x40072000 0x1000>;
interrupts = <53 1>;
interrupt-names = "usb_otg";
status = "disabled";
};
rnga: random@40029000 {
compatible = "nxp,kinetis-rnga";
reg = <0x40029000 0x1000>;

21
dts/arm/nxp/nxp_lpc55S2x_common.dtsi
View file

@ -320,6 +320,27 @@
num-bidir-endpoints = <6>;
status = "disabled";
};
usbhfs: usbhfs@A2000 {
compatible = "nxp,uhc-ohci";
reg = <0xa2000 0x1000>;
interrupts = <28 1>;
maximum-speed = "full-speed";
status = "disabled";
};
usbhhs: usbhhs@A3000 {
compatible = "nxp,uhc-ip3516hs";
reg = <0xa3000 0x1000>;
interrupts = <47 1>;
status = "disabled";
};
usbphy1: usbphy@38000 {
compatible = "nxp,usbphy";
reg = <0x38000 0x1000>;
status = "disabled";
};
};
&nvic {

15
dts/arm/nxp/nxp_lpc55S6x_common.dtsi
View file

@ -390,6 +390,21 @@
status = "disabled";
};
usbhfs: usbhfs@A2000 {
compatible = "nxp,uhc-ohci";
reg = <0xa2000 0x1000>;
interrupts = <28 1>;
maximum-speed = "full-speed";
status = "disabled";
};
usbhhs: usbhhs@A3000 {
compatible = "nxp,uhc-ip3516hs";
reg = <0xa3000 0x1000>;
interrupts = <47 1>;
status = "disabled";
};
usbphy1: usbphy@38000 {
compatible = "nxp,usbphy";
reg = <0x38000 0x1000>;

20
dts/arm/nxp/nxp_rt10xx.dtsi
View file

@ -1,5 +1,5 @@
/*
* Copyright 2017,2023 NXP
* Copyright 2017,2023,2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -846,6 +846,24 @@
status = "disabled";
};
usbh1: usbh@402e0000 {
compatible = "nxp,uhc-ehci";
reg = <0x402E0000 0x200>;
interrupts = <113 1>;
interrupt-names = "usb_otg";
clocks = <&usbclk>;
status = "disabled";
};
usbh2: usbh@402e0200 {
compatible = "nxp,uhc-ehci";
reg = <0x402E0200 0x200>;
interrupts = <112 1>;
interrupt-names = "usb_otg";
clocks = <&usbclk>;
status = "disabled";
};
usbphy1: usbphy@400d9000 {
compatible = "nxp,usbphy";
reg = <0x400D9000 0x1000>;

12
dts/bindings/usb/nxp,uhc-ehci.yaml Normal file
View file

@ -0,0 +1,12 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: NXP EHCI USB host controller
compatible: "nxp,uhc-ehci"
include: [usb-controller.yaml]
properties:
phy_handle:
type: phandle

12
dts/bindings/usb/nxp,uhc-ip3516hs.yaml Normal file
View file

@ -0,0 +1,12 @@
# # Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: NXP IP3516HS USB host controller
compatible: "nxp,uhc-ip3516hs"
include: [usb-controller.yaml, pinctrl-device.yaml]
properties:
phy_handle:
type: phandle

8
dts/bindings/usb/nxp,uhc-khci.yaml Normal file
View file

@ -0,0 +1,8 @@
# # Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: NXP KHCI USB host controller
compatible: "nxp,uhc-khci"
include: [usb-controller.yaml]

8
dts/bindings/usb/nxp,uhc-ohci.yaml Normal file
View file

@ -0,0 +1,8 @@
# # Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: NXP OHCI USB host controller
compatible: "nxp,uhc-ohci"
include: [usb-controller.yaml, pinctrl-device.yaml]

2
include/zephyr/arch/arm/mpu/nxp_mpu.h
View file

@ -34,7 +34,7 @@
#define BM4_WE_SHIFT 24
#define BM4_RE_SHIFT 25
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS || CONFIG_UHC_NXP_KHCI
#define BM4_PERMISSIONS ((1 << BM4_RE_SHIFT) | (1 << BM4_WE_SHIFT))
#else
#define BM4_PERMISSIONS 0

2
modules/hal_nxp/mcux/mcux-sdk-ng/components/components.cmake
View file

@ -20,7 +20,7 @@ if(${MCUX_DEVICE} MATCHES "RW61")
endif()
endif()
if(CONFIG_USB_DEVICE_DRIVER OR CONFIG_UDC_DRIVER OR CONFIG_BT)
if(CONFIG_USB_DEVICE_DRIVER OR CONFIG_UDC_DRIVER OR CONFIG_UHC_DRIVER OR CONFIG_BT)
set(CONFIG_USE_component_osa_zephyr ON)
endif()

16
modules/hal_nxp/mcux/mcux-sdk-ng/middleware/middleware.cmake
View file

@ -36,6 +36,22 @@ if(CONFIG_UDC_DRIVER)
zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/include)
endif()
if (CONFIG_UHC_DRIVER)
zephyr_include_directories(middleware)
set(CONFIG_MCUX_COMPONENT_middleware.usb.common_header ON)
set_variable_ifdef(CONFIG_DT_HAS_NXP_USBPHY_ENABLED CONFIG_MCUX_COMPONENT_middleware.usb.phy)
set_variable_ifdef(CONFIG_UHC_NXP_EHCI CONFIG_MCUX_COMPONENT_middleware.usb.host.ehci)
set_variable_ifdef(CONFIG_UHC_NXP_KHCI CONFIG_MCUX_COMPONENT_middleware.usb.host.khci)
set_variable_ifdef(CONFIG_UHC_NXP_OHCI CONFIG_MCUX_COMPONENT_middleware.usb.host.ohci)
set_variable_ifdef(CONFIG_UHC_NXP_IP3516HS CONFIG_MCUX_COMPONENT_middleware.usb.host.ip3516hs)
# For soc.c build pass
zephyr_include_directories(.)
zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/phy)
zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/include)
endif()
add_subdirectory(${MCUX_SDK_NG_DIR}/middleware/usb
${CMAKE_CURRENT_BINARY_DIR}/usb
)

12
soc/nxp/imxrt/imxrt10xx/soc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2017-2023 NXP
* Copyright 2017-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -245,8 +245,9 @@ __weak void clock_init(void)
kIOMUXC_GPR_ENET2RefClkMode, true);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
#if ((DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)) ||\
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbh1)) && (CONFIG_UHC_NXP_EHCI)))
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
@ -256,8 +257,9 @@ __weak void clock_init(void)
#endif
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
#if ((DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)) ||\
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbh2)) && (CONFIG_UHC_NXP_EHCI)))
CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M,

3
soc/nxp/imxrt/imxrt6xx/cm33/CMakeLists.txt
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2020, NXP
# Copyright (c) 2020,2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
@ -19,6 +19,7 @@ zephyr_library_include_directories(
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UHC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM)

3
soc/nxp/kinetis/k2x/soc.c
View file

@ -3,6 +3,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2018 Prevas A/S
* Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -102,7 +103,7 @@ __weak void clock_init(void)
CLOCK_SetSimConfig(&simConfig);
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS || CONFIG_UHC_NXP_KHCI
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
#endif

5
soc/nxp/lpc/lpc55xxx/CMakeLists.txt
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2019, NXP
# Copyright (c) 2019,2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
@ -16,9 +16,12 @@ zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
SECTIONS usb.ld)
zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER
SECTIONS usb.ld)
zephyr_linker_sources_ifdef(CONFIG_UHC_DRIVER
SECTIONS usb.ld)
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UHC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
endif()
# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via

46
soc/nxp/lpc/lpc55xxx/soc.c
View file

@ -1,4 +1,4 @@
/* Copyright 2017, 2019-2023 NXP
/* Copyright 2017, 2019-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -26,7 +26,7 @@
#ifdef CONFIG_GPIO_MCUX_LPC
#include <fsl_pint.h>
#endif
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511 || CONFIG_UHC_NXP_IP3516HS
#include "usb_phy.h"
#include "usb.h"
#endif
@ -287,6 +287,48 @@ __weak void clock_init(void)
#endif /* CONFIG_USB_DC_NXP_LPCIP3511 */
#if CONFIG_UHC_NXP_OHCI
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(usbhfs), nxp_uhc_ohci, okay)
/* set BOD VBAT level to 1.65V */
POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
NVIC_ClearPendingIRQ(USB0_IRQn);
NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn);
/*< Turn on USB Phy */
#if defined(CONFIG_SOC_LPC55S36)
POWER_DisablePD(kPDRUNCFG_PD_USBFSPHY);
#else
POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
#endif
RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll0, 48000000U);
#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
memset((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM);
#endif
#endif
#endif
#if CONFIG_UHC_NXP_IP3516HS
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(usbhhs), nxp_uhc_ip3516hs, okay)
/*< Turn on USB Phy */
#if !defined(CONFIG_SOC_LPC55S36)
POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
#endif
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, CLK_CLK_IN);
CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUnused, 0U);
USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_CLK_IN, NULL);
#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
memset((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM);
#endif
#endif
#endif
DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)

2
west.yml
View file

@ -210,7 +210,7 @@ manifest:
groups:
- hal
- name: hal_nxp
revision: 73d478f7afff753c9cf60248e0c0fff4ac572ee0
revision: cea5006f1829520e40db1b550a9f49cc69ceba7d
path: modules/hal/nxp
groups:
- hal