driver: espi: add espi peripheral channel 8042_KBC driver for rts5912
add espi peripheral channel 8042_KBC driver for rts5912 Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
This commit is contained in:
jhan bo chao
Benjamin Cabé
parent
805b213424
commit
da767376ca
3 changed files with 384 additions and 0 deletions
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@ -10,6 +10,9 @@ config ESPI_RTS5912
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if ESPI_RTS5912
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config ESPI_PERIPHERAL_8042_KBC
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default y
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config ESPI_PERIPHERAL_ACPI_SHM_REGION
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default y
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@ -20,6 +20,7 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
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#include "reg/reg_acpi.h"
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#include "reg/reg_emi.h"
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#include "reg/reg_espi.h"
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#include "reg/reg_kbc.h"
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#include "reg/reg_port80.h"
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "support only one espi compatible node");
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@ -28,6 +29,11 @@ struct espi_rts5912_config {
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volatile struct espi_reg *const espi_reg;
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uint32_t espislv_clk_grp;
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uint32_t espislv_clk_idx;
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#ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
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volatile struct kbc_reg *const kbc_reg;
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uint32_t kbc_clk_grp;
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uint32_t kbc_clk_idx;
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO
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volatile struct acpi_reg *const acpi_reg;
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uint32_t acpi_clk_grp;
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@ -58,6 +64,10 @@ struct espi_rts5912_config {
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struct espi_rts5912_data {
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sys_slist_t callbacks;
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uint32_t config_data;
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#ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
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int kbc_int_en;
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int kbc_pre_irq1;
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#endif
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#ifdef CONFIG_ESPI_OOB_CHANNEL
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struct k_sem oob_rx_lock;
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struct k_sem oob_tx_lock;
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@ -71,6 +81,222 @@ struct espi_rts5912_data {
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#endif
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};
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/*
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* =========================================================================
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* ESPI Peripheral KBC
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* =========================================================================
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*/
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#ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
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static int espi_send_vw_event(uint8_t index, uint8_t data, const struct device *dev);
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static void kbc_ibf_isr(const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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struct espi_rts5912_data *espi_data = dev->data;
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struct espi_event evt = {
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ESPI_BUS_PERIPHERAL_NOTIFICATION,
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ESPI_PERIPHERAL_8042_KBC,
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ESPI_PERIPHERAL_NODATA,
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};
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volatile struct kbc_reg *const kbc_reg = espi_config->kbc_reg;
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struct espi_evt_data_kbc *kbc_evt = (struct espi_evt_data_kbc *)&evt.evt_data;
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/*
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* Indicates if the host sent a command or data.
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* 0 = data
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* 1 = Command.
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*/
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kbc_evt->type = kbc_reg->STS & KBC_STS_CMDSEL ? 1 : 0;
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/* The data in KBC Input Buffer */
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kbc_evt->data = kbc_reg->IB;
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/* KBC Input Buffer Full event */
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kbc_evt->evt = HOST_KBC_EVT_IBF;
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espi_send_callbacks(&espi_data->callbacks, dev, evt);
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}
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static void kbc_obe_isr(const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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struct espi_rts5912_data *espi_data = dev->data;
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struct espi_event evt = {
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ESPI_BUS_PERIPHERAL_NOTIFICATION,
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ESPI_PERIPHERAL_8042_KBC,
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ESPI_PERIPHERAL_NODATA,
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};
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volatile struct kbc_reg *const kbc_reg = espi_config->kbc_reg;
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struct espi_evt_data_kbc *kbc_evt = (struct espi_evt_data_kbc *)&evt.evt_data;
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if (espi_data->kbc_pre_irq1 == 1 && !espi_send_vw_event(0x0, 0x01, dev)) {
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espi_data->kbc_pre_irq1 = 0;
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}
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if (kbc_reg->STS & KBC_STS_OBF) {
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kbc_reg->OB |= KBC_OB_OBCLR;
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}
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/* Notify application that host already read out data. */
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kbc_evt->type = 0;
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kbc_evt->data = 0;
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kbc_evt->evt = HOST_KBC_EVT_OBE;
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espi_send_callbacks(&espi_data->callbacks, dev, evt);
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}
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static int espi_kbc_setup(const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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struct espi_rts5912_data *const espi_data = dev->data;
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struct rts5912_sccon_subsys sccon;
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volatile struct kbc_reg *const kbc_reg = espi_config->kbc_reg;
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int rc;
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if (!device_is_ready(espi_config->clk_dev)) {
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LOG_ERR("KBC clock not ready");
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return -ENODEV;
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}
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espi_data->kbc_int_en = 1;
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espi_data->kbc_pre_irq1 = 0;
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sccon.clk_grp = espi_config->kbc_clk_grp;
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sccon.clk_idx = espi_config->kbc_clk_idx;
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rc = clock_control_on(espi_config->clk_dev, (clock_control_subsys_t)&sccon);
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if (rc != 0) {
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LOG_ERR("KBC clock control on failed");
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return rc;
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}
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kbc_reg->VWCTRL1 = (0x01 << KBC_VWCTRL1_IRQNUM_Pos) | KBC_VWCTRL1_ACTEN;
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kbc_reg->INTEN = KBC_INTEN_IBFINTEN | KBC_INTEN_OBFINTEN;
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NVIC_ClearPendingIRQ(DT_IRQ_BY_NAME(DT_DRV_INST(0), kbc_ibf, irq));
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NVIC_ClearPendingIRQ(DT_IRQ_BY_NAME(DT_DRV_INST(0), kbc_obe, irq));
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/* IBF */
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), kbc_ibf, irq),
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DT_IRQ_BY_NAME(DT_DRV_INST(0), kbc_ibf, priority), kbc_ibf_isr,
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DEVICE_DT_GET(DT_DRV_INST(0)), 0);
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irq_enable(DT_IRQ_BY_NAME(DT_DRV_INST(0), kbc_ibf, irq));
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/* OBE */
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), kbc_obe, irq),
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DT_IRQ_BY_NAME(DT_DRV_INST(0), kbc_obe, priority), kbc_obe_isr,
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DEVICE_DT_GET(DT_DRV_INST(0)), 0);
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irq_enable(DT_IRQ_BY_NAME(DT_DRV_INST(0), kbc_obe, irq));
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return 0;
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}
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static int lpc_request_read_8042(const struct device *dev, enum lpc_peripheral_opcode op,
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uint32_t *data)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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volatile struct kbc_reg *const kbc_reg = espi_config->kbc_reg;
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switch (op) {
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case E8042_OBF_HAS_CHAR:
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*data = (kbc_reg->STS & KBC_STS_OBF) ? 1 : 0;
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break;
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case E8042_IBF_HAS_CHAR:
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*data = (kbc_reg->STS & KBC_STS_IBF) ? 1 : 0;
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break;
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case E8042_READ_KB_STS:
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*data = kbc_reg->STS;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int espi_send_vw_event(uint8_t index, uint8_t data, const struct device *dev);
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static void espi_send_vw_event_with_kbdata(uint8_t index, uint8_t data, uint32_t kbc_data,
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const struct device *dev);
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static uint8_t kbc_write(uint8_t data, const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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const struct espi_rts5912_data *const espi_data = dev->data;
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volatile struct kbc_reg *const kbc_reg = espi_config->kbc_reg;
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uint32_t exData = (uint32_t)data;
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if (espi_data->kbc_pre_irq1 == 1) {
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/* Gen IRQ1-Level High to VW ch */
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espi_send_vw_event(0x0, 0x01, dev);
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}
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if (espi_data->kbc_int_en) {
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/* Gen IRQ1-Level High to VW ch */
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espi_send_vw_event_with_kbdata(0x0, 0x81, exData, dev);
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} else {
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kbc_reg->OB = exData;
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}
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return 0;
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}
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static int lpc_request_write_8042(const struct device *dev, enum lpc_peripheral_opcode op,
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uint32_t *data)
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{
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struct espi_rts5912_data *const espi_data = dev->data;
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const struct espi_rts5912_config *const espi_config = dev->config;
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volatile struct kbc_reg *const kbc_reg = espi_config->kbc_reg;
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switch (op) {
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case E8042_WRITE_KB_CHAR:
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kbc_write(*data & 0xff, dev);
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break;
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case E8042_WRITE_MB_CHAR:
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kbc_write(*data & 0xff, dev);
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break;
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case E8042_RESUME_IRQ:
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espi_data->kbc_int_en = 1;
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break;
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case E8042_PAUSE_IRQ:
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espi_data->kbc_int_en = 0;
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break;
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case E8042_CLEAR_OBF:
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kbc_reg->OB |= KBC_OB_OBCLR;
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break;
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case E8042_SET_FLAG:
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/* FW shouldn't modify these flags directly */
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*data &= ~(KBC_STS_OBF | KBC_STS_IBF | KBC_STS_STS2);
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kbc_reg->STS |= *data & 0xff;
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break;
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case E8042_CLEAR_FLAG:
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/* FW shouldn't modify these flags directly */
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*data |= KBC_STS_OBF | KBC_STS_IBF | KBC_STS_STS2;
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kbc_reg->STS &= ~(*data & 0xff);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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#else /* CONFIG_ESPI_PERIPHERAL_8042_KBC */
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static int lpc_request_read_8042(const struct device *dev, enum lpc_peripheral_opcode op,
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uint32_t *data)
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{
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return -ENOTSUP;
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}
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static int lpc_request_write_8042(const struct device *dev, enum lpc_peripheral_opcode op,
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uint32_t *data)
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{
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return -ENOTSUP;
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_8042_KBC */
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/*
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* =========================================================================
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* ESPI Peripheral Shared Memory Region
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@ -1238,6 +1464,81 @@ static void espi_vw_ch_setup(const struct device *dev)
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irq_enable(DT_IRQ_BY_NAME(DT_DRV_INST(0), vw_idx61, irq));
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}
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#ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
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#define ESPI_VW_EVENT_IDLE_TIMEOUT_US 1024UL
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#define ESPI_VW_EVENT_COMPLETE_TIMEOUT_US 10000UL
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static int espi_send_vw_event(uint8_t index, uint8_t data, const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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uint32_t i;
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volatile struct espi_reg *const espi_reg = espi_config->espi_reg;
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if ((espi_reg->EVCFG & ESPI_EVCFG_CHEN) == 0 || (espi_reg->EVCFG & ESPI_EVCFG_CHRDY) == 0) {
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return -EBUSY;
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}
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/* Wait for TX FIFO to not be full before writing, with timeout */
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if (!WAIT_FOR(!(espi_reg->EVSTS & ESPI_EVSTS_TXFULL), ESPI_VW_EVENT_IDLE_TIMEOUT_US,
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k_busy_wait(1))) {
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return -EBUSY;
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}
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i = 0x0000FFFF & ((uint32_t)index << 8 | (uint32_t)data);
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espi_reg->EVTXDAT = i;
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/* Wait for TX FIFO to not be full after writing, with shorter timeout */
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if (!WAIT_FOR(!(espi_reg->EVSTS & ESPI_EVSTS_TXFULL), ESPI_VW_EVENT_COMPLETE_TIMEOUT_US,
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NULL)) {
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return -EBUSY;
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}
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espi_reg->EVSTS |= ESPI_EVSTS_TXDONE;
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return 0;
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}
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static void espi_send_vw_event_with_kbdata(uint8_t index, uint8_t data, uint32_t kbc_data,
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const struct device *dev)
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{
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const struct espi_rts5912_config *const espi_config = dev->config;
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struct espi_rts5912_data *const espi_data = dev->data;
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volatile struct espi_reg *const espi_reg = espi_config->espi_reg;
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volatile struct kbc_reg *const kbc_reg = espi_config->kbc_reg;
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uint32_t i;
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if ((espi_reg->EVCFG & ESPI_EVCFG_CHEN) == 0 || (espi_reg->EVCFG & ESPI_EVCFG_CHRDY) == 0) {
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return;
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}
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/* Wait for TX FIFO to not be full before writing, with timeout */
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if (!WAIT_FOR(!(espi_reg->EVSTS & ESPI_EVSTS_TXFULL), ESPI_VW_EVENT_COMPLETE_TIMEOUT_US,
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k_busy_wait(1))) {
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return;
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}
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__disable_irq();
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kbc_reg->OB = kbc_data;
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i = 0x0000FFFF & ((uint32_t)index << 8 | (uint32_t)data);
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espi_reg->EVTXDAT = i;
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/* Wait for TX FIFO to not be full after writing, in IRQ disabled state */
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if (!WAIT_FOR(!(espi_reg->EVSTS & ESPI_EVSTS_TXFULL), ESPI_VW_EVENT_COMPLETE_TIMEOUT_US,
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k_busy_wait(1))) {
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espi_data->kbc_pre_irq1 = 1;
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__enable_irq();
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return;
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}
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espi_data->kbc_pre_irq1 = 1;
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espi_reg->EVSTS |= ESPI_EVSTS_TXDONE;
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__enable_irq();
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_8042_KBC */
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#endif /* CONFIG_ESPI_VWIRE_CHANNEL */
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/*
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@ -1883,6 +2184,15 @@ static int espi_rts5912_init(const struct device *dev)
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/* Setup eSPI bus reset */
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espi_bus_reset_setup(dev);
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#ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
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/* Setup KBC */
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rc = espi_kbc_setup(dev);
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if (rc != 0) {
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LOG_ERR("eSPI KBC setup failed");
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goto exit;
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}
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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espi_setup_acpi_shm(espi_config);
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#endif
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@ -1950,6 +2260,11 @@ static const struct espi_rts5912_config espi_rts5912_config = {
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.espi_reg = (volatile struct espi_reg *const)DT_INST_REG_ADDR_BY_NAME(0, espi_target),
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.espislv_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), espi_target, clk_grp),
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.espislv_clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), espi_target, clk_idx),
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#ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
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.kbc_reg = (volatile struct kbc_reg *const)DT_INST_REG_ADDR_BY_NAME(0, kbc),
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.kbc_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), kbc, clk_grp),
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.kbc_clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), kbc, clk_idx),
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO
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.acpi_reg = (volatile struct acpi_reg *const)DT_INST_REG_ADDR_BY_NAME(0, acpi),
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.acpi_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), acpi, clk_grp),
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66
soc/realtek/ec/rts5912/reg/reg_kbc.h
Normal file
66
soc/realtek/ec/rts5912/reg/reg_kbc.h
Normal file
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@ -0,0 +1,66 @@
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/*
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* Copyright (c) 2025 Realtek, SIBG-SD7
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_KBC_H
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#define ZEPHYR_SOC_REALTEK_RTS5912_REG_KBC_H
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struct kbc_reg {
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uint32_t STS;
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uint32_t IB;
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uint32_t OB;
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uint32_t PTADDR;
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uint32_t INTEN;
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uint32_t VWCTRL0;
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uint32_t VWCTRL1;
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};
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/* STS */
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#define KBC_STS_OBF BIT(0)
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#define KBC_STS_IBF BIT(1)
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#define KBC_STS_STS0 BIT(2)
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#define KBC_STS_CMDSEL BIT(3)
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#define KBC_STS_STS1 BIT(4)
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#define KBC_STS_STS2 BIT(5)
|
||||
#define KBC_STS_STS3 BIT(6)
|
||||
#define KBC_STS_STS4 BIT(7)
|
||||
|
||||
/* IB */
|
||||
#define KBC_IB_IBDAT_Pos (0UL)
|
||||
#define KBC_IB_IBDAT_Msk GENMASK(7, 0)
|
||||
#define KBC_IB_IBCLR_Pos (8UL)
|
||||
#define KBC_IB_IBCLR BIT(8)
|
||||
|
||||
/* OB */
|
||||
#define KBC_OB_OBDAT_Pos (0UL)
|
||||
#define KBC_OB_OBDAT_Msk GENMASK(7, 0)
|
||||
#define KBC_OB_OBCLR_Pos (8UL)
|
||||
#define KBC_OB_OBCLR BIT(8)
|
||||
|
||||
/* PTADDR */
|
||||
#define KBC_PTADDR_DATADDR_Pos (0UL)
|
||||
#define KBC_PTADDR_DATADDR_Msk GENMASK(11, 0)
|
||||
#define KBC_PTADDR_CMDOFS_Pos (12UL)
|
||||
#define KBC_PTADDR_CMDOFS_Msk GENMASK(14, 12)
|
||||
|
||||
/* INTEN */
|
||||
#define KBC_INTEN_OBFINTEN_Pos (0UL)
|
||||
#define KBC_INTEN_OBFINTEN BIT(0)
|
||||
#define KBC_INTEN_IBFINTEN_Pos (1UL)
|
||||
#define KBC_INTEN_IBFINTEN BIT(1)
|
||||
|
||||
/* VWCTRL0 */
|
||||
#define KBC_VWCTRL0_IRQEN_Pos (0UL)
|
||||
#define KBC_VWCTRL0_IRQEN BIT(0)
|
||||
#define KBC_VWCTRL0_TGLV_Pos (1UL)
|
||||
#define KBC_VWCTRL0_TGLV BIT(1)
|
||||
|
||||
/* VWCTRL1 */
|
||||
#define KBC_VWCTRL1_IRQNUM_Pos (0UL)
|
||||
#define KBC_VWCTRL1_IRQNUM_Msk GENMASK(7, 0)
|
||||
#define KBC_VWCTRL1_ACTEN_Pos (8UL)
|
||||
#define KBC_VWCTRL1_ACTEN BIT(8)
|
||||
|
||||
#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_KBC_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue