Commit graph

7,138 commits

Author SHA1 Message Date
Scott Worley
3b3ad0c22f soc: microchip: mec: Common SoC helper updates
We updated the SoC Microchip MEC common helper and headers.
Add helper routines to manipulate PCR sleep enable bits, etc.
Add miscellaneous helper routines.
Add QMSPI register definitions to be used by SPI and MSPI drivers.
Create a common header containing includes of all other
common headers to prevent changing each chip's soc.h
Note, we must add build logic to handle naming difference of eSPI
SAF/TAF nodes. Intel changed name of SAF to TAF. MEC15xx and MEC172x
older driver still use SAF in DT node naming.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2026-02-06 13:46:14 -06:00
Andrej Butok
ff8d194fdd soc: nxp: kinetis: fix SOC_SERIES inconsistency
- Fixes Kconfig SOC_SERIES naming for Kinetis SoCs,
  as required by HWMv2.
- Fixes: https://github.com/zephyrproject-rtos/zephyr/issues/69317

Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
2026-02-06 08:58:07 -06:00
Chaitanya Tata
863fe89ea1 soc: nordic: nrf71: Add support to enable Wi-Fi debug
To debug Wi-Fi cores, we need to enable access to Wi-Fi debug registers.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2026-02-06 08:55:23 -06:00
Jérôme Pouiller
70bec9b18c drivers: wifi: siwx91x: Fix deprecated sl_wifi_performance_profile API
sl_wifi_performance_profile_t is deprecated. The migration to
sl_wifi_performance_profile_v2_t is pretty easy, so there is not reason to
delay it (in fact, the two versions only differ in binary compatibility,
the API is still compatible).

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-02-06 08:54:54 -06:00
Jérôme Pouiller
d0ccc26781 drivers: wifi: siwx91x: Fix sl_si91x_* names
Replace deprecated sl_si91x_* by sl_wifi_system_*.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-02-06 08:54:54 -06:00
Jérôme Pouiller
c4b74b68b8 drivers: wifi: siwx91x: Fix sli_si91x_set_region_ap_request_t name
sli_si91x_set_region_ap_request_t has been renamed in
sli_wifi_set_region_ap_request_t.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-02-06 08:54:54 -06:00
Lucien Zhao
8ebf108b3e soc: nxp: imxrt: imxrt118x: decouple specified for full parts
- Improve the universality of the 118x series SoC and
  decouple the dependencies that point to specific parts.

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2026-02-06 08:53:47 -06:00
Muhammad Waleed Badar
00eaa50369 drivers: pinctrl: add bcm2711 pinctrl driver
The BCM2711 GPIO controller provides 58 GPIO pins (0-57) that can be
configured for various functions including GPIO input/output and
alternate functions for peripherals like SPI, I2C, UART, PWM, etc.

Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
2026-02-06 08:52:07 -06:00
Camille BAUD
51ef1ce2f5 soc: bflb: Fix EM zone clobbering occupation of WRAM
EM occupates the last 32KB of WRAM by default,
we cannot use it for now, disable EM

Signed-off-by: Camille BAUD <mail@massdriver.space>
2026-02-06 11:17:56 +01:00
Hau Ho
de786f13eb soc: renesas: rx: Initial support for RX140 SoC
This commit to initial support for RX140 SoC.

Signed-off-by: Hau Ho <hau.ho.xc@bp.renesas.com>
2026-02-06 11:09:14 +01:00
Jérôme Pouiller
df01f03c0c soc: silabs: siwx91x: Code/data relocation is required
Without this change, the fix introduced in commit 189fa5f4d8e ("modules:
silabs: Force sli_mv_m4_app_from_flash_to_ram() to be in RAM") is not
active.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2026-02-05 16:54:29 +01:00
Khai Cao
f2dfb302a9 soc: renesas: ra: add SB_CONFIG_SOC_RA_START_SECOND_CORE
Add SB_CONFIG_SOC_RA_START_SECOND_CORE for Renesas RA8P1
SoC to support building a minimal launcher image that
starts the second core on Renesas RA SoCs via sysbuild

Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
2026-02-05 10:24:43 +00:00
Anjali Kashyap
705703ad8a soc: stm32: fix pm_s2ram linker warning
Below warning is reported in Zephyr upstream weekly CI after
34985a73b836b7f44b3314854fc760270e38fb26 was merged:
```
ld.bfd: warning: orphan section .TEXT.pm_s2ram_mark_check_and_clear'
from zephyr/libzephyr.a(s2ram_marking.S.obj)' being placed in section
`.TEXT.pm_s2ram_mark_check_and_clear'
```

Fix the warning by adding the appropriate headers.

Signed-off-by: Anjali Kashyap <anjkas23@gmail.com>
2026-02-04 15:32:59 -06:00
Dat Nguyen Duy
afda1e8de4 drivers: spi_nxp_lpspi: introduce Kconfig option for ERR050456
ERR050456 affects only S32K344, not all S32 platform

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2026-02-04 15:28:13 -06:00
Jamie McCrae
ff212ba22e dts: nordic: Fix missing ranges properties and relative addresses
Adds these properties which are missing, and fixes instances of
wrongly using relative addresses when they are already absolute

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2026-02-04 13:51:57 +01:00
Hake Huang
9145fd8bd7 soc: mimxrt1180_m7: enahance mimxrt1180_m7 settings
enhance mimxrt1180_m7 core settings
with mpu_region support

Signed-off-by: Hake Huang <hake.huang@nxp.com>
2026-02-04 13:51:40 +01:00
Darcy Lu
189ce18e57 soc: realtek: Add image generate tool for RTS5817
Add tool to genarate images of RTS5817 after post build stage

Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
2026-02-04 13:49:21 +01:00
Darcy Lu
b734952881 soc: add realtek RTS5817
Add support for the rts5817 MCU

Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
2026-02-04 13:49:21 +01:00
Aksel Skauge Mellbye
8b09d8d967 soc: silabs: silabs_s2: Initialize sleeptimer early
Sleeptimer must be initialized before sl_power_manager since
SiSDK 2025.12, as it's no longer done internally in the power
manager.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2026-02-03 08:23:21 -06:00
Travis Lam
4a2f56bb8e soc: nordic: nrf7120 fix missing tfm support
Add NRF_TRUSTZONE_X_REGION_SIZE for mpc region size alignment.
fix missing include of soc header file.

Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
2026-02-03 12:13:27 +00:00
Axel Le Bourhis
96b0b9079e soc: nxp: mcxw7xx: refactor shared memory layout
- Define the entire SMU2 as a single memory region so it represents only
one entry in the MPU.
- Clean up linker.ld and sections.ld to remove obsolete/unused symbols
- Declare the "shmem_fwk" section in SMU2 used by connectivity framework
- Rearrange the rpmsg shared memory relatively to the entire SMU2 range
- Provide necessary symbols for the connectivity framework to locate its
  shared memory section within SMU2

This is preparatory work for upcoming connectivity framework
integration and mcxw70 ble enablement.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
2026-02-02 11:40:41 -06:00
Appana Durga Kedareswara rao
39fdb32183 soc: xlnx: versal2: fix NUM_IRQS to cover all hardware interrupts
The previous NUM_IRQS value of 256 was incorrect for the Versal2
RPU platform. Increase to 288 to ensure all hardware interrupt
lines are properly supported by the GIC driver.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
2026-02-02 11:39:13 -06:00
Camille BAUD
2d2bc6af01 drivers: regulator: driver for BFLB internal regulators
Drivers to manage BFLB SoC internal LDO11 regulators

Signed-off-by: Camille BAUD <mail@massdriver.space>
2026-01-30 05:56:02 -06:00
Camille BAUD
5d01941e32 bflb: soc: Consolidate brown out controls
Create a new binding and associated soc-level driver to set brown-out

Signed-off-by: Camille BAUD <mail@massdriver.space>
2026-01-30 05:56:02 -06:00
Krzysztof Chruściński
fe31b2a7e6 soc: nordic: common: nrf_sys_event: Fix absolute event register
Fix case where absolute event was registered. In that case PPI wake
up was never used.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2026-01-30 09:17:50 +01:00
Krzysztof Chruściński
b0ab79429a soc: nordic: common: nrf_sys_event: Fix missing return
nrf_sys_event_unregister was missing an immediate return when PPI
was used by the handle. It was stepping into non-PPI case where
an assert might have been triggered.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2026-01-30 09:17:50 +01:00
Joel Guittet
85854252b2 soc: espressif: esp32: increase bootloader dram length
Following recent updates, the bootloader dram segment length must be
increased to compile mcuboot on esp32.

Signed-off-by: Joel Guittet <joelguittet@gmail.com>
2026-01-29 16:14:57 -06:00
Sylvio Alves
5b00645e6e soc: espressif: loader: use zephyr,code-partition for flash offset
Use the zephyr,code-partition chosen node to determine the flash
partition offset for IROM/DROM mapping. This enables Direct-XIP
mode support where the slot1 variant image needs a different flash
offset than slot0.

Falls back to slot0_partition if zephyr,code-partition is not defined,
maintaining backward compatibility with existing configurations.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2026-01-29 16:14:13 -06:00
Jamie McCrae
80f19801b2 soc: sifive: sifive_freedom: Fix SoC Kconfig naming and issues
Fixes the Kconfig name of this so that it matches the value from
soc.yml, and deprecates the old name - this is required to support
future build system features. Additionally, it fixes an issue in
Kconfigs of this SoC of duplicating existing symbols

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2026-01-29 17:20:11 +01:00
Fin Maaß
2eeaefbd19 Kconfig: use configdefault to set default for FPU
By using configdefault the original dependencies
are preserved (CPU_HAS_FPU).

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-29 14:26:28 +00:00
James Bennion-Pedley
69d1b144ca soc: wch: Add idle gating functionality to fix hardware bug
In WCH chips entering idle via `wfi` will break ongoing DMA
transactions. This adds PM state to prevent `wfi` idle in specific drivers.

Signed-off-by: James Bennion-Pedley <james@bojit.org>
2026-01-29 14:24:11 +00:00
Peter van der Perk
23e314d187 imx95: Cortex-M7 add FlexCAN controllers
Adds FlexCAN definitions and 80Mhz clock for correct timing

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2026-01-28 14:42:21 +01:00
Jamie McCrae
b8ab27aa40 dts: Fix incorrect/invalid usage of RAM/NVM nodes for nRF54L*
Fixes various issues with how these have been used:
- Reserved memory was wrongfully used to describe an RRAM area
  for a CPU
- Reserved memory was wrongfully used to describe an SRAM area
  for a CPU
- A partition described using reserved memory did not have the
  required NVM erase size and write size parameters set for it
- RRAM partitions were not correctly setting ranges properties
- RRAM validation wrongly took the "base flash controller" into
  considering because it was not using unit addresses
- RRAM partitions incorrect set up so that they collided with
  one another for different cores

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2026-01-28 10:18:57 +01:00
Sylvio Alves
fbafad0520 drivers: video: esp32: fix camera sensor init race condition
Move camera XCLK setup from DVP driver (POST_KERNEL) to esp_lcd_cam.c
(PRE_KERNEL_2) to ensure the image sensor receives clock before its
I2C initialization. This fixes a race condition where sensors like
ov2640 would fail to respond during probe because XCLK wasn't yet
configured.

Also adds timestamp to captured video buffers and removes a noisy
error log for set_selection when the source returns -ENOSYS.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2026-01-28 08:33:10 +01:00
Mathieu Choplain
11cfe9feed soc: st: stm32mp2x: add OpenAMP resource table section to linker script
The `.resource_table` section was not declared anywhere, leading to an
"orphan section" linker warning when OpenAMP was used with the resource
table enabled.

Fix it by adding the missing section to the SoC-specific linker script.
(the section is identical to the one defined for STM32MP1x series)

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2026-01-27 15:19:09 -06:00
Axel Le Bourhis
100f4c26a6 hal_nxp: integrate mcuxsdk ble controller ng
Move ble-controller integration to mcux-sdk-ng to make future release
integration easier. Based on 25.09.00 release, same as the existing
version.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
2026-01-27 10:53:45 +00:00
Torsten Rasmussen
a0983a2f91 cmake: align board qualifiers in CMake with Kconfig
The value os board qualifiers in CMake and Kconfig differs.
CMake has a leading '/', as example:
CMake:   BOARD_QUALIFIERS=/nrf52840
Kconfig: BOARD_QUALIFIERS=nrf52840

This was also discussed in
https://github.com/zephyrproject-rtos/zephyr/pull/69740

This commit aligns the value of the CMake variable BOARD_QUALIFIERS to
the value of BOARD_QUALIFIERS (CONFIG_BOARD_QUALIFIERS) in Kconfig.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2026-01-27 10:52:37 +00:00
Hou Zhiqiang
1e6806bec1 soc: imx943: m33: Initialize DTCM to generate ECC bits
The TCM ECC is enabled by default after reset, so must initialize
the entire DTCM with word-aligned writes to generate vaild ECC bits
before any byte or halfword access, otherwise ECC faults will occur.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2026-01-27 08:07:08 +01:00
Tom Burdick
a5d4626b8c soc: infineon: pse84: Enable MVE instruction set
The cmsis_dsp tests were failing on the m55 due to incorrect
instructions being generated. Enabling Helium (MVEI/MVEF)
fixes the issue and most of the tests now pass.

Several tests are still failing unfortunately but no longer are
the tests failing on an vld1.16 instruction.

Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
2026-01-26 14:02:47 -06:00
Enzo Vanhauwaert
6a5091cde0 nxp: mimxrt595_evk: enable USBD support
Enable use of USB Next stack and UDC driver for mimxrt595_evk (imxrt5xx)

Signed-off-by: Enzo Vanhauwaert <enzo.vanhauwaert@hotmail.com>
2026-01-26 13:56:44 -06:00
Appana Durga Kedareswara rao
7acd5813e9 soc: amd: Add initial support for Versal SoC APU
Add initial support for the Versal SoC APU, which is based on
the Arm Cortex-A72 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.

This commit introduces the SoC definition and MMU configuration
required for APU-based development on the Versal platform.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
2026-01-26 13:56:19 -06:00
Yves Wang
bf668c8181 soc: nxp: mcxe24x: set WDT_DISABLE_AT_BOOT as y
Enable WDT_DISABLE_AT_BOOT by default for MCXE24X SoC series to prevent
unexpected system resets during initialization and development.

Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
2026-01-26 10:14:30 -06:00
Tomasz Leman
8d072e85b1 ipc: intel_adsp: fix inverted sync wait condition
The synchronous send helper intel_adsp_ipc_send_message_sync() had
inverted logic for determining when to wait for host acknowledgment.

Before this fix, the function would:
- Return immediately (without waiting) when send succeeded (ret == 0)
- Try to wait on semaphore when send failed (ret < 0)

This is backwards. The correct behavior is to wait for the host ACK
semaphore only when the message was successfully queued for
transmission.

The inverted logic caused multiple test failures:
- HDA tests received -EBUSY on subsequent sends because tx_ack_pending
  remained true when no wait occurred
- Smoke IPC tests timed out waiting for msg_flag/done_flag because
  messages were sent without waiting for host responses
- Clock calibration tests failed because timestamp responses were never
  received

This aligns the SoC glue implementation with the test-local helper
implementations and restores the original pre-refactoring behavior.

Related to: #102103
Related to: #102106

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2026-01-26 10:13:17 -06:00
Fin Maaß
869845d6ab aesc: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
ed6a969849 andestech: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
01bc8b2351 egis: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
8f69f66059 gd: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
fb1aeeb346 intel: niosv: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
5b0a847098 ite: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Fin Maaß
74e5e8fc13 lowriscv: riscv: use riscv,isa-extensions dt prop
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00