Use custom cpu_idle implementation for all VPRs and implement
workarounds for erratas which impact sleeping
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This places the L1 and L2 page tables continuously in memory,
and keeping them together. This avoids some fragmentations in
the virtual memory space.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add Kconfig entries to allow compile own s2ram implementation.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add STM32_INT_FLASH_SECURE_BASE_ADDRESS kconfig symbol to define
the base address of the memory mapped STM32 SoC secure internal flash
address range. This configuration and only apply to STM32 Cortex-M SoCs
that embed and internal flash and support TrustZone.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Using macrobatics, shrink the GPIO ports table such that it only contains
as many elements as required to access all enabled GPIO ports. This saves
a lot of ROM compared to the previously fixed-size table which had one
pointer for each *possible* GPIO port, regardless of whether or not they
existed on the target HW and were enabled in Devicetree.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The `pinctrl_soc_pin_t` format occupied two uint32_t even though all info
it stores can be compressed in 32 bits only, and also didn't map very well
to the hardware (especially on STM32F1). Due to defects, the format was
also NOT what the `stm32_gpioport_configure_pin()` function consumed to
actually configure a GPIO port, requiring additional decoding/manipulation
logic.
Introduce a vastly reworked format which only requires 32-bit per pinctrl
entry and maps nicely to hardware and becomes the new format consumed by
stm32_gpioport_configure_pin(). This heavily simplifies the pinctrl driver
since it no longer needs to examine the actual values (except to determine
the target GPIO port and pin - this is done on purpose!). The GPIO driver
converts Zephyr flags to this new format too.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use a single `if` chain to configure all mode-specific elements to make
the code easier to follow. While at it, add/update a few comments.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move the logic which sets the output level based on configuration to the
common `stm32_gpioport_configure_pin()` function to reduce duplication.
To support the GPIO use case where a pin's configuration is changed without
modifying its output state, a new parameter is introduced which specifies
whether or not the output level should be modified.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
All defines use just the target register's name as part of the define.
Follow this convention for DELAY/ADVCFGR.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use `_Pos`/`_Msk` suffixed defines for pinctrl format bits definitions and
declare `_Msk` already shifted. This is aligned with the CMSIS definitions
format which shorter, easier to understand and enables use of
macros _FLD2VAL/_VAL2FLD.
Update all code using these defines accordingly.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Set MAX_IRQ_PER_AGGREGATOR to 52, fixing spurious PLIC interrupts
caused by the default of 0.
Signed-off-by: Adrian Śliwa <asliwa@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The SoC supports L32EX/S32EX to do atomic CAS ops. Since we now
have support for these, we move sample_controller32 to use that
for testing.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Apollo4P requires cache to be configured and enabled early in the
boot process for proper interrupt timing and 96 MHz operation.
Without cache initialization, interrupts can be delayed by hundreds
of microseconds, causing timing anomalies in time-critical applications.
This aligns Apollo4P initialization with:
- Apollo3 SoC initialization (which includes cache init)
- Official Ambiq SDK examples (uart_async, etc.)
- Ambiq application notes for maximum performance
The cache must be initialized before low power init to ensure
proper memory access timing throughout the boot sequence.
Fixes interrupt timing delays observed in UART TDMA applications
running at 2 Mbaud with 1ms frame timing.
Signed-off-by: Tibor Kiss <kiss.tibor@gmail.com>
Remove the whitespace from dt_has_compat. The whitespace would be part of
the compatible name and never match the device-tree. Therefore, this config
would never be enabled by the DT.
Also fix a typo in BOOT_XSPI_NOR's message.
Signed-off-by: Daniel Schultz <dschultz@baylibre.com>
Ensure Zephyr post build sequence is run when TF-M is embedded
on a STM32 target since TF-M/STM can install its regression.sh
script which must be processed by running STM postbuild.sh
to be functional.
This change fixes an issue where running 'west build' on an
already built project, or running 'west flash' makes the
regression.sh script to be reinstalled raw from TF-M source tree
(platform/target/ext/stm/...) without being updated trough
postbuild.sh script.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Move set_target_properties for runners_yaml_props_target below
board.cmake include so that UICR image always flashes its own
output regardless of the main image configuration.
When the main image targets cpuapp/ns (TF-M), import_kconfig()
pulls CONFIG_TFM_FLASH_MERGED_BINARY into the UICR image's CMake
scope. This causes board.cmake to override hex_file with
tfm_merged.hex, which does not exist in the UICR utility image,
resulting in a flash failure.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Add support for the ODRIVE (output drive) field at bits 12-13 of the
IOPCTL register on RT7XX. This field controls the transmitter current
drive impedance selection (100/66/50/33 ohm).
- Add nxp,drive-current property to the rt-iocon-pinctrl binding
- Add IOPCTL_PIO_ODRIVE macro to pinctrl_soc.h
- Extend pin config mask from 0xFFF to 0x3FFF to include ODRIVE bits
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The Cortex-R frequency for the TI K3 series relies on the clock frequency
of the external crystal since it uses the DMTimer interrupt and the DMTimer
uses the external crystal clock as input clock. While some SoC series
inside the K3 family only allow one frequency for the external crystal
(based on the bootmode pin documentation inside the TRM) other allow
multiple possible frequencies. For SoC series that only allow one frequency
it is stored inside the series defconfig (am64x and j722s) and for series
that allow multiple frequencies it was moved to the board defconfigs
(j721e).
Additionally this frequency was wrong for the am64x and j722s series and
got corrected to 25 MHz.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
The SoCs in the TI K3 family enable the OpenAMP resource table
automatically in the Kconfig instead of being disabled due to being
optional in some cases. It is optional when booting after a SBL from the TI
MCU+ SDK but it is required when booting via remoteproc from Linux.
Due to this the enabling has been moved to the board level and whether it
is enabled is based on the documented boot method. For the undocumented
Cortex-R cores on the SK-AM64 it has been enabled since the Cortex-M core
has documentation for booting via remoteproc and for the Cortex-M core on
the AM243-EVM it has been disabled due to having no Cortex-A cores to run
Linux on.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
The Cortex-R cores in the AM64x SoC have 256 instead of 512 interrupts.
This was set wrong since the AM64x Cortex-R options came from the J72x
options which has 512 interrupts connected to the Cortex-R via the VIM.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Split up the am6x Kconfig files into am62x, am62lx, am64x and j72x to allow
different configurations for different SoC series. While this adds some
redundancy it allows better separation in case some configuration options
between SoCs need to be different, like the number of interrupts on
Cortex-R processors.
Furthermore some ARM-cores were theoretically configured but not actually
supported as build target for the general am6x SoC series, sometimes
because the cores are not present in the SoC itself (e.g. non Cortex-A
cores for the AM62Lx series) and sometimes because nobody added support yet
(e.g. Cortex-A on the AM64x series). Therefor all currently non-supported
combinations have been removed.
Finally the common files were put into the K3 family directory and
clang-format was run on them.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Some platforms (nrf53 and nrf54h) are using hook for entering
idle to execute SoC specific code. There can only be one hook
in the application so it was impossible for the user to add own
code that is executed in the hook.
Add CONFIG_NRF_CUSTOM_ON_ENTER_CPU_IDLE_HOOK option. If enabled,
the Nordic hook is not implemented. The user implements own hook.
It is the user's responsibility to include SoC specific part in
that hook.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add BLE controller port layer (IRQ, clock, RF callbacks) and linker
scripts for the vendor binary blob.
ble_rwdata.ld: places .pds_code, .tcm_data, .retention and ROM data
with GP-relative addressing into the .data section (RWDATA).
ble_hbn.ld: places .hbn_code (RF functions) and .retention_noinit
into the RETRAM region (HBN RAM at 0x40010000). Provides linker
symbols __LD_CONFIG_EM_SEL and __LD_BLE_CORE_REG_SIZE consumed by
the controller blob.
soc.c: configure GLB_EM_SEL for 8KB (or 16KB for m8s1p) exchange
memory when BLE is enabled, and copy .hbn_code from flash to RETRAM
at boot.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add a LONG(0) at a 16-byte aligned start of .flash.rodata_end so
the merged flash.rodata segment size never lands on a boundary
that trips esptool's --ram-only-header alignment assertion during
elf2image.
Applied to all espressif socs since the issue is not chip-specific.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
SRF needs to be initialized on the cm33ns soc to be used to
send requests to the SPE. Added configuration file and code
to properly initialize srf requests pool.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
VPR after boot has default sleep mode set to WAIT which is the most
power hungry sleep mode. Typically, user expects to see low current
when system enters system-on-idle state. Set sleep mode that is
more suitable: DEEPSLEEP by default for nRF54H20 PPR which allows to
reach <5 uA idle current and has almost the same wake up time as WAIT,
HIBERNATE for other VPRs on non-NRF54H20. It allows to get <5 uA
currents in system-on-idle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Update the help text for CONFIG_SECOND_CORE_MCUX to be more generic
and applicable to all supported multi-core RT series (RT11xx, RT118x,
and RT7xx), rather than being specific to RT11xx and Cortex-M7/M4.
The updated documentation now refers to "primary core" and "secondary
core" instead of specific core types, making it more accurate for all
supported SoC series.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Rework GPPI configuration for SD^2PPI global domain. There can
be an SoC which does not have dppic135, dppic136, ppib136 and
ppib137 nodes. Add build time conditions to configuration files.
Additionally, remove references to APBxx (bus) names which
could be confusing as they are not references anywhere else.
Use DPPIxxx identification instead.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Move files which are specific to nrf54h20 global domain from nrf54h
folder to common. Rename those files to use sd2ppi name instead of
nrf54h. SD2PPI (or SD^2PPI) is an abbrevation for Secure Distributed
(multi-Domain) DPPI - PPI system where DPPI resources requires
Ironside service.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add SOC_RTS5912_ULPM_POWEROFF_BRAM for user to decide
if the BRAM need keep power or not during ULPM.
SOC_RTS5912_ULPM_POWEROFF_BRAM default as n, means NOT to poweroff.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
Place mspi_timing_by_mspi_delay text and rodata in IRAM/DRAM.
This file contains PSRAM and flash timing tuning functions
that must not run from flash during MSPI clock reconfiguration.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add missing Kconfig.sysbuild to enable VPR launcher image when
building for the FLPR core.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
1. Remove the NRF_PLATFORM_HALTIUM and NRF_PLATFORM_LUMOS Kconfig
symbols and eliminate all "haltium"/"lumos" naming from the zephyr
directory.
2. The shared haltium_power.c/h and haltium_pm_s2ram.c/h files from
soc/nordic/common/ are duplicated into the per-SoC-series directories
(nrf54h/ and nrf92/) as soc_power.c/h and soc_pm_s2ram.c/h. The
corresponding build rules are moved from common/CMakeLists.txt to the
per-series CMakeLists.txt files.
3. Kconfig guards that relied on the platform symbols are replaced with
individual hardware feature checks derived from nrfx/MDK:
- select NRFX_POWER if !NRF_PLATFORM_HALTIUM -> if HAS_HW_NRF_POWER
- CLOCK_CONTROL default ... !NRF_PLATFORM_HALTIUM -> HAS_HW_NRF_CLOCK
- depends on NRF_PLATFORM_LUMOS -> SOC_SERIES_NRF54L||SOC_SERIES_NRF71
4. C preprocessor guards using CONFIG_NRF_PLATFORM_HALTIUM are replaced
with explicit SoC series checks (CONFIG_SOC_SERIES_NRF54H ||
CONFIG_SOC_SERIES_NRF92).
5. The sysbuild option NRF_HALTIUM_GENERATE_UICR is renamed to
NRF_GENERATE_UICR.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add kconfig options for the signature flag and mirror comparison range
address, allowing projects to customize these settings.
Additionally, this change introduces custom signature extension section.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Enclose default LLEXT heap section placements with
!CONFIG_LLEXT_CUSTOM_HEAP_PLACEMENT. Users who want to
write a custom linker script can include files like
snippets-noinit.ld, common-noinit.ld or the SOC linker
scripts without including the default LLEXT heap
section placements.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
SoC series such as AM62x and AM62Lx use the GIC500 module. This module
supports up to 16 SGIs, 16 PPIs and 960 SPIs. This comes to a total of 992
interrupts. Hence, update the NUM_IRQ to match this number.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
- Added autanalog MFD support in PSE84 DTS files
- Refactored autanalog ADC in PSE84 to use a common
MFD for handling the global AC configuration
- Constructed AC to use phandle in the overlay
for a better the user experience.
- Added support for a basic and advanced mode
with custom AC
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Convert three NXP drivers from raw DT_REG_ADDR() register access
to the Zephyr device MMIO API (DEVICE_MMIO_ROM / DEVICE_MMIO_RAM /
DEVICE_MMIO_MAP):
With the MMIO API, the drivers create their own mapping at init time via
DEVICE_MMIO_MAP() thus the corresponding mmu_regions entries are removed
from the five NXP SoC files that carried them.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
