Select PM_STATE_SET_IRQ_UNLOCKED for SoCs whose PM hooks still unblock
or restore interrupts from pm_state_set() or pm_state_exit_post_ops().
This preserves existing behavior until each SoC is migrated to the
default idle-owned IRQ restore contract.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Use the Cortex-M PM state-set prepare and finish helpers around WFI so
MCXE24X can follow the default locked IRQ PM contract.
Keep pm_state_exit_post_ops() limited to hardware resume cleanup by
clearing SLEEPDEEP without re-enabling interrupts.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace the opt-in locked marker with a legacy unlocked marker. With
this, SoC PM hooks use the locked IRQ contract by default, and only
legacy SoCs that still unmask interrupts from PM hooks select
PM_STATE_SET_IRQ_UNLOCKED.
Drop the old locked marker selections from already migrated NXP SoCs and
update the PM test expectation accordingly.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add a nocache memory region to mimxrt685s/hifi4's DT
(adsp_data_nocache). Move adsp_text and adsp_data from non-cached views
to cached views. Add Kconfig variables and symbols to SoC's memory.h
describing that region. Enable nocache memory support. Modify SoC's
linker script to set up linking against that memory region and add
nocache section initialisation to soc.c.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
The dedicated Bluetooth long workqueue (BT_LONG_WQ) exists to isolate the
latency of long-running operations (ECDH, and the GATT database hash
computation) from the system workqueue. It comes at the cost of a separate
thread: its stack plus control block consume on the order of 1.25 KB of
RAM, which is significant on the very memory constrained nRF51 (16 KB RAM
class) parts.
Disable BT_LONG_WQ by default on nRF51 using a configdefault in the SoC's
Kconfig.defconfig, keeping the platform specific policy out of the generic
Bluetooth Kconfig. With it disabled, the long-running operations
transparently fall back to the system workqueue (the ecc.c and gatt.c call
sites already handle this). This mirrors the existing nRF51 specific
defaults for BT_TX_PROCESSOR_THREAD and BT_RECV_CONTEXT, which likewise
trade dedicated threads for reduced RAM usage on this platform.
To ensure ECDH can run on the system workqueue without overflowing its
stack, also give SYSTEM_WORKQUEUE_STACK_SIZE a larger nRF51 default (1280)
when BT_ECC is enabled and the long workqueue is not. This value was chosen
from a measured high-water mark of 1000 bytes for the combined HCI init and
ECDH workload on an nRF51822 (bbc_microbit), leaving a safety margin. Even
with this larger system workqueue stack, the net result is a substantial
RAM saving compared to running a separate long workqueue thread.
Runtime-verified on bbc_microbit (nRF51822): with BT_LONG_WQ disabled and
the system workqueue stack at its new default, ECDH completes successfully
on the system workqueue (BT_DEV_HAS_PUB_KEY gets set) and the device
advertises normally.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add Cortex-A32 Application Processor SubSystem (APSS) support for
the Alif Ensemble E8 SoC (AE822FA0E5597LS0). This introduces the
APSS specific code in a dedicated soc/alif/ensemble/apss
directory, reusable by other Ensemble SoCs that include the APSS
cluster.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Introduce SOC_FAMILY_ENSEMBLE_APSS helper Kconfig symbol that
groups the Cortex-A32 architecture configuration shared by Ensemble
SoCs containing an Application Processor SubSystem (APSS) cluster.
This is analogous to the existing SOC_FAMILY_ENSEMBLE_RTSS helper
that groups the Cortex-M55 configuration for the RTSS cores.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
In addition to the existing Cortex-M55 cores (residing in the Real
Time SubSystem - RTSS), some SoC series in the Ensemble family contain
Cortex-A32 cores in their Application Processor SubSystem (APSS).
Reorganize RTSS-specific code from the common/ directory into a
dedicated rtss/ subdirectory to prepare for adding APSS support.
No functional changes for existing RTSS-based boards.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The MCXW7x active-mode DCDC regulator output voltage was previously
fixed by the power init path, which only ran when CONFIG_PM was
enabled. Some use cases (notably reaching the highest BLE TX power
levels) require a specific DCDC output voltage to be applied
unconditionally at boot.
Add an optional "active-dcdc-output-microvolt" property to the
nxp,spc binding so the target voltage is described in the device
tree. The property is intentionally SoC-agnostic: legal values are
validated per-SoC in C rather than constrained by an enum in the
binding, since the shared compatible spans several SoC families with
different DCDC capabilities.
Implement the configuration in a new soc_dcdc.c that is compiled
unconditionally (independent of CONFIG_PM). nxp_mcxw7x_dcdc_init()
maps the configured microvolt value to the HAL DCDC level, sets the
VOUT2P5_SEL bit only for the 2.5V custom mode, and applies the change
with the active-mode voltage detectors saved, disabled and restored
around it. BUILD_ASSERTs reject values the DCDC cannot produce and
cross-check the configured voltage against the NBU max-tx-power-dbm
(10 dBm requires 2.5V, above 0 dBm requires at least 1.8V). When the
property is absent the routine compiles to a no-op and the DCDC
output voltage is left untouched.
Move the active-mode DCDC handling out of set_spc_configuration() in
power.c so the device-tree configured value is preserved and not
overwritten by the low-power init path. The logic is kept
self-contained so it can later be lifted into a dedicated SPC driver
without binding or device tree churn.
Tested with samples/bluetooth/peripheral on frdm_mcxw71,
frdm_mcxw72 and frdm_mcxw70 (the latter exercising the no-op path).
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Add handling of the optional property which indicates that VPR core
is indicating its readiness by setting a specific VPR event. Mailbox
is polling for readiness before sending the signal. Feature is
optional and used only for instances with nordic-vpr-ready-event
property.
Add optional setting of the event in VPR initialization.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Many MAX32 targets do not respect DEMCR.VC_CORERESET, so add some small
reset hook read that can be used for reset type `12` to halt on reset.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Added option to nrf gswdt drivers to be able to configure
maximum timeout window and also to be able to stop gswdt.
This features are only available when gswdt service is
supported by local domain, otherwise gswdt can still be
used but with fixed timeout and cant be stopped.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
The shell commands require memory only when they run. It does not make
sense to allocate static memory for the shell commands.
It is especially true for the "silabs fota" command which requires large
buffers (16kB).
With heap allocation, there is no longer reason to limit the size of the
http_buffer. This buffer has to be larger than HTTP headers. 512B is
usually fine, but 1024B would avoid problems.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
DNS_RESOLVER is is fact not a requirement for "silabs fota".
DNS_RESOLVER selected NET_SOCKETS, so if we remove DNS_RESOLVER, we need to
explicitly select NET_SOCKETS.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Since use_tls was filled after the port number, the default port number was
set 80 even if https:// was selected.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This kconfig is for enabling zephyr fork tfm to build with
tfm nrf mramc service. The service should allow ns application
to configure mramc using psa call. The Kconfig should be specific
only for nrf7120.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
- Kconfigs in modules/ should not define configs with an SOC_ prefix.
Furthermore, these options are SDK specific, not SoC specific.
- The simplicity_sdk configs do the same.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Switched from GPIO_PORT_PIN_MASK_FROM_NGPIOS to the Devicetree-aware
macros (GPIO_PORT_PIN_MASK_FROM_DT_NODE)
to ensure the gpio-reserved-ranges property is respected by the drivers.
This aligns with the architectural design established in PR #56295,
where generic support for reserved ranges was centralized within the
DT-aware pin mask macros rather than creating new top-level aliases.
Fixes#57038
Signed-off-by: Anant Gyan Singhal <anant23082@iiitd.ac.in>
The symbol is no longer needed and causes duplicate
definition of symbols expected by MDK.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
to avoid giving a false impression that they can also be used on older
devices to lock AP-Protect.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The small-heap default for the SPIRAM heap was sized just below the
sys_heap small-only limit, but linker alignment rounded the region up
by one chunk, tripping the heap-size assertion at init on targets with
small internal RAM such as esp32.
Lower the default to an aligned value that stays within the limit after
alignment, so the SPIRAM heap initializes correctly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Octal PSRAM modules on esp32s3 are paired with octal flash. Without
CONFIG_ESPTOOLPY_OCT_FLASH the flash runs in untuned STR timing and can
corrupt at high PSRAM speeds, since runtime auto-detect only fixes the
IO mode and cannot enable timing tuning that is gated at build time.
Default ESPTOOLPY_OCT_FLASH to y when SPIRAM_MODE_OCT is selected so the
flash timing is tuned (DTR) out of the box. The user can still disable
it for boards that pair octal PSRAM with quad flash.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The flash-to-PSRAM copy mechanism behind SPIRAM_FETCH_INSTRUCTIONS and
SPIRAM_RODATA is only implemented for the esp32s2 and esp32s3. On the
esp32c5 and esp32p4 these options pulled in code that does not build,
so restrict the prompts to the supported series.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
MXS22IOSS has CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGH, this
adds support so that it can be used. This is specifically
needed for I3C which requires it
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Add SOC_LINE_STM32L4PLUS hidden configuration symbol for STM32L4+ SoC
series that have specific configuration constraint.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
When resuming from standby using the MAX32 RTC peripheral, we still need a
small delay to ensure the RTC is ready for interaction, so restore that
delay, but now conditionally.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Select HAS_PM and PM_STATE_SET_IRQ_LOCKED for SOC_MCXN947_CPU0,
matching MCXN547 and MCXN236. PM_STATE_SET_IRQ_LOCKED pairs with the
shared mcxn power hooks, which keep interrupts locked across low power
entry and resume.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
TF-m includes a GeneratedSource folder with default generated
sources files that are the standard use case for the kit_pse84_eval
board with EPC2. When supporting different boards we'd need a TF-m
PR to update those files and the cherry pick that into Zephyr's
fork and then directing the build properly. It makes more sense
to host a copies of these files and give them as inputs to the
TF-m build so that they are more easily maintainable.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Added FIFO support for PSE84 autanalog SAR. The FIFO is 512 elements
deep. It can be subdivided into x8 64 elements to support 8 independent
streams of ADC data.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add the radio on stm32wba to device tree and move the
bluetooth node and the ieee802154 node inside it.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Select CPU_HAS_ICACHE and HAS_MCUX_MCM_LPCAC for the MCXW7xx
SoCs. Default cache management to the external cache backend and set
the instruction cache line size to 256 bytes, matching the LPCAC
organization documented for MCXW72.
This makes the standard Zephyr cache API available to MCXW7xx
applications and drivers that need to invalidate the code cache.
Validated with an incremental build of build/lpcac_mcxw72 for
frdm_mcxw72/mcxw727c.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
In the case of true multicore with TF-M the cm33ns and cm55 cores
need to set up an SRF infrastructure to communicate secure requests
to the secure core when trying to interact with secured peripherals.
This is done with IPC messages between the cm33ns and the cm55 and
ways for them to signal to each other when a new request has been
submitted and then when one has been processed.
A queue is initialized on the cm33ns who acts as a relay between
the cm33s and the cm55.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
When enabling SRF Multicore support both the cm33ns and the cm55
cores need additional files to be included in the build to be
successful and functional.
On cm33s we need to instruct TF-M to enable the CM55 present flag and
the mailbox support.
On cm33ns side we need to enable the custom process request handling
for IPC SRF requests specify custom IPC packets and handle the address
remapping for CM55 addresses.
On cm55 side we have to reference files built durint TF-M install
and add the custom IPC handling for SRF requests. Additionally we need
to link its source files to the same one used by TF-M in ifx-cycfg.
Also added check for defines to avoid redefining in infineon_kconfig.h
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Add the required configuration files for srf ipc support.
Update the basic one to handle the config define for cm55 and
restructure removing unnecessary sections.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
A cm55 allocatable shared memory that is accessible by the cm33 cores
region was already set aside but not used.
This commit includes the CMakeLists and linker updates to use it to
allocate shared data.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Add initial support for the Espressif ESP32-S3-BOX-3 development kit.
This commit introduces board definitions for both PRO CPU and APP CPU
variants, including DTS, pinctrl, Kconfig, defconfig, and
documentation.
Signed-off-by: Sidhartha Raghaw <sidhartha.raghaw@notionext.com>
Adopt the new HAL/LL interfaces: ADC_LL_* macros,
esp_clk_tree_* clock helpers, and rng_ll_* entropy reads
across the adc, i2c, pwm, mdio and entropy drivers.
Update the Radio blobs to latest version.
Update linkers to include new sleep cache calls.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
NUM_IRQS must account for the reserved ISR table offset so every
CPU interrupt line maps into the software ISR table. Size it to the
32 CPU lines plus the offset.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Close wifi_setup() before ending the CONFIG_SOC_NRF71_WIFI_BOOT guard.
The extra preprocessor endif left the function body outside its guard
and broke builds that enable Wi-Fi boot from the secure image.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
