Currently, the only available platform is Nitrogen, featuring a
VexRiscv CPU that boots from external SPI flash and runs code from
external HyperRAM.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Fixes the missing Kconfig resource for the siwx91x SoC. This ensures
that soc_early_init_hook function is correctly called for the siwg917
SoC during initialization.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Code responsible for internal capacitor values containted
leftover workarounds in the calculations after PS update.
Removed redundant conversions and cleaned up both code
and comments to align both LFXO and HFXO calculation.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Some drivers need header file soc.h, according to Zephyr SoC Porting Guide
soc.h must be provided for each SoC, so created an empty one.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Enables using the whole flash on CH32V208
This also involves limiting frequency of the CPU to 120Mhz
from 144Mhz to meet recommendations.
Signed-off-by: Camille BAUD <mail@massdriver.space>
MDK 8.69.1 included in nrfx 3.10 already applies the workaround,
so there is no need to do it again.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
When PM2 is enabled, it will disable many of the devices, so need to
enable PM policy constraints for this mode also so that device drivers
can work.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Compared to the CH32V003, the CH32V00x series is an evolution that
uses a different microarchitecture (V2C instead of V2A) and different
pinctrl mappings.
Fork the current qingke_v2a and use the new proposed naming convention.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Move creation of last section id from ld linker script LONG() usage to
C code with last section attribute.
The use of `LONG()` works correctly with ld but lld emits a warning
because .last_section section is not allocated as there are no matching
input sections and discards the `LONG()` call, meaning the last section
identifier will not be present in the flash.
> ld.lld: warning: ignoring memory region assignment for
> non-allocatable section '.last_section'
Placing the last section id in `.last_section` in C code makes lld
allocate the memory for the id and thereby create the output section
with the correct output.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
The SOC defconfig overrides CONFIG_KERNEL_ENTRY from the default of
__start to _vector_table. This is undesirable for cores such as M4 where
the _vector_table symbol has just raw addresses and no instructions. The
change was done to make sure Zephyr images can be loaded via remoteproc in
which case the entrypoint needs to be 64 byte aligned. To fix this, use
_vector_table as the ELF entrypoint only for R5 cores.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
esp32-mp.c calls z_sched_ipi() so it needs to include ksched.h,
as it is no longer included via kernel.h after removal of
kernel/internal/smp.h.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Port the nordicsemi_nrf53_init to use soc_early_init_hook instead of
SYS_INIT as SYS_INIT is legacy.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Intial support of pinctrl driver for Renesas RX MCU
family.
This support base on using Renesas RX driver package in
hal_renesas layer
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
for high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
Initial support of clock control driver for RX MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
The qemu-system-rx is based on RX62N, this commit added
support for the RX62N SOC layer. MCU is using RXv1 core and
system timer running at 6MHz
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
For npck3m8k:
1. Update code ram from 320KB to 416KB (0x1005_8000~0x100B_FFFF).
2. Update data ram from 32KB to 64KB.
3. Move fiudiv from hfcbcd1 to hfcbcd2 register
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace incorrect call to memc_flexram_dt_partition() with
flexram_dt_partition() to resolve build error on
IMXRT10xx and IMXRT11xx.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Configures AHBSC MASTER_SEC_LEVEL register for the cpu1 before cpu1 is
enabled. By default, this gives CPU1 secure and privileged access to
the rest of the SOC, same as CPU0.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Use `defaut y if` instead of `depends on` as the related Kconfig
should be user configurable even when standby mode is not used.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
0~12.
supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
interface 0~8.
supports 16 bytes dedicated FIFO mode that only supports write or
read mode and the maximum buffer size is 256 bytes.
support non-FIFO write to shared FIFO read mode. The maximum
shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
i2c_burst_write(), i2c_write_read()
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The buf_in_nocache function is to be used by various device drivers
to check if buffer is in noncacheable region.
The cacheable DMA buffer shall be put into section .ambiq_dma_buff
due to certain restrictions of the SoC.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
There is no need for kernel/internal/smp.h as SOF does not call
z_sched_ipi(). Actually... git log over there has no mention of
z_sched_ipi() anywhere, just arch_sched_ipi().
And include <ksched.h> for source using z_sched_ipi() since
they are using scheduling functions, and would be the correct
file to include.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This platform was previously using a default sys_arch_reboot
implementation which did nothing. Add an implementation which uses the
CRL_APB_RESET_CTRL register to initiate a soft reset (SRST) of the
device.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
MAX32657 is Cortex-M33 based Analog Devices MCU.
It supports ARM TrustZone security model.
There will be two boards of this MCU Secure and Non-Secure
This commit defines Secure version of peripherals.
Basic feature of MAX32657 device:
- Core is Cortex-M33
- 50MHz IPO clock
- There are 54 interrupt vectors
- 1MB flash & 256 SRAM
- MAX32657 has:
- 1 x UART
- 1 x I2C/I3C
- 1 x SPI
- 6 x TIMER
- 1 x RTC
- 1 x WDT
- 1 x TRNG
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
For simplicity/consistency with many other soc families, rename the
bouffalolab_bflb soc family to the simpler bflb.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
