Adds arch-level instruction memory API with functions
for memcpying / memsetting and determining whether a
region is in instruction memory. Implement API for
Xtensa and ESP32, with support for word granular access.
Adds definitions for instruction memory to
Xtensa ESP32 platforms.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/silabs/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The flash on the ch32v series starts at 0x8000000 and, depending on
the system configuration, is aliased to 0x0. PR #110383 fixed flashing
with minichlink by changing the flash Devicetree entry to point at the
flash base, not the alias, but this broke the boot.
Fix by updating the ch32v003 and ch32v00x vector.S to jump into flash.
This matches the behaviour of the other ch32v series startup code.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The previous table passed DT_CHOSEN_SRAM_ADDR directly as the MPU
region base with REGION_SRAM_SIZE derived from DT_CHOSEN_SRAM_SIZE
alone. This has two distinct failure modes:
1. Alignment fault: ARMv7-R requires base_address % region_size == 0.
With the ZynqMP RPU DDR alias at 0x100000 (1 MiB), the base is not
aligned to the 256 MiB REGION_SRAM_SIZE. The hardware silently
masks the low bits, so the effective region becomes 0x0-0x0FFFFFFF.
The linker places the stack at 0x10100000, outside that window,
causing Background Faults on every stack access near the top of RAM.
2. AMP isolation: in designs where the R5 application occupies a high
DDR partition (e.g. 0x50000000-0x7FEFFFFF), anchoring at 0x0 maps
Linux DDR (0x100000-0x4FFFFFFF) as R5-cacheable normal memory,
breaking cache coherency and AMP isolation.
Replace the fixed-base approach with a compile-time selection that,
for each candidate size (256M/512M/1G/2G), rounds DT_CHOSEN_SRAM_ADDR
down to the corresponding naturally-aligned boundary, then checks
whether base + size covers DDR_END = DT_CHOSEN_SRAM_ADDR +
DT_CHOSEN_SRAM_SIZE. The smallest fitting size is selected, giving
the tightest naturally-aligned single region.
Example outcomes:
SRAM=0x100000, SIZE=256M: base=0x00000000, REGION_512M (unchanged)
SRAM=0x50000000, SIZE=767M: base=0x40000000, REGION_1G
(vs old base=0x0, REGION_2G: 1 GiB of Linux DDR no longer mapped)
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Introduce SOC_XILINX_ZYNQMP_APU for ARM64 Cortex-A53 with MMU and
arm_arch_timer defaults. Build soc.c and arm_mpu_regions.c only for
the RPU variant; add ARM64 linker script for the APU.
Register zynqmp_apu in soc.yml and add dts/arm64/xilinx/zynqmp_a53.dtsi
with GIC-400 (GICD @ 0xf9010000, GICC @ 0xf9020000) and core PS
peripherals: UART0/1, TTC0-3 timers, and ARMv8 arch timer.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Create APLIC direct mode test cases to exercise APLIC with direct mode,
and include direct-mode QEMU in places where other qemu_riscv32 variants
are included.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Extend bflb_rf_init() to support WiFi mode (WL_API_MODE_ALL) with
TX power targets and country code configuration when CONFIG_BFLB_WIFI
is enabled.
Add WiFi platform glue: MAC ISR wiring, task creation, low-power
stubs, wl80211 RTOS primitives (heap, RNG, timers), and the linker
section for WiFi shared RAM.
Introduce CONFIG_BFLB_BL61X_WL_RMEM_SIZE for PHY/RF retention memory
sizing.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The AES CCM AD (Additional Authenticated Data) relies on
dynamic memory allocation, the heap memory pool size
must be greater than zero.
This commit sets the heap memory one block size when you
enable crypto with CCM support. This ensures that the crypto
sample can be built and run.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Add support for the WCH QingKe V3A SoC series (CH32V10x family),
including Kconfig, CMake, pinctrl, and interrupt vector table.
Register the series in soc.yml.
Signed-off-by: Lucy Wong <mova845@outlook.com>
Add initial SoC support for the Microchip SmartFusion2 M2S010
platform.
This commit introduces the SmartFusion2 SoC integration layer
required to enable platform initialization and Zephyr build
integration for the M2S010 family. The implementation includes
basic SoC initialization code, register definitions, Kconfig
integration, and build system support.
Signed-off-by: Anton Vynohradov <vynohradov.external@bavariamatic.com>
When application is running in xip from the nor flash controlled by
the xspi manager, prevent controller full re-initialization.
Tested with
west build samples/hello_world
-b stm32h7s78_dk/stm32h7s7xx/ext_flash_app
--sysbuild -p
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The sleeptimer service from the gecko_sdk is a generic API which supports
multiple hardware timer peripherals internally. The reason we want to use
this rather than a Zephyr native driver, is that sleeptimer is what's used
by the power_manager service from the SDK which in turn is used by librail.
Combined with other, future commits, this will allow reducing the power
consumption of gecko_sdk based SoCs while they are idle.
Since the APIs between gecko_sdk and simplicity_sdk are the same, all
that's needed is to adjust the Kconfig dependencies and compile the
relevant sdk code. For now, this supports the RTCC peripheral only, which
is used on efr32mg13p, which is what I test with.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Add a shared ETM channel allocator that routes a peripheral event to a
peripheral task in hardware. Gated by the new in-tree
ESP32_SOC_ETM_SUPPORTED capability.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Following commit 4b57150 where stm32mp133.dtsi has been introduced.
For compliance purpose, complete SoC configuration consequently.
Signed-off-by: Erwan SZYMANSKI <erwan.szymanski@st.com>
Without esp_clk_tree_initialize() the clock tree stays uninitialized
and esp_clk_tree_enable_src() is a no-op, so peripheral source clocks
are not brought up. Initialize it at boot, as done on esp32p4.
Signed-off-by: Sylvio Alves <sylviojalves@gmail.com>
This commit adds the necessary Kconfig for TF-M support on STM32U3.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Read the chip revision during hardware init and log a warning when the
silicon is older than the minimum configured through
SOC_ESP32P4_REV_MIN_FULL, so a revision mismatch is visible at boot.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Pre-v3 silicon places the L2 cache at the high end of HP SRAM, so
usable RAM starts at the SRAM base instead of after the cache, and the
ROM reserves its static data at a lower address. Select the SRAM origin
and the ROM-reserved boundary based on the configured revision so the
linker places code, data and stack in valid RAM on both pre-v3 and
v3.x parts.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The per-context interrupt threshold CSR mintthresh (0x347) only exists
on ESP32-P4 rev v3.0 and above. On pre-v3 silicon, accessing it in the
context save/restore path is an illegal instruction, which traps on the
first context switch and hangs the kernel. Guard the save and restore
of this CSR so it is skipped on pre-v3 builds.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add hidden SOC_ESP32P4_REV_* symbols (v1.3, v3.0, v3.1) and the
derived SOC_ESP32P4_REV_MIN_FULL integer so a board can declare the
minimum supported chip revision. The v3.x family floors at v3.1,
matching the reference SDK.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/openisa/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
CONFIG_LEGACY_GENERATED_INCLUDE_PATH is deprecated and no longer
enabled by default, so generated headers must be included with the
zephyr/ prefix. Fix the legacy <autoconf.h> include in the HiFi4
memory layout header so the SoC builds without the deprecated
compatibility option.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
CONFIG_LEGACY_GENERATED_INCLUDE_PATH is deprecated and no longer
enabled by default, so generated headers must be included with the
zephyr/ prefix. Fix the legacy <autoconf.h> include in the linker
script so the SoC builds without the deprecated compatibility
option.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a system timer driver for the NXP RTC (rtc_jdp) IP on the MCXE31x
family. It implements the standard system clock interfaces and is
selected through the zephyr,system-timer chosen property pointing at an
nxp,rtc-jdp node.
The RTC is a free-running 32-bit up-counter with a single absolute
compare register (RTCVAL); the driver runs tickless against it. Because
the RTC keeps counting in all low-power states, it can serve as the
kernel tick source without a companion timer.
RTCVAL is an equality compare that synchronizes into the slow RTC clock
domain and sets INV_RTC while in progress, during which further RTCVAL
writes are ignored. The driver waits for INV_RTC to clear before a write
and, after it, re-reads the counter and retries with the compare bumped
forward if the count has already reached it, so a match is never lost to
the sync latency (a miss would only recur after a full 32-bit wrap). The
scheduling horizon is capped at half the counter range so a compare
cannot wrap past the counter and look like the past, mirroring
mcux_stm_timer.c.
The counter rate (clock-frequency / prescaler) is published at runtime
via TIMER_READS_ITS_FREQUENCY_AT_RUNTIME, making the devicetree
prescaler the single source of truth for the tick rate. The MCXE31x SoC
defconfig disables SysTick and defaults the tick rate when this timer is
selected.
Validated on frdm_mcxe31b: tests/kernel/timer/timer_api passes 15/15.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The R5 cores in K3 platform devices have only a small amount of local
memory. For larger projects much of the code is intended to be placed in
DRAM. But DRAM is XN by default. If Zephyr code area is in DRAM then we
need to setup a simple MPU region to enable execute permissions before
jumping to the real Zephyr start code in DRAM.
If placing Zephyr in DRAM, keep a small stub in ATCM which does this.
This is only active when setting Zephyr to run from DRAM, it can
still be run entirely from ATCM if the application is small enough
to allow for that by leaving `zephyr,sram = &atcm;` in DT.
Signed-off-by: Andrew Davis <afd@ti.com>
Customer demand requires porting the MEC172x version 2 eSPI
driver to MEC174x/5x/165x. We must move the eSPI V2 headers
out of the MEC172x SoC directory into a common directory.
There are several other small changes due to register
differences in various hardware subystems such as PCR,
KBC-8042, QMSPI, etc.
We added old register structures and defines allowing eSPI SAF V2
driver to build. These will be removed in the future PR updating
eSPI SAF V2 to use Zephyr system register access inline functions.
We can then remove the difficult to maintain registe stuctures.
Signed-off-by: scott worley <scott.worley@microchip.com>
The ACE and CAVS Xtensa linker scripts never included the generated
snippets-data-sections.ld file, so any section registered through
zephyr_linker_sources(DATA_SECTIONS ...) was silently dropped. The new
ztest benchmark framework registers its iterable RAM sections this way,
which made benchmark tests fail to link with undefined references to
_ztest_benchmark_*_list_start/end on these SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
With the introduction of the DEVICE_MMIO facilities in the Xilinx GEM
device driver in #87313, the two static, identity-mapped MMU entries
for the register spaces of the two GEM instances defined at the SoC
level and processed when initially setting up the MMU page tables are
no longer used and no longer required for the driver to function.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/nuvoton/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/infineon/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
