Commit graph

6301 commits

Author SHA1 Message Date
Tim Lin
6114e6a381 soc: ite: it51xxx: Prevent floating FSPI pins by enabling tri-state
To prevent FSPI pins from floating, which may cause internal leakage
and increase SoC power consumption, tri-state is enabled by default.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-08-06 17:09:46 +03:00
Ren Chen
7ac7a0e0bd soc: ite: it8xxx2: increase sspi_clk and fix clock divisor setting
This commit raises the sspi clock from 24MHz to 48MHz and
corrects the clock divisor setting for it82xx2 chips.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
2025-08-06 12:16:19 +03:00
Ren Chen
4f413d85eb soc: ite: it8xxx2: disable sspi clock and automatic clock gating
This commits disables sspi clock and automatic clock gating.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
2025-08-06 12:16:19 +03:00
Daniel Baluta
21d2742ab9 soc: imx8m: adsp: Add NonCacheable linker section
There are some drivers like NXP SDMA that need a NonCacheable
data region to put data like channel control or buffer descriptors.

So far, we haven't added such a section because the linker created
one default orphan section at the end of the data section.

But this generates a warning in the build system:
xtensa-nxp_imx8m_adsp_zephyr-elf/bin/ld.bfd: warning: orphan section
NonCacheable' from modules/hal_nxp/libmodules__hal_nxp.a(fsl_sdma.c.obj)'
being placed in section `NonCacheable'

So fix this by explicitly define a NonCacheable area at the end of data
section.

This works because imx8mp cache attributes are
_memmap_cacheattr_imx8_wt_allvalid = 0x22212222
and the area where the NonCacheable section is allocated is
write-through.

So all the configuration for the SDMA core is not-cached at write.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2025-08-06 12:13:05 +03:00
Raffael Rostagno
916d67870d soc: esp32c2: Add BT support
Add bluetooth support to ESP32-C2 and ESP8684.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-08-06 12:10:59 +03:00
Daniel DeGrasse
aa0ff3cf4f soc: nxp: flexspi_xip: Update FLASH_MCUX_FLEXSPI_XIP ramload dependencies
CONFIG_FLASH_MCUX_FLEXSPI_XIP should also be disabled when using MCUBoot
ramload mode with revert support.

Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
2025-08-05 11:53:58 +01:00
Daniel DeGrasse
207211a00d soc: nxp: common: disable FLASH_MCUX_FLEXSPI_XIP if using ramload
MCUBoot RAMLOAD mode relies on CONFIG_XIP=n, but FLASH_MCUX_FLEXSPI_XIP
y-selects this symbol. Disable CONFIG_FLASH_MCUX_FLEXSPI_XIP for the
case where we are using MCUBoot ramload mode.

Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
2025-08-05 11:53:58 +01:00
Alvis Sun
dbc49f04d7 driver: bbram: npcx: update bbram status register bit offset for npck3
Update the bit offset of bit VCC_STS in the BKUP_STS register.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2025-08-05 10:25:09 +01:00
Sebastian Głąb
ee89450165 boards: nordic: nrf54l09pdk: Remove obsolete board
Board nrf54l09pdk was renamed to nrf54lv10dk.
Remove obsolete board definition.

Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
2025-08-05 10:24:48 +01:00
Sylvio Alves
2aca4ef0c2 soc: espressif: esp32c2: Enable deep sleep support
Adds support for deep sleep mode on the ESP32-C2 SoC, allowing
significant power savings.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-08-04 17:06:38 -04:00
Sylvio Alves
d03550255f soc: espressif: load RTC region into loader process
Only RTC DRAM area is currently being loaded during segment loader.
It means that RTC_IRAM and RTC_DATA is missing, causing
issues when sleep-modes are needed.

This also re-format the segments logging output
to meet with MCUBoot/Simple boot cases.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-08-04 17:06:16 -04:00
Marek Matej
fa1840268b scripts: update the CI requirements for Espressif port
Updated twister.yaml workflow to fetch esptool for the CI.
Fix format of the arguments used in the esptool-5.0.2.
Check that esptool is available on build time.
Update runners for esp32.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-08-04 17:02:52 -04:00
Sreeram Tatapudi
01972a1fcc soc: infineon: psc3: Adding folder structure for PSC3 series
Adding kconfig, and other soc files for PSOC Control C3 devices

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2025-08-04 19:57:57 +01:00
Vit Stanicek
8b1affbb49 soc: mimxrt798s/hifi4: Add soc.c
Add soc.c. Handle IRQ mapping (INPUTMUX) and clock setup.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-08-04 19:57:10 +01:00
Vit Stanicek
1a41cbc742 soc: mimxrt798s/hifi4: Rework linker and memory defs
Rename symbols so that they reflect purpose of defined memory regions.
Point region symbols to nodes in the DT. Move bogus IDT section before
DSP's ITCM. Move common ROM and RAM sections before the heap.

The move had to be done as these sections and the heap did overlap.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-08-04 19:57:10 +01:00
Vit Stanicek
7635d98bbb dt: mimxrt700_evk/hifi4: Add definitions
Add dummy interrupt controller, clock control, pin control, Flexcomm 0,
Flexcomm 2, SAI0, SAI1, SAI2 into SoC's DT. Enable relevant nodes in
board's DT and include pinctrl definitions. Add default LED and button
nodes. Set /hifi4's real frequency. Add memory nodes for device's main
SRAM.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-08-04 19:57:10 +01:00
Vit Stanicek
1521cb9bc8 soc: mimxrt798s: Expand definitions for /hifi4
Add desired Kconfig implications for the mimxrt798s/hifi4 domain. Add
pinctrl_soc.h and set up an include path for it.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-08-04 19:57:10 +01:00
Guennadi Liakhovetski
25f98c95a8 soc: intel: ace: fix GDB stub
A recent commit inadvertently broke GDB stub on ACE. Revert that
part of the faulty commit.

Fixes: commit cfd6a0673c ("SoC: Intel: ACE: remove unused litelals
parts in interrupt vectors")

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2025-08-04 19:55:57 +01:00
Sylvio Alves
350f322126 soc: espressif: disable default MCUBoot confirmed image generation
MCUBoot currently always builds the image as confirmed,
but image confirmation should be explicitly handled by the application
or subsystems.

This change disables the default behavior to avoid premature confirmation
during build time.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-08-04 19:54:25 +01:00
Yongxu Wang
969ff6fddf soc: nxp: imx93: fix system tick idle issue on m33
clear SLEEP_HOLD_EN bit to make sure m33 system tick
works fine in idle task

Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
2025-08-04 11:54:50 +01:00
Christoph Jans
9d06c38fff soc: silabs: Add support for efm32pg23 and efm32pg28
Introducing the efm32pg23 and efm32pg28 Series 2 Silabs chips.

Signed-off-by: Christoph Jans <jans.christoph@gmail.com>
2025-08-04 11:53:23 +01:00
Miguel Gazquez
5df200275d soc: riscv: sensry: Remove __soc_is_irq and disable unused config
The sy1xx SoC enabled CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ and provided
its own __soc_is_irq implementation. However, the behavior matches the
default implementation, making the override unnecessary.

This commit removes the custom implementation and disables the config
option to remove unnecessary code.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2025-08-04 11:51:36 +01:00
Miguel Gazquez
022723752b soc: riscv: wch: Remove unused __soc_is_irq function
The __soc_is_irq function is only used when
CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ is enabled, which is not the case
for any WCH SoC. The implementation is therefore dead code.

Additionally, the implementation matches the default fallback behavior,
so no functional change would occur even if the config were enabled.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2025-08-04 11:51:36 +01:00
Neil Chen
4e2b0cdf05 boards: frdm_mcxa153, frdm_mcxa156: add ostimer support
1. add ostimer support
2. update ostimer as default kernel timer

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2025-08-02 13:18:46 +02:00
Camille BAUD
bdffc08279 bflb: Make BL60x independant from SDK
Reorganize and update soc folder files for SDK-independance
Reorganize and update hal_bouffalolab files for SDK-independance
Reorganize and update soc dts files for SDK-independance
Update serial and pinctrl driver files for SDK-independance
Update ai_wb2_12f, bl604e_iot_dvk, and dt_bl10_dvk
to new bl60x support
and fixup openocd config of ai_wb2_12f

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-01 07:57:36 -04:00
Camille BAUD
0c352f1b3a soc: bflb: re-add ATOMIC_OPERATIONS_C
This reverts 514258aa23
which causes issues here

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-01 07:57:36 -04:00
Fin Maaß
56bf288ed8 soc: litex: add array functions to soc.h
adds functions to read and write arrays to the soc.h file.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-08-01 07:55:01 -04:00
Fin Maaß
5a0fba3b9d soc: litex: support little CSR ordering
litex supports little CSR ordering, also support
it in zephyr. historical the default is big ordering.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-08-01 07:55:01 -04:00
Fin Maaß
0a2140589a soc: litex: check CONFIG_LITEX_CSR_DATA_WIDTH
Litex only supports CONFIG_LITEX_CSR_DATA_WIDTH
with 8 and 32 bit, enforce it here too.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-08-01 07:55:01 -04:00
Fin Maaß
456bfbff5d soc: litex: use generic data types
use generic data types

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-08-01 07:55:01 -04:00
Fan Wang
7ea280466b drivers: sdhc: Add support for Apollo510 SDIO host
This commit added support for Apollo510 SDIO host driver and
ambiq board configuration in fs_sample and disk_performance

Signed-off-by: Fan Wang <fan.wang@ambiq.com>
2025-07-31 17:16:12 -04:00
Vit Stanicek
e679ef486a hal_nxp: Factorise inclusion of fsl_inputmux
Create Kconfig variable NXP_INPUTMUX, which selects the fsl_inputmux
driver. Imply the MCUX component symbol from it. Imply that variable
from the NXP PINT, SmartDMA and LPC DMA drivers and from the mimxrt685s
SoC.

This needed to be done for the mimxrt700_evk/mimxrt798s/hifi4 domain, as
the INPUTMUX peripheral handles IRQ assginments and its driver
(fsl_inputmux) is used directly by the domain's soc.c. Instantiating the
currently dependent drivers (for PINT and SmartDMA) isn's possible nor
reasonable on the said target.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-07-31 17:11:54 -04:00
Karsten Koenig
130625e737 soc: nrf54h: Configure CTRLSEL and pin for TRACE
Configure the CTRLSEL value and the clock pin so that the TRACE pins
work when the TDD gets used.

Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
2025-07-31 07:41:53 -04:00
Karsten Koenig
7c813bf00f soc: nordic: ironside: Add TDD
Added support for the IronSide TDD service which allows configuring and
powering the trace and debug domain of the nrf54h20.
Also provide option to start the trace and debug domain in the soc start
sequence.

Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
2025-07-31 07:41:53 -04:00
Karol Lasończyk
8f2d3e7623 soc: nordic: Extend address validation to cover GPREGRET
Extension of the validate_base_addresses.c file to cover GPREGRET
in all Nordic SoCs.

Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
2025-07-31 10:53:43 +01:00
Dmitrii Sharshakov
cbe6a716d3 soc: rp2350: add IMAGE_DEF using rom_start linker script
Use this approach for a simpler flow and to make relocation of images
into RAM easier.

Also do not force-select CONFIG_XIP (which is a default anyway), since
RP2350 can boot from SRAM.

Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
2025-07-31 10:50:41 +01:00
Mike J. Chen
2dc6793261 soc: imxrt5xx: add fusion f1 dsp backtrace support
Add needed backtrace helpders routines and enable
backtrace for the Xtensa Fusion F1 DSP in the
IMXRT595S.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2025-07-31 10:49:54 +01:00
Sadik Ozer
10b3fe8d1c soc: arm: adi: MAX32657 add HAS_PM flag
Add HAS_PM flag to enable power management for MAX32657

Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2025-07-30 17:25:03 -04:00
Tahsin Mutlugun
add6eb6726 soc: adi: max32: Use ceiling method to calculate exit latency ticks
The default 'near' mode results in zero exit latency ticks, which
prevents `sys_clock_set_timeout` from being called. This causes
the system to remain stuck in deep sleep modes. Use ceiling method
to obtain a nonzero exit latency tick count.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
2025-07-30 17:25:03 -04:00
Swift Tian
814ed6803f tests: fix arm_irq_vector_table fail on Ambiq platforms
Fixed build fail since 4c93fcd35b.
Fixed test run fail on Ambiq platforms.
Added Ambiq section in the test.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2025-07-30 07:27:19 -04:00
Bjarki Arge Andreasen
2854115443 soc: nrf54h: remove deprecated gpd (global power domain) driver
Remove the deprecated GPD (Global Power Domain) driver.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2025-07-29 09:03:37 -04:00
Bjarki Arge Andreasen
2b0d1ae4d0 soc: nordic: nrf54h: transition from gpd to zephyr pinctrl and pds
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.

The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2025-07-29 09:03:37 -04:00
Adrian Warecki
0fe396cb11 ace: mmu: Add shared heap section
Add a new shared_heap section. Update the xtensa_soc_mmu_ranges structure
to include a new memory range for the shared heap.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2025-07-29 11:21:21 +01:00
Jiafei Pan
2d62d3f605 soc: imx95: a55: enable GIC redistribute and its noncoherent
GIC redistribute and ITS on i.MX 95 is DMA noncoherent, so enable
CONFIG_GIC_V3_RDIST_DMA_NONCOHERENT and CONFIG_GIC_V3_GIC_DMA_NONCOHERENT.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-07-29 11:18:50 +01:00
Jiafei Pan
353a96b623 soc: imx95: a55: include LPI in irq number
In case of ITS is enabled, need to include LPI in the total number
of irq.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-07-29 11:18:50 +01:00
Yishai Jaffe
7f3a728aaa soc: silabs: s2: make order in soc Kconfig's
Made some order in the Kconfig's for silabs series 2 socs.
Made a distinction between silabs "generic family" (e.g. xg21) and silabs
"device family" (e.g. efr32mg21).

Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
2025-07-28 16:40:58 -04:00
Alberto Escolar Piedras
6d8ad26868 soc/Kconfig: Move SOC_COMPATIBLE_NRF* options to soc/nordic/Kconfig
Since the change to HWmv2 we do not need to have this options in the
top level anymore. Let's move them into the top level Nordic SOC
Kconfig file.
(Note they moving into into each individual soc Kconfig would
add a dependency on SOC_FAMILY_NORDIC_NRF which is not set for
bsim targets)

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2025-07-28 08:35:13 -04:00
Alberto Escolar Piedras
13c8a51227 soc/nordic/nrf53/Kconfig.soc: Fix typo
Just a copy paste typo

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2025-07-28 08:35:13 -04:00
Alberto Escolar Piedras
d9b130823a soc: nordic: nrf54l: Set SOC_COMPATIBLE for 54L15 CPUFLPR target
So we can use just SOC_COMPATIBLE_NRF54L15 in place of
SOC_NRF54L15

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2025-07-28 08:35:13 -04:00
Michał Bainczyk
2e06c4ed20 drivers: nrf: add build asserts for memory-regions property
Add build asserts for "memory-regions" property in nrf drivers which is
required on targets with DMM for saadc, pdm, pwm, twim, twim_rtio, twis,
tdm, uarte, spim and spis. On targets where the property is not required
the assertion macro expands to nothing.

Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
2025-07-28 04:27:25 -04:00