Select RISCV_PMP on the esp32c5 hpcore so it can run user mode,
and lay out the PMP regions the userspace model needs under
MPRV.
Align the flash-mapped and IRAM/DRAM boundaries to the PMP
granularity and size the ROM entry to a single NAPOT slot. Keep
the IRAM text and flash rodata as SoC regions, visible to both
modes. The CPU subsystem and peripheral windows get no entry:
kernel accesses are covered by the kernel-mode catch-all, and
user threads must not reach them.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
External allocator client is used on flpr or ppr which has only a single
IPC connection. Use single IPC node instead of expecting ipc0 label.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Drop the espressif/<soc>/<soc>_<module>.dtsi files in favor of one
<soc>.dtsi per SoC, and matching SOC_ESP32*_<MODULE> symbols in
favor of the plain SoC symbol. SOC_PART_NUMBER now reports the SoC.
Each board instead states its own flash, giving both reg and ranges
because the SoC dtsi no longer sets either, and its own psram size where
it has one.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add a coredump backend for the AMD ACP DSP that stores the Zephyr
coredump together with a SOF compatible DSP "oops" record in the ACP
exception buffer. The backend writes the panic code where the SOF host
driver expects it and raises a DSP-to-host interrupt so the host can
collect the dump.
Enable ARCH_SUPPORTS_COREDUMP for the acp_7_x SoC and wire the new
backend into the coredump core and build.
Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Replace direct NVIC_ClearPendingIRQ() calls with
k_irq_clear_pending(). The raw NVIC ISPR/ISER wake-source scan in the
psoc4100tp power code stays as-is: there is no portable
"any interrupt pending" query.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add device tree and SoC definitions for the remaining Cortex-R5F
cores on the TI J721e SoC (MAIN R5FSS0 core 1, MAIN R5FSS1 cores 0
and 1, and MCU R5FSS0 cores 0 and 1).
Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
Add PSC3M6 as a die under SOC_SERIES_PSC3 in cat1b/psc3/: Kconfig
entries, NUM_IRQS and null-pointer-detection overrides, and the
secure SRAM/noinit handling.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Signed-off-by: Niranjan M <niranjan@aerlync.com>
Add Hexagon DSP architecture support to Zephyr RTOS, targeting the
Qualcomm Hexagon V67+ ISA running as a guest under the H2 hypervisor.
This includes:
- Architecture scaffolding (Kconfig, CMakeLists, arch selection)
- Public headers (arch.h, thread.h, exception.h, error.h)
- Core runtime: context switch, interrupt/exception handling, idle, TLS
- Memory management stubs for flat-memory H2 guest model
- SoC support for QEMU hexagon virt machine
- CMake/LLVM toolchain integration for hexagon cross-compilation
Hexagon uses H2's GEVB (Guest Event Vector Base) for interrupt dispatch
rather than a traditional function-pointer vector table, so
GEN_IRQ_VECTOR_TABLE is disabled by default.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
A window was only reported when a fragment woke within the sleep floor of
its deadline, but a real sleep can wake earlier than that, so on some
configurations no window was reported at all. Close the window on the RTC
timer wake instead, and keep the time left to the deadline to close a wait
that never slept.
Assisted-by: Claude:opus-5
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Added support for Infineon's CAT1C based CYT4DN series SoC.
CONFIG_GEN_IRQ_VECTOR_TABLE is disabled because gen_isr_tables.py
sizes the hardware vector table to the multi-level CONFIG_NUM_IRQS.
This would result in unnecessary flash consumption and excessive
VTOR alignment padding. A static 16-entry table matching the physical
Cortex-M NVIC lines is provided instead.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
Signed-off-by: Alexpandi Muniyandi <alexpandi@linumiz.com>
The drom0 segment origin sat at 0x42800000 although instructions
and data go through one unified flash cache window that starts
at 0x42000000. The memory mapper reserves irom_len + drom_len
linear bytes from the window start, so the gap between the two
mappings was not accounted for and a later mapping could land
on rodata.
Place drom0 at the irom origin and add a .flash_rodata_dummy
section so rodata is emitted right after the aligned text span.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The drom0 segment origin sat at 0x42800000 although instructions
and data go through one unified flash cache window that starts
at 0x42000000. The memory mapper reserves irom_len + drom_len
linear bytes from the window start, so the gap between the two
mappings was not accounted for and a later mapping could land
on rodata.
Place drom0 at the irom origin and add a .flash_rodata_dummy
section so rodata is emitted right after the aligned text span.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The load header leaves .rtc.force_fast and .rtc.force_slow
uncopied, so statics kept there come up as garbage under
MCUboot. On top of that .rtc.force_slow was linked into
rtc_iram_seg, placing RTC_SLOW_ATTR data in RTC fast memory.
Move .rtc.force_slow into rtc_slow_seg where it belongs, ahead
of the NOLOAD sections. Make .rtc.dummy NOLOAD so .rtc.text
and .rtc.force_fast stay adjacent in flash and span the
RTC_IRAM descriptor across both through the instruction bus
alias of RTC FAST memory, and span the RTC_DRAM one across
.rtc.data through .rtc.force_slow. Keep _rtc_slow_length
covering the whole slow area through a new _rtc_noinit_end
symbol, since the sleep code uses it to decide RTC slow memory
retention on this SoC. Mark the loadable sections
ALIGN_WITH_INPUT and assert that each span keeps equal
physical and LMA offsets.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The load header leaves .rtc.force_fast and .rtc.force_slow
uncopied, so statics kept there come up as garbage under
MCUboot. The wake path reads state from RTC fast memory, so
this also leaves the chip resetting through the timer group
watchdog on every deep sleep wake.
Make .rtc.dummy NOLOAD so .rtc.text and .rtc.force_fast stay
adjacent in flash and span the RTC_IRAM descriptor across both
through the instruction bus alias of RTC FAST memory. Span the
RTC_DRAM descriptor across .rtc.data through .rtc.force_slow,
moved ahead of the NOLOAD sections. Keep _rtc_slow_length
covering the whole slow area through a new _rtc_noinit_end
symbol, since the sleep code uses it to decide RTC slow memory
retention on this SoC. Mark the loadable sections
ALIGN_WITH_INPUT and assert that each span keeps equal
physical and LMA offsets.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The load header describes only .rtc.text and .rtc.data, so
.rtc.force_fast and .rtc.force_slow sit in the flashed image
but are never copied. Statics kept there come up as garbage
under MCUboot.
Span the RTC_IRAM descriptor across .rtc.text and
.rtc.force_fast and the RTC_DRAM one across .rtc.data through
.rtc.force_slow, and move .rtc.force_slow ahead of the NOLOAD
sections so each span stays contiguous. Mark the loadable
sections ALIGN_WITH_INPUT and assert that the VMA and LMA
spans agree.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Update the hal_stm32 module to the latest revision, which requires some
changes on the Zephyr side:
1) The Kconfig option STM32CUBE_SOC_NAME_OVERRIDE is now used verbatim.
A few SoC Kconfig files which set the option need to be updated as they
expected the HAL to perform some transformations. This changes allows
getting rid of a hack in the STM32WL3 Kconfig, which was the goal.
2) The Ethernet pinctrl nodes for STM32H5 series (except H5Ex/H5Fx) have
been updated to match the Data Sheet names. This requires updating the
DTS of some boards to match the new names.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add CONFIG_ADVC_DRIVER_USED to opt into the NXP ADVC (Adaptive
Voltage Control) driver on MCXL255. Defaults to off, no behavior
change for existing builds.
Wire it into the mcux-sdk-ng build: pull in fsl_advc.c/.h directly
and link libadvc_cm33.a / libadvc_cm0p.a from their west-blobs
location (zephyr/blobs/mcxl255/). The driver.advc component is not
enabled, since its auto-synced CMakeLists.txt would also link the
same libs from a nonexistent device-tree path.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Add the MCXL OSTIMER0 devicetree node and make the MCUX OS
timer driver selectable for MCXL25x CPU0 targets.
OSTIMER0 is disabled by default. When MCUX_OS_TIMER is selected, SysTick
is disabled and the system clock rate is set to the OSTIMER clock rate.
Signed-off-by: Samuel Slesar <samuel.slesar@nxp.com>
Addd the possible st,nor compatible on a MSPI XSPI bus
for executing code in external application on a stm32 device
Signed-off-by: Francois Ramu <francois.ramu@st.com>
soc_early_init_hook() is a generic Zephyr SoC API, called automatically
by the kernel during a normal Zephyr boot. TF-M's
platform/ext/target/nordic_nrf/common/core/target_cfg_71.c also needs
this same hardware bring-up to run during the Secure boot, which never
goes through Zephyr's kernel init and so never calls the hook
automatically and has to call the function by name instead.
Because target_cfg_71.c declared its own prototype for
soc_early_init_hook() rather than sharing a header with this file, and
TF-M's standalone fallback in nrf71_init.c happened to reuse the same
name with a different (int) signature, the two independent
declarations of the same symbol silently disagreed. The compiler
cannot catch this across translation units, so it went undetected
until it caused TF-M to read an uninitialized register as a bogus
error code and panic on every boot, before any log output was even
possible.
Extract the actual init logic into a new, TF-M-specific function
nordicsemi_nrf71_init(), matching the pattern already used by nRF54L
(nordicsemi_nrf54l_init()). soc_early_init_hook() becomes a thin
wrapper that just calls it, so Zephyr's normal boot is unaffected,
while TF-M can now call nordicsemi_nrf71_init() by a name that isn't
also a generic Zephyr API with its own, unrelated contract.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
The Bluetooth host requires the Cipher module (AES-ECB) for Resolvable
Private Address (RPA) generation, and AES-CMAC for Security Manager (SMP)
pairing (LESC).
Since TF-M's profile_medium disables these by default, and Zephyr's TF-M
CMake integration cannot pass arbitrary PSA algorithm overrides down into
the tf-psa-crypto build, this commit intercepts the TF-M build by setting
TFM_TF_PSA_CRYPTO_PLATFORM_EXTRA_CONFIG_PATH to a board-specific header
that force-enables the necessary modules. This is done from the SoC
CMakeLists.txt to avoid out-of-tree modifications to the vendored TF-M
repository.
Signed-off-by: Vignesh Pandian <vignesh@aerlync.com>
Add full poweroff with wakeup pin support on STM32U3.
Also enable the selection of the power supply now that the pwr node is
added in dtsi.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32U3 uses a different terminology than other series, defining wake up
lines instead of wake up pins. As such, several functions need to be
redefined.
Adapt the pwr_wkupctrl driver to support STM32U3.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add the support of ICACHE in the STM32U3 SoC Kconfig, and add the line size
in the device tree.
No need to change anything in soc_early_init_hook because cache is already
enabled here (but was doing nothing until now).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The Espressif SoC sysbuild fragment forced MCUboot into
overwrite-only mode, which leaves no image to revert to, and the
bootloader Kconfig still preferred the older swap using move for
the family. Remove both so these SoCs get swap using offset like
every other target, and document the change in the migration
guide.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When CONFIG_ESPRESSIF_QEMU is set, publish the SPI flash size and
partition offsets as global properties for the espressif_qemu emu
platform that assembles flash_image.bin.
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
Add CONFIG_SOC_ESP32_PM_SLEEP_STATS to log one line per completed light
sleep window with requested/executed time, fragment count, power-domain
tags and sleep-call result. Helps evaluating sleep config and health on
test environments.
Expose API call to fetch data from the latest completed sleep window.
Assisted-by: Grok:4.6
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Drop compile-time patch address macros and use devicetree addresses.
Wi-Fi patch addresses will be updated by overriding WICR node.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
esp32_lptim_hook_get_freq() returned systimer_us_to_ticks(1) * 1e6, which
truncates the fractional 10.4 ticks/us rate on ESP32-C2 (26 MHz XTAL /
2.5) to 10. Convert a full second instead, so post-sleep kernel time
compensation matches LP timer.
lpm_counter_ticks_per_us() truncated the same rate and skewed the
pre-sleep elapsed time used to lead the LP wake. Both call sites now
share a single ticks-per-second helper, so the rate is converted in one
place only.
Assisted-by: Grok:4.6
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Rework the sleep path timing calculation to improve precision by
calculating sleep time and wakeup margins with the right time
references.
When CONFIG_ESP32_PM_SLP_IRAM_OPT is enabled, the early wake path
(RTC timer re-enable, GPIO restore, and post-exit ops) is also
placed in IRAM so resume does not refill from flash after CPU
power down.
Light sleep DT exit-latency-us is 0 so PM does not shorten the
budget; the RTC lead is applied in power.c. C5 keeps flash powered
in light sleep via SOC_ESP32_PM_FLASH_KEEP_POWER_IN_LSLP.
Assisted-by: Grok:4.6
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Rename the STM32MP15 Cortex-M4 SoC Kconfig symbol from the generic
SOC_STM32MP15_M4 to the silicon-specific SOC_STM32MP157CXX_M4, and update
its in-tree users (96b_avenger96, stm32mp157c_dk2 and the OSD32MP15x
SiP). The associated Kconfig.defconfig fragment is renamed to match.
This is a pure Kconfig symbol rename: no devicetree, board target or
functional change.
Signed-off-by: Richard Gudino <richar_1321@hotmail.com>
Assisted-by: Claude:claude-opus-4-8
RTC_GetWakeupCount() and RTC_SetWakeupCount() are declared in
fsl_rtc.h, which power.c only includes when the standby DT node
is enabled. The calls in the PM_STATE_STANDBY case were not
guarded by the same condition, so any build without the standby
node compiled them with no declaration in scope, producing
"implicit declaration of function" errors.
Wrap the wakeup-count adjustment in the same standby guard used
for the fsl_rtc.h include and the RTC_ClearStatusFlags() call,
so the RTC symbols are only referenced when the header is
present. This fixes the build for frdm_rw612 and rd_rw612_bga
targets that do not enable the standby node.
Fixes: #117797
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Add the .resource_table linker section for RZ/G2L and RZ/G2UL so the
OpenAMP resource table is kept in the image.
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
mimxrt758s and mimxrt735s were only pre-declared as
SOC_PART_NUMBER_MIMXRT758SG*/MIMXRT735SG* order-code bools under the
single mimxrt798s SoC, with no SOC_MIMXRT758S/SOC_MIMXRT735S symbol,
no soc.yml entry, and no dedicated cpucluster Kconfig of their own.
Give both parts full SoC-level presence mirroring mimxrt798s exactly:
a soc.yml entry with the same cm33_cpu0/cm33_cpu1/hifi4/hifi1
cpuclusters, SOC_MIMXRT758S/SOC_MIMXRT735S Kconfig symbols plus their
per-cpucluster variants in Kconfig.soc, the matching add_subdirectory
selection in CMakeLists.txt, and the cm33/hifi1/hifi4 subdirectory
Kconfig/Kconfig.defconfig/soc.h guards extended to the new symbols.
No board currently targets either new SoC, so this is groundwork only;
the existing mimxrt798s configuration and behavior are unchanged.
Signed-off-by: Wei Feng <wei.feng_5@nxp.com>
SystemInit() enables the RAM banks that are off out of reset, but its own
prologue writes to the stack before it gets there, which fails when the
stack lives in one of those banks. Ungate them in soc_reset_hook() and
tail-call SystemInit(), so neither step touches the stack. The function
has to be naked, or a prologue would run before the store.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
LPC54XXX_SRAM2_CLOCK names one bank, but controls every bank SystemInit()
enables, which on the LPC546xx is SRAM2 and SRAM3. Rename it to
SOC_SERIES_LPC54XXX_SRAM_CLOCKS: the option applies to the whole series,
and the Kconfig style guide asks for a SOC_SERIES_ base in that case.
Assigning the old symbol now fails the build, so a configuration that set
it is told rather than silently changed.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
The .metadata load header emitted for MCUboot builds describes only two
of the four loadable LP-SRAM sections. Its LP_DATA descriptor points at
.rtc.data, which collects RTC_DATA_ATTR / RTC_RODATA_ATTR and is empty in
any application that does not use those attributes, while .rtc.force_fast
and .rtc.force_slow are described by no descriptor at all. Both are
present in the flashed image but never copied, so the zero-initialised
ESP-IDF statics they hold come up as whatever LP-SRAM last contained.
On ESP32-C6 that leaves s_sleep_sub_mode_ref_cnt[] (sleep_modes.c) with
garbage reference counts. get_sleep_flags() then reports the ADC/TSEN
monitor, ultra-low and RTC-fast-uses-XTAL sub-modes as active, so
esp_deep_sleep_start() keeps the LP peripheral domain powered and skips
sar_periph_ctrl_power_disable().
On a Seeed XIAO ESP32-C6, with a PPK2 into the BAT pad at 3700 mV and
time-averaged over the deep-sleep gaps, the floor measured 92.94 uA
under MCUboot against 12.56 uA booted directly, and 11.84 uA under
MCUboot once this change is applied. Absolute figures are
board-specific; the relative change is the point.
Point the LP_DATA descriptor at .rtc.force_fast through .rtc.force_slow,
and move .rtc.force_slow ahead of the NOLOAD .rtc.bss / .rtc_noinit
sections so the four loadable LP sections are adjacent in both VMA and
LMA. The reorder is required, not cosmetic: correcting the descriptor
alone leaves .rtc.force_slow displaced by any non-empty NOLOAD section,
so the loader writes it to the wrong address and overwrites
.rtc.bss / .rtc_noinit in the process.
Mark the four loadable LP sections ALIGN_WITH_INPUT so that an
over-aligned input section pads the load address the same way it pads
the virtual address, which is what keeps the descriptor's span valid
once RTC_SLOW_ATTR data is present, and assert that the VMA and LMA
spans of .rtc.force_fast through .rtc.force_slow agree so that a future
change cannot silently reintroduce the skew.
Applies to the SoCs whose LP sections all share one memory region:
esp32c3, esp32c5, esp32c6, esp32h2 and esp32p4. esp32s3 splits them
across rtc_iram_seg and rtc_slow_seg, where .rtc.force_fast would land
in the unconditionally loaded LP_IRAM descriptor and lose its
deep-sleep retention; esp32 and esp32s2 have three distinct regions
against two descriptors and need a third one. Both are left for a
separate change.
Fixes#118246
Assisted-by: Claude:claude-opus-5
Signed-off-by: Martin Drinnan <mrdrinnan@gmail.com>
Add DEVICE_DT_INST_GET_COMMA helper macro to include/zephyr/device.h to
easily get a device pointer followed by a comma when expanding
devicetree foreach iterators like DT_INST_FOREACH_STATUS_OKAY.
Update drivers, soc, subsys, and tests to use the common definition.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Assisted-by: Antigravity:gemini-1.5-pro
Move the STM32 NeoChrom GPU2D driver out of drivers/misc and
store it instead into soc/st/stm32/common since it is specific
to STM32 SoCs.
While moving it, rename the config from NEOCHROM_GPU2D into
STM32_NEOCHROM_GPU2D to match with other STM32 configs.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The gpio and pinctrl drivers each open-coded the split of an
absolute pad number into a Zephyr gpio port and pin index. Move
it into one header in the common soc folder and use it from
both, so the next pad user cannot get the split wrong. The
pinctrl copy was a no-op because its pad numbers are already
absolute, so it is dropped.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a default y for CONFIG_HDLC_RCP_IF when NET_L2_OPENTHREAD is
selected on the RW6xx SoC family. This mirrors the default already
present in the Matter chip-module Kconfig.defaults and ensures that
standalone OpenThread builds on RW612 have a consistent Kconfig state.
Without this change the symbol was left unset in Kconfig even though
the connectivity framework middleware pulled in the HDLC driver through
a side-channel, leading to a misleading menuconfig view.
Signed-off-by: Baptiste Coffin <baptiste.coffin_1@nxp.com>
Rename the ESP32_SOC_* capability symbols to SOC_ESP32_* so
that symbols defined under the soc folder follow the Zephyr
Kconfig naming policy. Update all references in the common
soc code and in the counter and bluetooth drivers.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add set_pdm_clock() to configure the PDM clock:
- parent = AUDIOPLL1, rate = 196.608 MHz
The AUDIOPLL1 chain is shared with SAI via set_audiopll1_clock(),
which is guarded by both nxp_mcux_i2s and nxp_micfil. SAI and PDM
clock setup functions are each guarded by their own compat check.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
