CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h',
allowing other SoCs using the CVA6 core to reuse the same CSR definitions.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to
'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Egis ET171 implements Andes custom CSRs. Enable the following features:
1. Low level initialization of Andes CSRs
2. HWDSP and PowerBrake extensions with context save/restore
3. EXEC.IT extension
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
TLSR951x also supports Andes extended CSR. Reworks the following CSR
handling to use the RISC-V custom CSR common code:
1. Use common macros for HWDSP CSR context save/restore.
2. Use common macros for PFT CSR context save/restore.
3. Use common low-level CSR initialization via __reset hook.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Rework Andes-specific CSR to use RISC-V custom CSR common code.
Move these stuff to 'arch/riscv/custom/andes':
1. Rename 'soc_v5.h' to 'andes_csr.h' for CSR definitions.
2. Replace '_start' with '__reset' hook for low-level CSR initialization.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move 'EXECIT' CSR support to common code.
5. Move PMA CSR driver to common code.
6. Use RISC-V common linker.ld instead of SoC-specific linker.ld.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Apply the same CONFIG_ESPI_IT8XXX2 guard to the .h2ram_pool section
in the IT51XXX linker script, since the eSPI driver is compatible with
IT8XXX2. This keeps linker behavior consistent and avoids unused
memory allocation on non-eSPI platforms.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The .h2ram_pool linker section was previously always included, even on
platforms that do not enable eSPI. This caused unnecessary memory
reservation in the RAMABLE_REGION for non-eSPI configurations.
Add a CONFIG_ESPI_IT8XXX2 guard around the .h2ram_pool section definition
so that it is only included when eSPI support is enabled.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Limit the loop to the smaller of nvic_iser_nb and
GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT to ensure safe access.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
The CONFIG_BUILD_NO_GAP_FILL option became obsolete after commit
2e8868c16e and has since been deprecated.
Remove the unused Kconfig select from the CC23x0 SoC configuration.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Use cpuapp_slot_partition instead of slot0_partition, so it is possible
to add MCUboot header through --pad-header option.
In such cases, the FLASH_LOAD_OFFSET does not point to the begining of
the slot, but to the beginning of the executable area, thus the check
for the active slot should use ranges instead of exact values.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Use sleep mode instead of Low Power Mode (LPM). LPM is
similar to deep sleep, not intended to be used for general
idle.
Signed-off-by: Kevin Gillespie <Kevin.Gillespie@analog.com>
This commit adds eSPI TAF support for npck3, including initialization
settings for flash operation mode. It also updates the mechanism to
release FLASH_NP_FREE, preventing a possible race condition between
automatic and standard requests.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
This commit adds eSPI support for npck3, including support for the
maximum frequency of 66MHz. The method to read the level of eSPI reset
pin differs on npck3, so the definition of eSPI_RST has been updated
accordingly.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This allows a project to select where cpu_freq_pstate_set()
gets implemented. The system integrator may choose to use
a default stub, a version implemented by the SOC, or a custom
version implemented by the project.
The existing 'native' SoC version now has its output contain
the string "SoC" while the new stub version has the string
"Stub" in its. This allows a means to differentiate between the
two.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
MCUBOOT requires LTO to be enabled, while using code relocation
forces switching it off. When `__ramfunc` is used, LTO can also
be used. Then the `cache_retain_and_sleep` function will work
correctly, but slightly slower.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Retrieve the value of SYS_CLOCK_HW_CYCLES_PER_SEC from the osc node in
the RZ/A3UL devicetree.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Set SL_SI91X_BT_BLE_STACK_BYPASS_ENABLE in ble_ext_feature_bit_map to
support host-driven BT/BLE stack operation on SiWx91x devices.
When enabled:
- Events are delivered directly to the host, bypassing internal stack
processing
- Ensures critical events like CARD_READY reach the host reliably
- Allows external host stack to control BT/BLE operations
- Provides more memory to the application, as the internal stack is
bypassed
This change enables direct event packet delivery from the firmware event
handler, ensuring proper operation when the internal BT stack is
bypassed.
Required for BT/BLE tester and host-controlled stack configurations.
Signed-off-by: Arun Kumar Nagelly <arnagell@silabs.com>
Add configuration for BLE
Add 32KHz Osc clock needed by BLE
Move nxp_nbu.c include to be shared on mcxw7x and mcxw2x
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Both MCXW2xx and MCXW7xx now share the same SoC family
(CONFIG_SOC_FAMILY_MCXW).
Isolate mcxw7xx-specific module/code from mcxw2xx.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
This is a SOC based on AE350. In addition to the core, some
modifications have been made to the peripheral functions,
including the integration of built-in USB.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
Added driver and bindings for the coresight nrf submodule.
add integrated it for the nrf54h20.
The coresight subsystem is a combination of ARM Coresight peripherals
that get configured together to achieve a simplified configuration based
on a desired operating mode.
This also replaces the previous handling in the nrf54h20 soc.c which was
powering the subsystem up but not configuring it.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Pinctrl needs to set the needed drive and direction of the pins. Also
this later allows automatically setting the clock bit for the traceclk
pin.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Moved the nrf_etr driver from the drive/misc folder into the recently
established driver/debug folder where it is a better fit. Moved the
associated files such as bindings and headers accordingly as well.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
This commit introduces a new function to verify the firmware version of
the SiWX917 network coprocessor. It checks the expected version (updated
manually after each bump of Wiseconnect SDK in hal_silabs) against the
actual version retrieved from the device.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Enable support for latest GINF method which requires 3 paramters
for each GPIO group and enables gpio support for intel_ptl_h
platform.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Retrieve the value of SYS_CLOCK_HW_CYCLES_PER_SEC from the osc node in
the RZ/N2L, T2M devicetree.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add a first region in the MPU to disable all access to the whole
memory range. With that ensure that the MPU will block all
access to regions that aren't defined in further regions.
Ensure as well that the peripheral area is accessible.
This handles the errata 2.1.1 PLD might perform linefill to address
that would generate a MemManage Fault of the STM32H7Rxx / STM32H7Sxx
device errate ES0596 - Rev 6.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The update will fail if the address is outside of this range.
This failure might trigger a bad state where the device is
non-trivial to recover.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
Move the option to force constant latency mode outside of nRF54l, since
it is an option applicable to most Nordic SoCs.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Adds snippets-text-sections.ld to ACE linker scripts.
For now, this is for the memory mapping test.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There were some corner cases and stress test could fail. Reworking
tail bits handling to make the stress test pass.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Fix an incorrect interpretation of the chip select signal
for the SPIM instances. If cs-gpios is used then the chip
select pin is used as a GPIO, and should have CTRLSEL=0.
Only when NRF_FUN_SPIM_CSN is used should CTRLSEL
be configured to enable hardware control of the pin.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Provide PM support, specifically suspend-to-ram, for STM32WB0x.
Enable STM32_RADIO_TIMER Kconfig parameter when PM is set.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Use radio timer as the system timer when Bluetooth is used.
Modify CMakeLists.txt to compile radio timer driver when
STM32WB0_RADIO_TIMER is enabled.
Remove the common parts from hci_stm32wb0.c that are present
in the radio timer driver.
Set and retrieve the appropriate value for SYS_CLOCK_TICKS_PER_SEC and
SYS_CLOCK_HW_CYCLES_PER_SEC respectively.
Define radio_timer node and its properties.
Enable radio_timer node in nucleo_wb0x boards.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
