STM32L4 devices, except STM32L412 STM32L422 STM32L4P5 STM32L4Q5, have
32 4-byte battery-backed RTC backup registers. Other STM32L4 devices
have backup registers in tamper module, not used in Zephyr.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All STM32L1 devices have 4-byte battery-backed RTC registers, but
they have different number of registers:
STM32L151Xb-a has 5 registers.
STM32L151Xb has 20 registers.
STM32L151Xc, STM32L152Xc, STM32L152Xe have 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add BBRAM entry for all STM32H7 microcontrollers except STM32H7A3 and
STM32H7B3 which have backup registers in tamper module.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All supported STM32F3 devices have 4-byte battery-backed RTC registers,
but they have different number of registers:
STM32F303x8 and STM32F334 have 5 registers.
STM32F303xc and STM32F303xe have 16 registers.
STM32F302x8 has 20 registers.
STM32F373 has 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Among supported devices only STM32F031, STM32F051, STM32F072 and
STM32f09x have 5 4-byte battery-backed RTC registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add the HSI48 clock to the stm32 devices that have this
clock signal.
Within a stm32 family, only few might have the
RCC_HSI48_SUPPORT.
STM32WB has a CLK48 mux.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1170 and RT1160 CM7 and CM4 cores have the same set of differences.
Merge the DTS files for both CM4 and CM7 cores, to create generic
rt11xx_cm4 and rt11xx_cm7 files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add system reset control device (sysrst), so that the drivers can
assert/deassert its reset line through the public reset controller
driver API.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Re-enable the CAAM for entropy
now that the HAL driver has been fixed
Job descriptors must be accessed coherently
between CAAM DMA and core.
The M4 Cores still do not work
because of mpu/cache/kconfig arch complications,
disable caam for M4 cores in DTS
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable RTU System Timer Module (STM) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to
133.333333 MHz.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Define the octospi node for the stm32l4plus MCUs from
STMicroelectronics.
It is controlled by a OSPIMgr in front of each peripheral.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
FlexSPI memory map indicates that the FlexSPI register space is 128MB, not
64MB. Update this value to be correct.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds an ieee802154 node to the list of nRF5340 application
core's peripherals. While it does not translate directly into a physical
RADIO peripheral, it represents the capability to use the ieee802154
radio (indirectly, through the network core).
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Ensure that PECI block is enabled in the EC Subsystem by clearing
the PECI_DIS (peci disable) register
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
For all STM32 featuring octospi, clock-names are added to use them
instead of indexing for configuring the clock.
For U5 series, a third clock is added for the OSPI manager.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Set the status of the DMA controller, xdmac, to disabled. In effect
changing the default status from okay to disabled for all sam e70
based board.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add support input interrupts for GPIO pins on NXP S32Z27
SoC. The driver will convert GPIO pin to respective
interrupt line that will be processed by External
Interrupt Controller.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add initial support for the NXP S32Z27 SIUL2 External
Interrupt Controller. Each SIUL2 node has a child node
will act as an interrupt-controller that processes external
interrupt signals.
This driver is required to manage GPIO interrupts.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
New ADC driver for the TI CC13xx/CC26xx family.
ADC channel configurations are translated from Zephyr constants to
simplelink driverlib ones (e.g., sample times use a lookup table).
Async mode was also implemented & tested.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Define the DMA and DMAMUX peripheral for the stm32MP1
DMA1 and 2 are of type V1 of 8 streams (channels) each
with a DMAMUX peripheral. See the RefManual for details.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Set default interrupt priority to 3 for all Microchip MEC172x eSPI
host child devices except the UART's which are set to 1.
The espi peripherals don't require the maximum priority hence they
are being made uniform and a lower priority 3.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
USB interface that may be used to send messages from a USB host to
the M4 processor in the S3B, and vice-versa.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
Add MEC172x full duplex qmspi driver version to support full
duplex transfers as expected by the Zephyr spi driver model.
On every spi clock we transmit one bit and receive one bit.
This driver will work with Zephyr SPI NOR driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
updated dts variables naming (hyphen instead of underscore).
moved all properties in microchip ldma yaml to a separate include file,
these properties will be common with the (to be added)
full duplex spi driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Enable GPIO driver on s32z270dc2_r52 boards. S32Z27 pads are grouped
into GPIO ports A to N.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 LINFlexD peripheral operating
in UART mode. Polling and interrupt-based serial API's are supported.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce support for Pinctrl driver on NXP S32Z/E SoC's.
The NXP S32 pin controller is a singleton node responsible for
controlling the pin function selection and pin properties, based on the
pin node group approach. The pinmux configuration is encoded in a
32-bit value.
Each S32 SoC implementing Pinctrl must create a `pinctrl_soc.h` header
which define SoC-specific macros to initialize the pinctrl structure.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 devices, specifically for
S32Z27 from S32Z/E family.
NXP S32Z27 processors are composed of two Real-Time Units (RTU)
containing each four ARM Cortex-R52 cores with flexible split/lock
configuration, and dedicated internal SRAM.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Ethernet MAC dts definition for STM32F107, similar to STM32F207 but with
different clocks, especially no PTP clock.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
Adding ethernet in the DTS file and corresponding binding
for Cyclone V SoC FPGA board..
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
rt1170 has two group fast gpio and shared the same
interrupt source. Now add the dts definition for the
fast gpio
Signed-off-by: Crist Xu <crist.xu@nxp.com>
Add successive inclusion for STM32F072 dts by including
STM32F070 dts instead of STM32F0 dts.
This allows to reuse the definition of
- Flash
- SPI
- USB
from the new parent.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Replace the hardcoded kPWM_Prescale_Divide_128
driver prescaler with the ones defined in the dtsi file
that allow overriding them by the user.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Update RT11xx SOC DTSI files to use DT nodelabels on RT11xx SOCs,
instead of reencoding the base address of each peripheral in the M7
and M4 DTSI files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix ordering of IOMUXC pinctrl selections for gpio pinmux setting.
This will allow the gpio_configure call to correctly set
mux settings for this SOC.
Fixes#50502
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The vref has to be set to 3000mV.
It is the voltage to find on the stm32F3.
is fixed by the platform to be lower or equal to VDDA.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add gpio-reserved-ranges property to gpio controllers on RT10xx devices
that have gaps in their GPIO numbering.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Two issues:
- The nsmi_gpio107 node is being defined twice with the same pinmux
property value. This is an error when compiling the file with dtc.
Zephyr's dtlib doesn't currently error out on this, but it will soon.
Fix this by removing one of the redundant definitions.
- The eeprom_clk_gpio117 node label is referring to a node named
gpspi_clk_gpio117, which is already defined in the same file, but
with a different pinmux property value. This looks like a clear
copy/paste error causing invalid pinmux settings for the
gpspi_clk_gpio117 node.
Fix it by aligning the node name with the node label to create
a separate node with its own pinmux value.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Fix the incorrect temperature sensor (Die temp), the default value of
the vref-mv is 3.3V.
Actually, the vref is a board value rather than a soc one
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The LPC55s3x SOC comes with 2 FlexPWM peripherals each with 4 Sub-Modules.
Each Sub-Modules has 2 channels A && B.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
The property is similar to the usb_controller_index_t
enum that is available in the NXP SDK.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
According to errata sheet, LSE driving-capability should not be set
to 0 or 1.
Set it to 2 as default value.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Reduce the default RAM usage for the NXP LPC MCAN CAN controller driver by
reducing the number of RX buffers, TX buffers, and filter elements.
The LPC MCAN uses regular SRAM as backend and the default configuration
causes SRAM overflows for many CAN tests.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
There are three types GD32 FMC.
GD32 FMC v1: its flash memory has 1 bank, page size is equal in the
bank, flash size is smaller than 512KB.
GD32 FMC v2: its flash memory has 2 banks. Page size equal within the
same bank but different between banks. Flash size can be up to 3072KB.
FMC v2 has two registers to control bank0 and bank1 separately.
GD32 FMC v3: its flash memory has 2 banks, use sector size as the
minimum operating unit, the sector size is not equal.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
The enet1g peripheral was missing in device tree for nxp rt11xx.
With this commit, the peripheral can be operated like the enet peripheral
with the eth_mcux (kinetis-ethernet) driver at 10/100 Mbit (no gigabit).
Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
R-Car Gen3 platforms have up to 7 channels. Add the node to
the rcar_gen3_cr7 SoC series. In contrary to Linux, declare
only one PWM controller with 7 channels. So only one node is
written into dtsi file.
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Define RaspberryPi Pico ADC.
The ADC has internally connected temperature sensor,
Add property to enable this.
The ADC has a single VREF. VCC usually connects to it,
but it may not be in a case.
Add property to make configurable it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Use the clock control API to enable peripheral clocks. Note that both
GPIO and pinctrl drivers are updated at once since they share some IP
blocks.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use the clock control API to turn on ADC clocks. Note that clock
selection is not yet implemented, so we still rely on custom rcu
properties for that.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There is only a single DMA in GD32F3X0. It is referenced as DMA in
datasheet, not DMA0 as in series that have > 1.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use node label to overwrite the flash and ram properties.
This removes some boilerplate as it is less verbose.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Added code to enable platform specific Virtual Wire GPIOs. With this
change, able to send the USB-C overcurrent Virtual Wire event to
Meterolake SOC.
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
The clock bus of the specific SPI module (FIU) is under FIUCLK. The
previous commit misconfigured it to APB3_CLK. Although it won't
cause any issue as the driver doesn't use it. It should be fixed to
prevent confusion when reading the datasheet.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
zephyr.dts:482.21-491.5: Warning (simple_bus_reg): /soc/dietemp: missing
or empty reg/ranges property.
To fix this bug, just move dietemp node outside of soc{}.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
This adds flash driver for Renesas SmartBond(tm) family.
This technically uses QSPI controller but since default and most
commonly used configuration is to boot from external QSPI flash (DA1469x
do not have built-in flash) and that flash is mapped into memory space,
it can be represented as internal flash.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds serial driver for Renesas SmartBond(tm) family. Both polling
and interrupt APIs are supported.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds GPIO driver for Renesas SmartBond(tm) family.
Driver supports pin configuration (input/output) and interrupts on edge.
Interrupts on level are not supported by hardware.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds initial support for Renesas SmartBond(tm) DA1469x series SoC.
Initailly only DA14699 is explicitly supported, however this code should
also run on other SoCs in this series since all of them support the same
core features available initially.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This device-tree file is only used by rt10xx dtsi files, as rt11xx (and
other families as well) have their own root SoC specific dtsi file.
Rename nxp_rt.dtsi to nxp_rt10xx.dtsi for consistency across families.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
All 'k' parts share the same amount of RAM/FLASH, so rename file to
include 'x' instead of 'i'.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new reset driver for GD32 platforms. This driver controls the
reset registers from the RCU peripheral. It can be used to restore
peripherals to their initial state when initializing a device.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit enables the SoC's flash memory controller.
- added lpc55s36 specific code in the NXP MCUX driver
to take advantage of the SoC's check-before-read
capability
- enabled the FMC node in the SoC's dtsi (iap)
- added the flash controller chosen node to the board's dts
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Disable flexspi flash controller by default, allow boards to enable it.
This SOC uses external flash, so boards should only enable the flash
controller when their specific flash module has been verified to work
with the flash driver API in Zephyr.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
enable IAP flash controller for secure core, as this is the core where
flash support has been verified.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Disable IAP by default for lpc55s06, enable it for the non secure core
as this is the mode that the flash controller has been tested in.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for LPC54xxx IAP flash driver to soc_flash_lpc.c
Driver is tested on M4 core only, and is therefore disabled on the M0 core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update flexspi partition layout to add a 128KB storage partition. Also,
fix flash device name and size to match the SIP flash present on
the RT1024 SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Document support for flexspi as flash controller on mimxrt1064_evk, and
move status=okay for internal flash to soc level dtsi
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
disable flash controller for nonsecure core, as only the secure core is
tested with flash support.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
set nxp,imx-flexspi to disabled by default to disable flash driver for
this SOC unless enabled by the target board. This SOC uses external flash,
so boards should enable the flash controller only when flash support
has been verified with their specific external flash module
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
According to DT spec, device_type property is deprecated (ref. 0.3 spec,
2.3.11):
> The device_type property was used in IEEE 1275 to describe the device’s
FCode programming model. Because DTSpec does not have FCode, new use
of the property is deprecated, and it should be included only on cpu and
memory nodes for compatibility with IEEE 1275–derived devicetrees.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Make use of nodelabels to extend flash/sram nodes instead of re-defining
the whole tree. This pattern is already used in some other files.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The can2 only works if gating clock of the master can (can1)
is enabled, therefore also set that bit for can2.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add the support of the temperature sensor in the ADC device-tree node of
each stm32 where it is available.
- Check all the ADC of the stm32 mcus where the temp and VrefInt monitoring
is available (based on the Ref Man).
- Check that has-temp-channel; and has-vref-channel; in the corresponding
ADC node of the DTS of each stm32 mcu is correctly set.
- Verify the VTEMP/ VREFINT activation in the in adc_stm32.c for example).
-Add the die-temp node (based on the ref man/ datasheet).
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
USB SRAM region was accidentally deleted by an earlier
commit. Rename the memory region used by USB to USB_SRAM instead
of SRAM4. SRAM4 was the wrong name for this region.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit defines the GPDMA peripheral for the stm32U5.
This dma is of a new type with 16 channels and 114 requests.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove 'ranges' property from gpio node as it shouldn't be there
since we aren't converting 1:1 between address spaces. This fixes
the following DTC warning:
Warning (ranges_format): /soc/gpio@e000a000:ranges: empty "ranges"
property but its #size-cells (0) differs from /soc (1)
Signed-off-by: Kumar Gala <galak@kernel.org>
We currently get a number of warnings like:
Warning (simple_bus_reg): /soc/otgfs_phy: missing or empty
reg/ranges property
This is due to the usb phy nodes not have a reg property since they
don't have an mmio address associated with them.
Move the phy nodes out of the SoC node so their lack of a reg property
will not cause a warning. This is similar to how Linux dts files
handle the phy nodes.
Signed-off-by: Kumar Gala <galak@kernel.org>
The nist-config and health-test-magic properties are added
to the dtsi file, in the RNG node for the stm32 devices
that supports the RNG entropy source validation.
The health-test-magic nb exists on stm32l552 stm32h723/7a3.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add spi0 and spi1 configuration to rp2040.
spi0 and spi1 are declared as compatible with
"raspberrypi,pico-spi" and "arm,pl022".
"raspberrypi,pico-spi" is just inherited from
"arm,pl022" and "reset-device"
spi0 and spi1 declare as compatible with "raspberrypi,pico-spi"
and "arm,pl022".
"raspberrypi,pico-spi" is just inheriting "arm,pl022" and
"reset-device" for declaring the 'reset' property,
with no additional property and implementation.
Add also pinctrl macros to dt-bindings header.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
The fast-gpio has a dedicated interrupt idx 99, not
the same with the normal gpio. So if we want to use
the fast-gpio, need use the interrupt idx 99.
Signed-off-by: Crist Xu <crist.xu@nxp.com>
The lpc and mcux drivers' DRV_COMPAT is updated for the new bindings
introduced in the previous commit. The drivers' Kconfig files also
reflect this change (DT_HAS_ENABLED_NXP_...).
The SoC device trees are updated with the new bindings
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT600.
Added alias for usdhc0 to be able to use SDHC test.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add pinctrl definitions for the SMC peripheral (8) and add the
module to the sam4e soc.
IDs and addresses are taken from the datasheet.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The current atmel sam flash driver was develop based on the cortex-m7
version of smart arm microcontroller. The driver support write
protection and cache functions which is not supported by other cortex-m
variants. This fixes current driver implementation and devicetree
entries for all sam variants.
Notes:
* The cortex-m3 doesn't have support erase pages flash command and
because of that the driver still not not compatible. Keep it disabled
until a patch be send. The hwinfo driver is not affected by this
restriction.
* The sam4l variation requires a specific driver because uses another
flash controller (flashcalw). Added another compatible to
differentiate and keeped node disabled until a driver be available.
Fixes#48516
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Labels are no longer needed because devices are obtaines using
zephyr,ieee802154 DT choice.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable the IEEE 802.15.4 radio node on all boards that listed
'ieee802154' in the supported field.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This is temporary until support has been enabled. lpc55s36's IAP controller
is different and does not match previous implementations.
The Zephyr driver uses a data structure matching the IAP controller to
implement a feature that should normally come out of the ROM.
Since IAP support is not in yet, disabling the option in the SoC's Kconfig
and disabling the node in the device tree is the proper way to go forward.
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_NRF5_DRV_NAME in preparation for the
removal of NET_CONFIG_IEEE802154_DEV_NAME.
All SoC files have been updated with the addition of an ieee802154 node
(disabled and only on those SoCs that define ieee802154-supported. The
peripheral has been enabled in the nRF52840DK board (used for testing
ieee802154).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_KW41Z_DRV_NAME in preparation for the removal
of NET_CONFIG_IEEE802154_DEV_NAME.
KW41Z files have been updated with the addition of radio and an
ieee802154 nodes The peripheral has been enabled in the frdm_k41z board
(used for testing ieee802154).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_CC13XX_CC26XX_SUBG_DRV_NAME in preparation
for the removal of NET_CONFIG_IEEE802154_DEV_NAME.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_CC13XX_CC26XX_DRV_NAME in preparation for the
removal of NET_CONFIG_IEEE802154_DEV_NAME. All boards used in testing
have been updated to enable the peripheral in DT as well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files were missed during the migration. This patch adds the prefix
where missing.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add system clock control device (sysclk), so that the drivers can turn
on/off its clock through the clock control API.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
The stm32f303x8 SoC is not equipped with spi2 and spi3 peripherals.
Exclude them from the SoC-level devicetree.
Signed-off-by: Jan Kuliga <jtkuliga@gmail.com>
Add the octospi nodes to the stm32h7A3 and
and h7B0/h7B3 devices.
Note that RM0455 gives a size of 1kB.
The definition of the octospi clock source for both intances
is given by the DTS node. The selected value for
the alternate clock control is the PLL1_Q.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the octospi nodes to the stm32h723/h725
and h730/h733/h735 devices.
Note that RM0468 gives a size of 1kB.
The definition of the octospi clock source for both intances
is given by the DTS node. The selected value for
the alternate clock control is the PLL1_Q.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds the pll2 and pll3 clock control nodes
with st,stm32u5-pll-clock compatible.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This CL adds a DT node, 'power_leakage_io', which property,
'leak-gpios', contains GPIOs that have leakage current. In oerder to get
better power consumption, npcx power driver will disable the connections
between these io pads and input buffers before entering deep sleep.
Then, restore the connections after ec wakes up.
The users can overwrite this property at board DT file. Here is an
example:
&power_leakage_io {
leak-gpios = <&gpio0 0 0
&gpiob 1 0>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL configures low-voltage (1.8V) detection via GPIO driver with
GPIO_VOLTAGE_1P8 flag. It also adds support for this flag in
pin_get_config() function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Cleanup npcx low-voltage (1.8V) detection configuration. It removes
unused soc utilities, macros, and DT node. We will configure this
feature by GPIO driver with GPIO_VOLTAGE_1P8 flag later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Move the RX (MISO) delaying capability information to Devicetree. It is
done using 2 properties:
- rx-delay-supported: enabled on SPI nodes that support delaying RX.
This property can be used by the driver to determine if this
capability is supported or not on a given instance.
- rx-delay: the actual RX delay value
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Devicetree is the natural place to describe hardware, so move the
maximum frequency the SPI can work with to Devicetree instead of relying
on values from HAL.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
Implement support for SAMR34 and SAMR35 parts, tested on a SAMR34
Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO,
PWM, ADC.
NOTE: The SAMR34 datasheet lists NVIC line 20 for the ADC's interrupt,
but the SAML21 datasheet gives line 22. It appears that the SAMR34 sheet
is incorrect (the ADC doesn't function with line 20), and as such, I have
also omitted the adjustments for TC4 and AC...
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Implement support for SAML21 parts, tested on a SAML21 Xplained Pro dev
board. Confirmed operational peripherals: UART, GPIO, PWM, ADC.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Remove 'label' property from SDHC nodes. We can use variants of
DEVICE_DT_GET to get access to a device pointer for use in an
application.
Signed-off-by: Kumar Gala <galak@kernel.org>
Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT
nodes and related yaml files. Currently, PSL pad configurations are made
by pinctrl mechanism. Please refer
https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add counter nodes to timer nodes in dts of stm32l4 series.
This should enable the support of the basic counter API
on all stm32l4 mcus for general-purpose and basic TIMx timers.
Signed-off-by: Jan Kablitz <kabeljant@gmail.com>
Clean up unused pinmux function 'npcx_pinctrl_mux_configure()' and
related 'NPCX_DT_IO_ALT*' macro functions.
Please refer https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add NPCX Power Switch Logic (PSL) DT node which controls the power rails
of SoC to get better power consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:
1. Add two pinctrl properties and their enums for PSL input
detection configuration.
psl-in-mode:
- "level"
- "mode"
psl-in-pole:
- "low-falling"
- "high-rising"
2. Add macro functions to get PSL input detection and pin-muxing
configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
properties.
Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.
/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
psl-in-mode = "edge";
psl-in-pol = "low-falling";
};
A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This adds basic support for the watchdog timer on the RP2040 MCU and
Raspberry Pi Pico development board
Signed-off-by: Jamie McCrae <spam@helper3000.net>
When required, add "st,stm32h7-spi" compatible on stm32 compatible
series (today: stm32h7, stm32mp1 and stm32mp1).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use consistent name for SPI HW block properties across Microchip
HW, so applications using a device tree overlay work
transparently.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Some EFR32 SoCs use a secure element subsystem to manage
security features (i.e., TRNG, secure bootloader or cryptographic
functions).
This driver relies on the SE Manager high-level API provided by Silicon
Labs. The API interacts with the SE subsystem, provides helper functions
to achieve cryptographic operations and ensures that only one operation
is running at a time by using mutexes and semaphores.
Instead of relying on the SE Manager from Silicon Labs, one could
recreate the behaviour of the Manager and put the code in the crypto
driver folder and create a dependency for other drivers using the crypto
manager (e.g., keys, entropy).
I went for the SE Manager API as it is already there and supported by
Silicon Labs.
Tested using the random subsystem.
Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
The definition of the octospi clock source is given
by the DTS node. The default value selects the sysclk
(not pclk) for the alternate clock control.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The definition of the clock source for the 2 octospi
instances is given by the DTS node.
The default value selects the sysclk (not pclk)
for the alternate clock control.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
According to the formulas found in the reference manuals of the SoC
families using the "st,stm32-temp-cal" version of the temperature sensor
(i.e. G0, G4, H7, L0, L1, L4, L5, U5, WB, WL), the temperature is
computed with the following formula:
T = ((TS_CAL2_TEMP - TS_CAL1_TEMP) / (TS_CAL2 - TS_CAL1))
* (TS_DATA - TS_CAL1) + TS_CAL1_TEMP
What is called ts-cal-offset in the stm32_temp driver is therefore the
same value as TS_CAL1_TEMP1. Use it directly instead of defining another
property.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pin control support for SWO log backend, by creating a new
ITM node for the ARM instrumentation trace macrocell. Add pin control
properties under this node, and refactor the swo-req-freq property to be
defined within this node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add devicetree node for the pinctrl of the Xilinx Zynq-7000 series. Pinctrl
is set through a subset of the System Level Control Registers (SLCR), which
is accessed through the syscon driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit rewrite renesas R-Car clock driver in order
to be able to support any new SoC easier.
This work is so creating a clock driver per soc alongside a
common driver for all reneasas r-car boars.
- drivers: create a driver per soc
- create a common driver
- create a common header used by soc & common driver
- create a soc specific driver calling for common driver
- dts: use new compatible
- use old yaml as common yaml
- create a new "child" yaml to define the new compatible field
- change compatible in device tree
As in Linux, the driver can support both r8a77951 and r8a77950
SoC's so we decided to name the new driver as in Linux with Zephyr
prefix : "clock_control_r8a7795_cpg_mssr.c".
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit is reworking clock definition in
order to match linux filetree and definition
as much as possible.
- dt-bindings: rework renesas clocks dt-bindings
- regroup renesas related dt-bindings in a folder
- rename renesas rcar common dt-binding to match linux name
- add soc specific dt-binding matching linux name
- soc dt-bindings are defining clocks matching linux names
- dts: use new clocks names
- move clocks definitions in SoC layer for each core clock entry
- driver: use new clocks names
As seen in this commit, we are declaring clocks for "R8A7795" SoC
to match linux names.
Linux is not declaring "R8A77951" SoC specific files because
its also supporting the first H3 SoC version numbered "R8A77950".
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
The STM32H7A3 SoC has 64 kB of ITCM RAM mapped at address 0x00000000.
Tested using zephyr_code_relocate().
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In #46480 the st,stm32-fdcan driver was updated to use clock_control to
configure peripheral bus clocks. However, the default clocks property
added to the can1 node of stm32u5.dtsi was not correct.
This correction has been tested on known good hardware which uses the
STM32U5 and FDCAN peripheral.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
This commit unifies the driver initialization for can1 and can2
instances so that a single macro can be used.
Enabling the master clock for can2 as introduced in 8ab81b02 had to
be moved to devicetree in order to have the same CAN_STM32_CONFIG_INST
macro for all instances.
Signed-off-by: Martin Jäger <martin@libre.solar>
The erase time for a sector differs by a few order of magnitude for the
various SoCs of the STM32H7 family. Declare it in the device tree using
the existing max-erase-time property. For that it is necessary to add
"st,stm32-nv-flash" to the compatible node.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Some flash properties are currently in the individual SoC definitions,
while they are common to the whole STM32H743/753 SoC line. Move them one
level higher.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
h753
Some flash properties are currently in the individual SoC definitions,
while they are common to the whole STM32H7A3/STM32H7B3 line. Move them
one level higher.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property. Update the dts bindings to not require it and
remove setting of the label property in dts files.
Signed-off-by: Kumar Gala <galak@kernel.org>
G4 and U5 series missed clock information in DT. Driver likely worked
because it was using HAL helpers, bypassing the purpose of DT and clock
control drivers. The clocks property is now required in the binding
file.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The ns16550 flags reg-shift property as optional. In case it is not
supplied, the ns16550 driver relies on a value defined in <soc.h>, or,
by default it takes 4 (shift by 2).
This patch adds the property to all ns16550 nodes, with the following
values:
- 2 if SoC did not have any custom value defined by
UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4)
- If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such
value (4=2, 2=1, 1=0).
These changes will allow simplifying the ns16550 driver.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- The MX25UM51345G flash is connected to FLEXSPI PortA for
mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Enable access to the HS_SPI pins(JP26) on the mimxrt595_evk board.
Using DMA mode, tested with spi_loopback testcase.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
WWDG1 doesn't work on STM32H7 because its peripheral clock
is never enabled due to wrong enable bit in RCC_APB3ENR
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
The STM32F723 SoC has 16 kB of ITCM RAM mapped at address 0x00000000.
Tested using zephyr_code_relocate().
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This includes DTS bindings for the Texas Instruments CC13xx/CC26xx flash
controller driver and adds support for it in CC1352R and CC2652R SoCs
DTS files.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix various board fixed-partition definitions where the devicetree cell
has been defined oddly, such as 9 nibbles (which makes no sense since
the cells are 32 bit) or 7 nibbles where all the others are 8.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix PM minimum residency time and exit latency for rt11xx to reflect
actual delays when entering and exiting low power modes.
Fixes#45750
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Set the priority of the wwdg instance to 6
else a build error happens :
static assertion failed: "Invalid interrupt priority.
Values must not exceed IRQ_PRIO_LOWEST"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
LPC55sx6 SOC has NXP Manufacturing Programmed Area(NMPA) stored at
offsets 0x3EC00-0x3FDFF. Correct uuid offset to be within this region.
Fixes#43870
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
All the SPI1,2,3 clock of the stm32h7x mcus
are sourced by the PLL1_Q by default. This must be set
in the DTS to have a valid clock rate calculation.
The pll1_q is divided by the <div-q> property of the pll node.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This PR Fixes the Audio PLL Rate Calculation (there was an additional
divide / 8 which is not necessary and does not appear in similar
calculations in example code from the SDK).
Additionally, it adjusts the SAI .dtsi to more correctly configure the
mclk rate, and adds comments specifying what the regististers mean.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
The binding was erroneously changed in commit 988fe8d, which led to
build failures. This commit reverts the change.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add inclusions of header files with devicetree related ADC definitions
to the nRF SoC dtsi files so that those definitions can be used also
for nRF SoC based boards.
Provide definitions of nRF ADC and SAADC analog inputs suitable
for use in devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx eSPI and host_subs driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx adc driver. Please notice users need to
configure the corresponding pinctrl nodes in 'pinctrl-0' property in the
adc0 DT node. For example, if ADC0 and ADC2 channels are selected for
the application, please add the follwoings in your board DT layout file.
&adc0 {
status = "okay";
/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
pinctrl-0 = <&adc0_chan0_gp45
&adc0_chan2_gp43>;
pinctrl-names = "default";
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in ps2 driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in pwm driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in i2c driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in uart driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Removes label and compatible properties
from the flash section. The properties are
provided by included stm32h723.dtsi.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Removes label and compatible properties
from the flash section. The properties are
provided by included stm32h723.dtsi.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
* Corrects SRAM0 size. The `TCM_AXI_SHARED`
is `000` after reset. That means ITCM
is shared with SRAM0.
* Adds missing SRAM1,2,4, and ITCM
regions.
* Adds label and compatible properties
to the flash section.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
convert lpc11u6x syscon clock driver to pin control, and remove all
pinmux usage from driver and syscon dts node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
switch gpio driver to use pio nodes to configure pin control settings,
and stop using pinmux driver within gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
Add clock sources bindings on F0/F3/G0/G4/L0/L1/L4/WB/WL series.
Due to inconsistencies, some common bindings are now split:
F1 -> F0/F1/F3
L4 -> L4/G4/WB
Update .dtsi files when required
In a first step, allowed sources are limited to already supported
clocks: LSI/LSE/HSI/HSE/MSI/PCLK/PLLCLK/SYSCLK
Support for other clocks such as HSI48, SAIXCLK, ... is left for a
next step.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This is a follow-up to commit 586e26e8fc.
Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the UPLLCK clock for the CAN controller as recommended by the Atmel SAM
E70 data sheet.
Move the configuration of the clock prescaler from Kconfig to devicetree
and limit it to the values recommended by the SAM E70 datasheet.
Fixes: #45012
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
In #45014 the m_can compatible identifier was changed from "m-can-base"
to "m_can-base" while #45216 was being developed. This commit updates
the dts for u5 to the latest format.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Cleaned up the IPC configuration for nRF5340 SoC in Device Tree. This
change fixes the (simple_bus_reg) warning about the missing or empty
reg/ranges property.
This is a follow-up to commit cf6a58d.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Add support for the fdcan peripheral to the stm32u5 series device tree
include. This can be applied here since (at present) all of the stm32u5
series MCUs have an FDCAN peripheral.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
All DT nodes end up being part of the generated 'devicetree_unfixed.h'
header, wether they are referenced or not. The number of entries in that
file can grow quickly when using pre-generated pinctrl nodes.
Considering <devicetree.h> (file uncluding devicetree_unfixed.h) is used
in lots of places nowaday, not using /omit-if-no-ref/ can lead to
increased build times.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Comparator will monitor signal though ADC channel, based on
user configuration, callback will be triggered.
This will enable comparator functionality for nuvoton MCU utilizing its
ADC threshold detection feature. Implementation is exported through
sensor trigger API. Use of CONFIG_ADC_CMP_NPCX is required.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
add pin control nodes for LPC SOCs, to be filled with pin control
settings at the board level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. When jumping from the current image to the other,
the firmware switches the eSPI-related pins to GPIO function at
initialization if define alt1_no_lpc_espi in def-io-conf-list.
It causes the eSPI to reset and breaks the eSPI communication after the
image jump. This patch prevents it by removing alt1_no_lpc_espi from
def-io-conf-list.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the cpu0 allocation to use SRAM0-SRAM2 for 192K and change
cpu1 to use SRAM3-SRAM4 for 80K.
Signed-off-by: David Leach <david.leach@nxp.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the M4 allocation to use SRAM0+SRAM1 for 128K.
Signed-off-by: David Leach <david.leach@nxp.com>
LPC platforms define multiple SRAM memory blocks that are contiguous
in memory but the zephyr build system doesn't have a method to
specify all the nodes to be used for a CPU's chosen "zephyr,sram"
node. To be able to get full use of memory, sram0 is redefined to
80KB in size.
Fixes#43872
Signed-off-by: David Leach <david.leach@nxp.com>
with the legacy USDHC driver fully removed from the tree, the
nxp,imx-usdhc binding can now be used for the new SD host controller
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add generic SDHC dts binding, as well as DTS binding for NXP USDHC.
Update iMX.RT DTS binding to use USDHC compatible
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Rename the base Bosch M_CAN CAN-FD controller devicetree binding to
match the product name and the upstream Linux devicetree binding.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
STM32WB55xG MCUs include 256 KiB of SRAM split into three banks.
The size of the main bank is 192 KiB, and not 96 KiB as it was
specified in the device tree. This commit fixes the issue and
also updates the definition of the NUCLEO-WB55 board, based on
a STM32WB55RG MCU.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
The PWM period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The binding did not define the PWM cells. Only channel and period have
been added as they are the minimum required ones (flags are not supported).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to be consistent with other platforms, include the PWM
dt-bindings by default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period cell will soon be required by the pwm_dt_spec facilities,
this patch adds it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Include the PWM dt-bindings by default, so that boards can use utilities
like PWM_MSEC() without extra includes. This is a common pattern done
for e.g. i2c or gpio.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
... and "nordic,nrf-pwm" binding:
- use channel indexes instead of pin numbers in `pwms` properties that
define PWM LEDs
- add the period and flags cells to `pwms` properties in all PWM LED
definitions; use the commonly used period of 20 ms (giving 50 Hz)
as a default setting
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... to align with what is used in most other PWM bindings.
Update PWM nodes in SoC .dtsi files accordingly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align with other PWM drivers and treat the `pwm` parameter (described
ambiguously as "PWM pin") of the `pwm_pin_set_cycles` function as a PWM
channel, not an SoC pin. This will also make the driver consistent with
the `pwm-cells` property definition in the "nordic,nrf-sw-pwm" binding
and with related `DT_PWMS_*` macros.
The change described above requires also providing a way to specify
SoC pins that are to be assigned to the PWM channels. Hence, the commit
introduces in the "nordic,nrf-sw-pwm" binding the `channel-gpios`
property that replaces the `channel-count` one.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On some parts, it could be required to use steps before applying
highest frequencies.
This was previously done as part of LL_PLL_ConfigSystemClock_FOO
utility functions which are no more used.
Use device tree to mention when this is required and implement it
in stm32_clock_control_init().
Additionally, fix the calls tp LL_RCC_SetAHBPrescaler, which require
use of ahb_prescaler helper.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a new scheme to define clock bingings on u5.
In a next steps, this new scheme will allow to provide u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32h7 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit has the necessary changes to update the consumers
of pinmux driver(SPI, I2C, UART) and update the board specific
files to use the pinctrl interface.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
This PR fixes up the Scatter-Gather EDMA mode for the MCUX EDMA Driver,
as well as enabling the dma reload feature for the same EDMA Driver.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
This commit adds a flash_controller node for the stm32u5 soc family
blocks of 8K and erase time given by the Datasheet (with margin).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the period cell to GD32 PWM compatible and update all boards
accordingly. A period of 20 ms (50 Hz) has been set for all PWM LEDs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
STM32 supports now custom PWM flags, include them by default as done for
the standard flags.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
add soc level pinctrl node to LPC55s6x DTSI file, to be populated with
pin groups at the board level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add boolean properties to the binding for the nRF RADIO peripheral
to indicate whether the following features are supported:
- IEEE 802.15.4 mode
- 2 Mbps BLE mode
- coded BLE PHY
- high TX power settings
Set these properties appropriately in devicetree radio nodes for all
nRF SoCs.
Add also such properties and set them in appropriate nodes for nRF
flash controllers to indicate whether they support partial erase.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
For consistency with the scheme used for other nRF peripherals,
use the peripheral name that nRF Product Specifications use.
In this case, it is WDT, not WATCHDOG.
Also remove the requirement for the label property in the binding.
It is no longer needed.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing devicetree nodes representing the following peripherals
in nRF SoCs:
- ACL
- BPROT
- CCM
- COMP/LPCOMP
- CTRLAP
- DCNF
- MPU (nRF MPU peripheral in nRF51 Series, not ARM MPU)
- MUTEX
- MWU
- NFCT
- OSCILLATORS
- POWER (in nRF51 and nRF52 Series)
- PPI
- RESET
- SWI
- USBREG
Add also corresponding bindings and validation of base addresses of
these nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit cf6a58d3f6.
Restore the "nordic,nrf-ipc" compatible property in mbox nodes for both
nRF5340 cores and use it together with the new "nordic,mbox-nrf-ipc"
one. This way either the MBOX or the IPM driver can be used for these
nodes without further modifications. This eliminates the need to use
overlays in quite a few cases, so remove all those no longer needed
ones (which are also a bit confusing now as they refer to no longer
existing ipc@2a000 and ipc@41012000 nodes).
Restore also the ipc node label removed in the commit mentioned above,
as the label is used in validation of base addresses of nRF DT nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Since the HCI entropy device is a software construct that is able to
provide entropy bytes by retrieving them from a Bluetooth Controller,
generalize it by moving it to the Nordic common DTS code. Additionally
move the chosen nodes from the nRF5340 DK board files to the SoC ones.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Update Microchip XEC TACH driver to support MEC172x.
Standardize device tree properties between chips.
Standardize device structure usage.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add devicetree node for IPC driver so that the IPC interrupt properties
can be accessed with device tree interrupt property macros and
configured using devicetree overlays.
Signed-off-by: Eivind Jølsgard <eivind.jolsgard@nordicsemi.no>
Co-authored-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In order for pinctrl support to be complete, RT series GPIO driver must
support pinmuxing within the driver level. RT series pinmux settings do
not correspond directly to gpio port/pin numbers, so use DTS mappings to
pinctrl nodes to select and apply pinmux settings in the gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx series has similar pin configuration peripheral to RT10xx, with
some differences in register layout. Create new pinctrl definition
header file, and reuse existing driver code for RT10xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
OCRAM can be used for DMA, and in this case it should be marked as
noncacheable. Add KConfig symbol and appropriate linker scripts to
enable OCRAM region to be defined as noncacheable, and initialized with
data from flash at boot.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This update Atmel sam and sam0 ethernet gmac and mdio drivers to use
pinctrl driver and API. It updates all boards with new pinctrl groups
format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam0 serial drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam afec driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format. In addition, it
add overlay files to allow run samples/drivers/adc example.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam usb drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam counter driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam i2c drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format. This add missing
i2c-0 alias into sam4l_ek board.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam spi driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam serial drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Aspeed ast10x0 series SoCs contain a ARM Cortex-M4F processor. This
processor operates at 200MHz and executes on SRAM.
This patch adds support for ast1030 as the first SoC of this series
which is targeted but not limited at the bridge IC in a server system.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I668af1ff8a36a05da791c3329ae08f5ae712bdd4
Enable pinctrl for ethernet mcux driver, and update kinetis DTS node to
include labelling for PTP node, to enable driver to access pinctrl
properties.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for MEC172x series to Microchip XEC PWM driver.
Standardize device tree properties for both SoC families.
Standardize device structure usage.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The datasheet for both sam4s/same70 specifies that the NRST pin
is an input after reset, used as a user reset.
Add the user-nrst property to match the default.
Fixes#43306
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add the parent controller device node plus the child nodes for all
GPIO pin banks managed by the GPIO controller to the device trees
of the Zynq-7000 and ZynqMP SoCs.
Device base addresses, IRQ lines, number of banks, number of pins
per bank and bank descriptions taken from the Zynq-7000 TRM (Xilinx
document ID ug585), the Zynq UltraScale+ TRM (Xilinx document ID
ug1085) and the Zynq UltraScale+ Devices Register Reference (Xilinx
document ID ug1087, web-based document).
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
add dtsi settings for rt series
dtsi use gpr to replace pinmux
nxp iomuxc has gpr which has more settings than mux and io settings
current solution is to export gpr separately and access then directly
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce ADC properties which indicated if the ADC instances have
dedicated channels for the internal temperature sensor or voltage
reference.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Don't set AFIOEN when enabling IO port clock.
The bit is set upon requirement within pinctrl
or pinmux
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
RT11xx USB PLLs source from 24MHz XTAL oscillator. Add this oscillator
as a clock source for the usb dts entries for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add power management code for the RT10xx SOC. By default, the code will
simply gate the core clock and transition the SOC to WAIT mode when
sleeping, but if clocking hooks are register to reduce clock frequencies
these will be called as well, and the SOC core voltage will be lowered
for additional power savings.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Since we are moving to pinctrl, removing pinmux.c
from mec172x board folder and removing pinmux from dts
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
SOC specific wrapper files were used to include pinctrl DTSI files.
Remove these in favor of including pinctrl header files directly from
board pinctrl definitions.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Kinetis pinctrl groups need dummy pinctrl node to populate with pinctrl
options at the board level. Add one in each
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The Bluetooth HCI driver based on the RPMsg transport now uses the IPC
service module. The compatible Bluetooth sample - HCI RPMsg - has also
been migrated to the new IPC solution.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Add zephyr,memory-region compatible to SRAM1 nodes. These memory
regions are dedicated to the USB device controller for USB descriptors.
Fixes#43090
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
the stm32h725 family is mostly identical with the stm32h723 family with
the exception that the h725 family has an in-built SMPS.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@escolifesciences.com>
Add the 256 kB On-Chip memory area which is located at 0xfffc0000.
In conjunction with a corresponding 'chosen' entry at the board level,
equivalent to board device trees based on the Zynq-7000, explicit placement
of data in the OCM becomes possible, for example when setting up the GEM
Ethernet Controller's DMA area.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add a new hwinfo driver to get the reset cause on
SAM4S/SAME70/SAMV71 SoC series.
The user-nrst dts property has been added to enable external user
resets.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Unify the CAN controller configuration done in Zephyr devicetrees:
- Specify a resynchronization jump width (sjw) of 1 time quanta in SoC
devicetrees as this is the most common. Boards can override this if
needed.
- Specify a sample point of 87.5% as recommended by CAN in Automation
(CiA) in SoC devicetrees. Boards can override this if needed.
- Specify a bus speed of 125 kbits/second (arbitration phase) and 1
Mbits/second (CAN-FD data phase) in board devicetrees as this is what
is used by all Zephyr CAN samples.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Properly set both pull up and down flags explicitly when
making changes.
Properly implement disabling interrupts on a given pin.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
The current MCUX IGPIO driver assumes that the target SoC supports
the DR_SET, DR_CLEAR, and DR_TOGGLE functionality, but some do not
(namely, the M7 core of the i.MX8M Plus SoC). Current releases of
the MCUXpresso SDK IGPIO driver contain utility functions to set,
clear, and toggle pins which include provisions to support SoCs
with and without DR_SET, DR_CLEAR, and DR_TOGGLE, and this change
switches to using these utility functions.
Additionally, this change enables GPIO support on the mimx8ml8_m7
target.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.
Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.
In the same PR modify the DTS files and the linker scripts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The last 2k bytes of the data RAM is used by the booter in some npcx EC
chips. This commit adds a bootloader_ram DT node to describe this
additional layout of the RAM. As a result, we can determine the total
RAM size by adding the size of flash0, sram0, and bootloader_ram.
Also, this commit moves 64k bytes from the code RAM (flash0) to the data
RAM (sram0) for npcx7m7fc because its internal flash is 512K bytes.
(In the Chromebook application, we need the code RAM size <= half of the
flash size.)
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The application may not always use the PSL mode. Change the status of
node vsby-psl-in-list default disabled. The application can override it
when it wants to use PSL hibernate.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Added basic support for the RP2040 SoC. Support
includes booting and starting the kernel, on one
core only.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
As npcx9m3f/npcx9m6f needn't share the upper 2KB of data RAM to Booter,
let's fix the data RAM size from 62KB to 64KB for them.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
the pre-dic is not used in rt11xx series, but for driver compatible
with rt10xx we still need have it in dts
fixing: #42179
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Remove the "cpus" node from the SoC device tree. The Zynq-7000
comes with either 1 or 2 CPU cores. While all the different
models within this SoC family have different capabilities in
particular when it comes to the programmable logic part and
I/O pins, there is no difference between the XC7Zxxx (2 cores)
and XC7ZxxxS (1 core) models when it comes to the peripherals
integrated in the SoC. Therefore, it makes little sense to
add a zynq7000s.dtsi next to the existing zynq7000.dtsi whose
only difference is the CPU count. Instead, the "cpus" node,
containing the appropriate CPU core definitions for the SoC
the respective target is equipped with, shall be specified at
the board level instead.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Adds power state definitions for RT1170. Min residency times are loosely
derived from transition times into similar power states in the datasheet
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds power state definitions for RT1160. Min residency times are loosely
derived from transition times into similar power states in the datasheet
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:
- system reduces core voltage during sleep
- core clock can be gated in deep sleep
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Pin controller address is the same for all member of the
GEN3 SoC Series, but pinmux configuration is SoC specific.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This PR adds the different handling of temperature sensor for the
STM32L5 soc. In this soc, there are some calibration settings which
need to be applied for temperature conversion.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
Certain stm32 soc's have a single shared irq for all adc channels
on those soc's only a single channel is supported.
Added a Kconfig that enables a shared irq for stm32f2x, stm32f4x,
stm32f7x soc's. The shared IRQ uses a flag to limit the number of
interrupts defined to only 1. A shared irq handler is added which
determines which ADC instance the interrupt is for, it then calls
into the existing interrupt.
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
Add timer and pwm nodes. The structure follows a similar approach to the
one used by STM32. Timer nodes store all timer information (e.g.
pre-scaler), whereas the pwm nodes are children of the timer node
indicating a specialization of the multiple timer functionalities.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add timer and pwm nodes. The structure follows a similar approach to the
one used by STM32. Timer nodes store all timer information (e.g.
pre-scaler), whereas the pwm nodes are children of the timer node
indicating a specialization of the multiple timer functionalities.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
HSE clock frequency value depends on target.
It can't be defaulted.
Remove this property to ensure it is set properly for each target.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Assign unique memory-region attribute values for both OCM
memory areas so that the lower region starting at address 0
is identified as OCM_LOW, while the alternate location for
the OCM memory is identified as OCM_HIGH.
The updated linker command file will use those identifiers
for OCM section mapping based on which of the two OCM areas
is marked as 'chosen' at the board level.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Now in Zephyr only stm32f7 processors have by default provided support
for QSPI IP block.
The same IP block is also available in stm32h7 (with different offsets),
so proper DTS description shall be provided as well for it.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In npcx_itim_evt_isr, it updates the cyc_sys_announced variable and
then calls sys_clock_announce() to update the kernel curr_tick variable.
If an ISR handler with higher priority preempts the timer ISR after the
sys_clock_announce is updated and before the sys_clock_announce() is
called, it will read the wrong time when calling k_uptime_get() because
the cyc_sys_announced and the curr_tick are not synchronized.
The commit fixes the problem by raising the timer's interrupt priority
to the highest one (i.e. 1 in npcx's configuration).
This commit also moves the computation of the delta cycle inside the
spinlock in sys_clock_elapsed() to prevent another potential racing
condition.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Some STM32 series need to configure health test register
for proper RNG behavior.
In addition, some also require to write a Magic number
before writing the configuration.
Note: on stm32h7 not all product lines support this configuration.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
As Nordic SPI, I2C and UART buses can act as both slave and master,
these nodes can have different compatible properties, and are annotated
with a comment, instead of a compatible property. This forces boards to
put compatible properties in their definitions, which is unnecessary
boilerplate for most boards, as most boards acts as masters on these
buses.
Set master mode by default for these buses, to reduce boilerplate and
potential errors in board definitions. Boards that need to act as slave
nodes will just continue to override the compatible properties.
Likewise, existing boards that override this compatible property with a
master binding will not be affected by this change.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
The stm32u5 device has a single iwdg node entry and label
without any need for interrupt. Even if it exists the irq entry
is not required.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove the requirement for specifying #address-cells and #size-cells
properties for CAN controller devicetree nodes.
CAN controllers do not have a common concept of devicetree child nodes
and thus have no need for these properties. This is in line with
upstream Linux kernel devicetree bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
NPCX series used npcx-lvol-ctrl-map to record the GPIO & low voltage
control register map. However, GPIOE3 was configured as GPIOE6, which
is a non-existed pin. This commit fixes the GPIOE3 low voltage control
map.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
RT11xx can peripheral had incorrect clocking configuration in SOC clock
init code and DTS. Fix peripheral configuration.
Fixes#41251
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add board support for NXP i.MX8M Plus EVK. This board has the following
features:
Processor : i.MX8M Plus Quad applications processor
Memory : 32-bit LPDDR4 w/6 GB
eMMC 5.0/5.1 w/32 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 2x2 Wi-Fi 802.11b/g/n/ac and BT 4.2
2x Ethernet (1x w/ TSN)
PCIe M.2
2x CAN FD DB9 Female connectors
USB : USB 3.0 Type C for Power
USB 3.0 Type A
USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
When building for an STM32K010xB MCU, there is a deprecated properties
warning, which should be fixed by this PR.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
PSL_IN pin select register is Vsby power-up reset. When the other
core-domain-reset reset the chip, PSL_IN3/4 don't set to GPIO. This
commit adds PSL_IN3/4 to the pin select list in NPCX devicetree. So
these pins can be set to GPIO when the other core-domain-reset.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
GPT base address in the devicetree for the RT11xx SOC series was
incorrect, this commit fixes it
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a driver to enable the GPT timer on RT1xxx parts to be used
instead of systick as a clock source. The timer is set to run in reset
mode, and uses the low frequency 32kHz oscillator for power savings
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Include the mem-region bindings for the stm32 ccm nodes and set the name
in the current dtsi files.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Enable flexspi for RT11xx SOCs. This requires selecting the correct
KConfig symbol for the cortex m4 and m7 SOCs, as well as correcting an
error in the flexspi DTS node and updating the clock init for RT11xx
SOCs.
Note that in addition, the NXP hal must be updated to properly support
including the cache management driver for the Cortex M4.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
There is currently no information available about the XIP
addresses for the nRF52840 and nRF5340.
Add this via a new 'reg' block in the relevant QSPI nodes, along with
names for the register blocks so they are easier to retrieve.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
GPIO10 was missing from RT11xx DTS, and is required to manage SD card
power. Enable this GPIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
MCUX PWM driver used hardcoded clock source. update driver to use clock
bindings to determine PWM peripheral clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use nrfx_gpiote and nrfx_ppi allocators to allocate channels
at runtime instead of fixed, device-tree based allocation which
is harder to maintain.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.
Changes include:
- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add the USB On-The-Go Supplement, Revision 2.0 in the DTS
of the stm32u575 and stm32u585 devices
(not for the stm32U5 serie).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix register addresses in rt11xx SOC dts. Flexcan1 was defined with an
incorrect register address, and watchdog 3 was incorrectly labelled as
watchdog 1. Watchdog 2 should not be enabled, as it is only accessible
from code running in the trustzone context.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add baseline support for mimxrt1160_evk Cortex M4 and M7 cores
UART shell, synchronization, and hello world have all been verified to
build and run correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert all in-tree NXP FlexCAN instances from hardcoding the CAN bus
timing in time quanta to specifying a desired sample point of 87.5% as
recommended by CAN in Automation (CiA).
This allows for the CAN driver to calculate the optimal time quanta
based on the CAN clock and the requested CAN bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface
to access the SPI flash. This commit adds the driver support for it.
With this commit, the application can call the flash APIs
(via spi_nor.c) to access the internal flash of NPCX EC chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
Add SoC-specific code, the basic device tree and Kconfig data as well
as the corresponding linker command file for the Xilinx Zynq-7000
family of SoCs. This SoC - either as a QEMU simulation or on actual
hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini-
tial target for the ARMv7 Cortex-A support.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add a dedicated compatible for STM32MP1 clock control node.
Since, on such platform, clock configuration is done on A9
side, only the clock-frequency property is available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a DTS description of timer5 to: STM32G474, STM32G484, STM32G473,
STM32G483, and STM32G471
Add a DTS description of timer5 to: STM32G474, STM32G484, STM32G473,
STM32G483, STM32G491, and STM32G4A1
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Adds SPI support on LPSPI1 to the RT1010. LPSPI1 is available on pins
6, 8, 10, and 12 of J57 on the evaluation board
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit enables the LPSPI1 peripheral on the RT1015 EVK. LPSPI pins
are not populated by default, but headers can be added to J19 on the EVK
to access these signals
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The maximum supported speed according to the SX126x datasheet (I have
not found that information in the STM32WL datasheet or reference
manual). Increase the Sub-GHz SPI frequency from 1 Mhz to to 12 MHz,
which corresponds to a baud rate prescaler of 4 with a 48 MHz clock. It
also matches what is done the the STM32CubeWL package.
This reduces the time the MCU is kept running, thus reducing the global
power consumption.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This adds the uart4 device to the stm32f3_disco board
based on the stm32f303 device from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds stm32f103xd series dts file that was missing.
Also, changed stm32f103xe.dts for highlighting the differences between
f103xd and f103xe series.
Signed-off-by: Deimantas Aukštkalnis <deimantas.aukstkalnis@teltonika.lt>
Since version 1.11.0, Full stack M0 binary requires 216K of flash
being available, while previously 212K were required.
Review flash partitioning to take it into account.
Additionally:
- update value in board yaml file.
- align value in package .dtsi file
Fixes#38735
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The NPCX I2C implementation contains two modules, an I2C port and an
I2C controller. Disable the I2C controller nodes by default and require
the user to enable both the I2C port and controller in the devicetree.
Signed-off-by: Keith Short <keithshort@google.com>
Fix a typo bug where sercom5 pinctrl has pad2 and pad3
has duplicated pads for pb0/pb2 and pb1/pb3.
Per the datasheet, pb2 and pb3 should be pad0 and pad1 respectively.
Signed-off-by: Ron Smith <rockyowl171@gmail.com>
The priority of the LPTim interrupt on each stm32 soc
is put at the same level as the SysTick. This priority
level is given by the system Handler priority reg
(SHPR3) when the PM is not configured.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
stm32f411 includes stm32f401 which do already correctly define spi4
The definition in stm32f411 was missing a clock attribute
Signed-off-by: Kim Bøndergaard <kim.boendergaard@escoglobal.com>
stm32f410, stm32f411 and stm32f412 enable the SPI5 device with
bit 20 on the APB2 clock
Signed-off-by: Kim Bøndergaard <kim.boendergaard@escoglobal.com>
Add a shim that allows using the nrfx PDM driver via the Zephyr API.
Add also missing devicetree nodes representing the PDM peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-pdm" binding with a new property that allows
specifying the clock source to be used by the PDM peripheral (so that
it is possible to use HFXO for better accuracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
add correct binding, fix size to 32MBit, add erase and write
block size to support mcuboot and rename to reflect the actual
flash model.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Atmel sam0 adc peripheral have multiple interrupt vectors for same5x
devices. This configure interrupt vector by name to ensure that proper
interrupt handle will be executed.
Fixes#37779
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Compatible "soc-nv-flash" was removed as part as #38077,
while it should have been kept, similarly to what was done
on other SoCs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The max-erase-time property was introduced for the STM32 flash driver,
but it was inserted as an optional property in the generic
soc-nv-flash binding which is used by other SoCs.
Make it a required property in a new st,stm32-nv-flash binding
instead, since it is at present a vendor specific property.
Update the DTS files accordingly. Keep the existing "soc-nv-flash"
value in the compatible list in each case, so that DT_HAS_COMPAT(...
soc_nv_flash) tests on these nodes will still succeed, but put it
after a newly added "st,stm32-nv-flash" compatible, so that the
SoC-specific binding will be used as it is discovered first by the DT
tooling.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Change IPM_STM32_HSEM Kconfig definition so that it picks the correct
default automatically depending on which cpu node is enabled in the
device tree, rather than relying on board specific Kconfig overrides.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add Digital-to-Analog Converter driver (based on DACC module) for Atmel
SAM MCU family. Only SAME70, SAMV71 series devices are supported in
this version.
Tested on Atmel SMART SAM E70 Xplained board.
Origin: Original
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Microchip MEC172x series I2C driver implementing controller
and target modes. The driver implemenents its own I2C port
pin control functions and does not depended upon pinmux. Future
updates will make use of PINCTRL when that subystem is finalized.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Following change of HSE clock binding, remove hse-bypass
which is no longer an option and replace it with hse-tcxo
which is the configuration closest to previous status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Like the first instance of the dma in the stm32l3xx soc,
the second DMA instance of the stm32f373 is of the same type
V2bis (dma request is fixed (no dma-slot).
The dma-cell has channel and config.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add missing RADIO and EGU nodes. We already have compatibles for
these defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing EGU nodes. We already have a compatible for
these defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing RADIO and EGU nodes. We already have compatibles for
these defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing EGU and TIMER nodes. We already have compatibles for these
defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing RADIO and EGU nodes. We already have compatibles for these
defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing RADIO and EGU nodes. We already have compatibles for these
defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing FICR, UICR, RADIO, and EGU nodes. We already have
compatibles for these defined, and the peripherals are present, so
define them for consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing FICR, UICR, RADIO nodes. We already have compatibles for
these defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The way we currently handle direction finding extension (DFE) support
on Nordic nRF5 controllers relies on required devicetree properties
related to DFE in the "nordic,nrf-radio" node.
That doesn't make sense on radios without DFE support, though.
Any .dtsi for an SoC without DFE support which has such a node would
require extraneous DFE related properties like dfe-antenna-num.
Instead of making the properties required, mark them optional. We
indicate the presence of DFE support via a new 'dfe-supported' boolean
property which the SoC .dtsi files can set (or not) depending on
support.
This gives us the opportunity to do some cleanup in the Kconfig,
removing CONFIG_HAS_HW_NRF_RADIO_BLE_DF since we know from the
devicetree whether DFE support is available.
Handle that change appropriately in radio_df.c. This gives us an
opportunity to improve readability in the devicetree-related macro
magic in that file.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Sort by unit address. This involves multiple files since there are
includes and secure/non-secure files to deal with.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Renames stm32g0 tim1 brk interrupt to brk_up_trg_com, such that the
naming aligns with stm32f0 series and drivers can find the interrupt
with a common name.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add ADC driver version 2 for MEC172x using new in-tree headers
and device tree properties. Update the ADC shell for the new driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The psoc6 SoC has 2 cores, each with different allowed priority ranges:
CM0: 0-3 (2 bits of NVIC prio, no prio reserved by the kernel)
CM4: 0-6 (3 bits of NVIC prio, one level reserved by the kernel)
Since some of the peripherals are only available to the CM4, those
should be set to a priority that is actually valid for it. In this case
the lowest possible one is 6, so transition from 7 to 6.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Microchip XEC has been using the standard NS16550 driver.
Using the standard NS16550 driver requires extra HW programming
for XEC UART in board level and did not support XEC GIRQ interrupt
programming. We add an XEC specific driver and remove UART specific
register programming from the board level and implement interrupt
support. Also, by implementing a SoC specific driver we can add
driver PM in the future.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Microchip XEC two custom DT properies girqs and pcrs cell sizes
are defined as constants. There is no need to replicate these
is the chip DTSI since the value cannot be changes. Fix the syntax
of the cell size constant to match the naming convention used
thoughout DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The ipm_stm32_hsem driver is a virtual mailbox based on STM32 HSEM.
Since we already have LL_HSEM(low-level HSEM) API on the hal_stm32
module, looks there is no need to implement a new HSEM driver.
But there are still have some limitations, the HSEMx interrupt is
not shareable. If another HSEM user wants to use the HSEMx interrupt,
the ipm_stm32_hsem mailbox needs to be disabled.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
We try to reduce the ambiguity between 'soc/nuvoton/' and
'soc/nuvoton_npcx' folders. Most if soc vendors name their soc folder by
the company name with SOC_FAMILY suffix instead of the company name
directly. It is clearer if the soc company has different product lines
that aim to specific markets.
In this CL, the 'numicro' suffix is used for Nuvoton Microcontroller
production line. It distinguishes the 'npcx' suffix that used for
Nuvoton Embedded Controller (EC) of Notebook PC product line.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Update the Microchip XEC pinmux driver to use system I/O
routine for read/write of registers instead of direct use
of volatile and CMSIS defines. Add GPIO port number to
bindings instead of using hard coded value from chip headers.
Modify SoC DTSI pinmux syntax, requires "pinmux: pinumx {..."
or the DT macros will not work. Since pinmux is used by MEC152x
we update its chip pinmux DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The booter (bootloader) behavior may be different in different NPCX
chip series. One example is that the booter sets host interface type in
NPCX7 series but leave the firmware to set it in NPCX9 series.
This commit adds a new DT node to record variants in its properties.
NPCX drivers can understand if they need to configure the related
setting by checking the node's properties.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
dtc v1.6.1 produces an error without specifying #address-cells
on an interrupt-controller node.
Fixes#36495
Signed-off-by: Eric Johnson <eric@liveathos.com>
Add watchdog support to the mimxrt685 platform.
The mimxrt685 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt685 does not retain this memory through a
reset.
Signed-off-by: David Leach <david.leach@nxp.com>
Add Atmel sam0 sercom[uart] pinctrl bindings and implements pinctrl at
driver level. It changes all sam0 boards to use new feature and remove
pinmux driver dependency for sercom[uart]. The samples that require a
binding were update to keep consistency and avoid errors.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add initial basic description for Cortex-M33 based
stm32u5 soc series.
This encompass description for base nodes, such as:
- cpu
- flash
- clocks
- sram
Additionally, provide description for variant stm32u575Xi.
Related to clocks nodes, added bindings for stm32u5 specific
rcc node as well as msi and pll clocks.
Header file stm32_clock_control.h was also updated to support
these new bindings.
Note that for compatibility with existing definitions, clock
node describing main pll clock, known as "PLL1", was given two
labels: "pll" and "pll1".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The type of DMA for the stm32f0 devices was wrong
Its DMA is of type V2bis where the peripheral request is fixed.
The corresponding DMA cell has 2 elements.
The stm32f091 has two DMA instances.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a shim that allows using the nrfx I2S driver via the Zephyr API.
Add also missing devicetree nodes representing the I2S peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-i2s" binding with a new property that allows
specifying the clock source to be used by the I2S peripheral (so that
it is possible to use HFXO for better accurracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Create version 2 of the MEC GPIO driver to support MEC172x to not
interfere with MEC152x. When the MEC172x ECIA interrupt aggregator
driver is ready, this driver will use ECIA for registering GPIO
interrupt callbacks instead of maintaining its own interrupt table.
Add V2 DT binding.
Add the Kconfig configuration settings for the MEC172x GPIO
V2 driver at the SoC and board level.
Add port id to DT allowing use of DT FOR EACH macro in the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This CL moves the phandles which don't contain 'reg' prop. from 'soc' to
'soc-if' node since they are the interface phandles only. It also
prevents "missing or empty reg/ranges property" warning messages.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
In the eeprom read operation, when rambuf was available
mutex was not unlocked after the read. Consequence of that is
that device was blocked after that read for incoming operations.
This commit fixes the issue
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add basic counter driver based on Timer Counter (TC) module for Atmel
SAM family.
Remarks:
- The driver is not thread safe.
- The driver does not implement guard periods.
- The driver does not guarantee that short relative alarm will trigger
the interrupt immediately and not after the full cycle / counter
overflow.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit adds dt definitions for the hw aes accelerator
on stm32g0 Series.
The accelertor is available on the following socs:
stm32g041, stm32g061, stm32g081, and stm32g0c1.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds a dt node for the hw aes accelerator of the
stm32l5 series.
The stm32l562Xe.dtsi file now includes the newly created
stm32l562Xe.dtsi with the additional aes definitions instead of the
stm32l552Xe.dtsi file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Each stm32 dma can be of V1 or V2 or V2bis type. Each type
has a dma-cell with specific nb of element. The feature and slot
properties are not required depending on the stm32 family.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This adds the dts to PASS the tests/drivers/dac/dac_loopback
on the nucleo_f429zi board, when PA0 and PA4 are connected.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
reuse the lpc's lpadc driver for rt1170, modify the dts and add
some macro to shield some code of LPC series. Also add the
board support inside the tests/drivers/adc/adc_api/src/test_adc.c,
and a dts node:zephyr,user inside
samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay
Signed-off-by: Crist Xu <crist.xu@nxp.com>
Adding support for the stm32l051 devices.
Signed-off-by: Even Falch-Larsen <even.falch.larsen@nomono.co>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added minimal device tree and board files to build Microchip
MEC172x. SOC layer stripped down to allow build for checking
compilation only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The zephyr sam gmac driver don't get register address and, in some
cases, peripheral id from devicetree. This replace headers constants
in favor of devicetree values.
This fix wrong Atmel SAME7x/SAMV7x gmac register address and add
missing peripheral id property for SAM family.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current GMAC compatible not allow especialize properties by SoC
family. Split current generic Atmel GMAC compatible into two new
compatibles which are defined by SoC families. This increase the
freedom and avoid odd situations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Define the subghz radio node in the module dtsi file, with the internal
RF switch connection and TCXO setting, and point at it from the
corresponding dev board file.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add a device node for the subghz radio in stm32wl.dtsi. The radio is
present in all chips of the series, so having the node there with the
common properties simplifies the board dts files.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This adds support for controlling the SUBGHZSPI NSS line in STM32WL
devices. This is a special dedicated SPI port only connected to the
radio device internally, chip select happens through a bit in the PWR
module. Adding a special dt-property to identify the port, it all gets
built out on non-WL devices.
Deduplicate the existing dts bindings in the process, and add the new
one for the special spi with the new property.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add I2C bus initial support to Renesas R-Car SoC series.
Both I2C2 & I2C4 buses are supported on R-Car H3 board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit adds the dt node for rng to the stm32wl series
and sets it as chosen zephyr,entropy source.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds support for stm32g0 socs with integrated rng and hw aes
acceleratior, which are stm32g041, stm32g061, stm32g081, and stm32g0c1.
It also adds the definitions for the rng peripheral
and sets it as chosen zephyr,entropy source.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds the dts definitons for the seeed lora-e5 module.
Additionally I add myself as codeowner for the new dts/arm/seeed
directory.
This module packages a stm32wle5jc Sub-GHz Wireless Soc,
together with a 32MHz TCXO, a 32.768KHz crystal oscillator, and
power and RF circuitry.
With the introduction of lora support definitions for the radio
will be added in a future commit.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds dt support for stm32wle4, and stm32wle5 single core,
as well as stm32wl54 dual core socs.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds dma1, dma2, dmamux support in dtsi for stm32l5
series. This commit also fixes a compilation warning due to the
usage of upper case in "reg = <0x4000F400 0x400>".
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
add devicetree node for usart4 and usart5. usart4 and 5
shares the same interrupt line (14), hence both can't be enabled
at the same time.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Nuvoton provides different series MCU. The NPCX series has a specific
id, which can identify the real chip part number. This CL adds soc id
for the NPCX series.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This commit adds max-erase-time element which holds the
maximum erase time of a sector or page or half-page for
all the series of stm32.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Add the lptim1 device node definition and enable the corresponding
exti interrupt in sys_clock_driver_init().
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The PS/2 module in npcx provides a hardware accelerator mechanism
including an 8-bit shift register, a state machine, and control logic
that handle both the incoming and outgoing data. The hardware
accelerator mechanism is shared by 4 PS/2 channels. To support it,
this CL separates the PS/2 driver into channel and controller drivers.
The controller driver is in charge of the PS/2 transaction. The channel
driver is in charge of the connection between the Zehpyr PS/2 API
interface and controller driver.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Add a device node for the FMC controller found in stm32f427, f437 and
f446 devices, works fine with the current memc_stm32_sdram driver.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The NXP LPC syscon driver failed to build on several platforms for
various reasons. We need dts support on LPC55s1x and LPC55s2x, the
driver doesn't seem like it will work on LPC54114 so we exclude it
there for now.
Additionally, fix a dtc warning on LPC55s6x based on unit-address in
the node naming needing to be lowercase.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The atmel pwm driver doesn't have a easy way to test and show
functionality to users. This re-assign led-0 function from
gpio-leds to pwm-leds. The current led-0 entry at gpio-leds
was keep with status disabled, as refence. It allows test pwm
driver for SAM Cortex-M7 MCUs. The led-1 assume Zephyr sample
default led0 alias.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add the device tree data for the 4 Ethernet controllers integrated into
the ZynqMP SoC, GEM0 to GEM3.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit fixes the compilation warning occurred due
to usage of upper case in "interrupt-controller@4000F400".
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit adds PWM support in dtsi for stm32l5 series. Adding
other timer nodes for different stm32l5 series PWM capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
GPIOTE1 on the nRF5340 SoC is always accessible as a non-secure
peripheral. However, it is only defined in the non-secure DTSI file.
This is therefore a missing node in the secure DTSI file, since
non-secure addresses are accessible by secure software.
Move the node definition to a common include file and pull it into the
app core DTSI as well. To keep things clean, adjust the node labels so
that:
- 'gpiote0' and 'gpiote1' are defined in the secure DTSI
- 'gpiote0' is not defined in the non-secure DTSI
- 'gpiote' is defined in both secure and non-secure DTSIs
- 'gpiote' refers to the same node as 'gpiote0' in the secure DTSI
- 'gpiote' refers to the same node as 'gpiote1' in the non-secure DTSI
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The sram1 node in nrf5340_cpuapp.dtsi represents the SRAM accessible
to the network core on the SoC.
However, while the network core can access the app core's SRAM, the
app core cannot access the net core's SRAM. Therefore, the sram1 node
should only appear in DTSI files for the net core, and not the app
core.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The RAM of can instances starts directly after it's predecessor.
This commit fixes can2 and can3 support for stm32g4 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Property "st,prescaler" of binding "st,stm32-pwm" was set to 2
different default values 0 or 10000 in *.dtsi files.
Since this property rather depends on application than hardware
description, there is no reason to have 2 different default values
in use. Besides, it is a trap for pwm users that should take into
consideration this random default value.
Fix this by defaulting the property systematically to 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add radio peripheral to nrf5340_cpunet DTS. The peripheral
description includes antenna matrix congiuration for Direction
Finding extennsion.
Appropriate binding file for nRF radio peripheral already egxists.
There is no default antenna matrix configuration. Antennas number
and GPIOS mapping to DFEGPIOS is project specific.
Complete configuration must be provided by end user as overaly.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Moved can, spi, usb, usb_fs_phy nodes to f103X8 dts.
Adds CAN for f103X8 series.
Tested on stm32f103c8 soc.
Tested on stm32f103vb soc.
Signed-off-by: Bhavesh Bhojwani <bhaavesh.bhojwaani@gmail.com>
Add radio peripheral to nrf52820 DTS. The peripheral description
includes antenna matrix congiuration for Direction Finding extennsion.
Appropriate binding file for nRF radio peripheral already egxists.
There is no default antenna matrix configuration. Antennas number
and GPIOS mapping to DFEGPIOS is project specific.
Complete configuration must be provided by end user as overaly.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This commit adds DAC1 support in dtsi for stm32f3 series. Some
stm32f3 series has DAC2 so adding the same where applicable.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit adds a closing parenthesis for soc model of stm32g050.
Resolves issue #36014
Signed-off-by: Bhavesh Bhojwani <bhaavesh.bhojwaani@gmail.com>
Since the valid bit-depth of RAM_PDn registers are different, this CL
introduces a 'ram-pd-depth' property in 'nuvoton,npcx-pcc' node if the
application needs to turn off the partial ram blocks for better power
consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Arrange device-tree files of npcx7 series by following steps:
1. Move device-tree declarations of npcx family to npcx.dtsi.
2. Leave specific device declarations of npcx7 series to npcx7.dtsi.
3. Move chip series related mapping tables such as
npcx7-miwus-wui-map.dtsi and so on to npcx/npcx7 folder.
4. Move common device-tree declarations used in each npcx series to
npcx-miwus-wui-map.dtsi and so on to npcx folder.
Then, the npcx device-tree folders are arranged to:
dts/arm/nuvoton
|--npcx
| |--npcx7
| | |--npcx7-miwus-wui-map.dtsi
| | |--npcx7-alts-map.dtsi
| | |--.....
| |--npcx-miwus-wui-map.dtsi
| |--npcx-alts-map.dtsi
| |--.....
|
|--npcx.dtsi
|--npcx7.dtsi
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces series-prefix "npcx7-" with family-"npcx-" for npcx dts
nodes such as 'espi-vws-map' and 'miwus-int-map'. Since we plan to
introduce the npcx9 and later series, adding a new node such as
npcx9-espi-vws-map for each series is more complicated and not
necessary.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a port property to describe which hardware port a GPIO device node
is describing since we can't tell from the registers (as the registers
are interleaved in the same MMIO space).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove (disabled) MPU support for the NXP Kinetis K2x. At least the
MK22F51212, which is the only K2x supported by Zephyr so far, does not
contain an MPU.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The change removes the following warning:
Warning: /soc/tc@4000C000: simple-bus unit address format error,
expected "4000c000"
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Device Tree address mixup between
SAI2 <-> SPI2 and SAI3 <-> SPI3
Add functionality to SPI2/3
Tested on SPI2
Signed-off-by: Rico Ganahl <rico.ganahl@bytesatwork.ch>
Switch the interrupt controller address to lower case to avoid this
warning:
stm32f723e_disco.dts.pre.tmp:97.39-102.5: Warning (simple_bus_reg):
/soc/interrupt-controller@40013C00: simple-bus unit address format
error, expected "40013c00"
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
add dts bingings for dma usage
add dts support for adc with edma and hwtrigger
add a periodic_trigger feature to dts
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Add SCIF bus initial support to Renesas R-Car SOC series.
SCIF1 is used as main serial and shell output on R-Car H3 board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Commit 233149eec5 moved flash sram nodes
under /soc for various nordic ICs, but the indentation isn't right for
52811. Fix it.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
For dmamux nodes the dma-requests property specifies the number of
peripheral request inputs(not nr. of request trigger inputs).
This commit fixes this for g4 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
reg value should match value provided within node name (as in pll@2).
Fix this to avoid warning.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
As the KW2XD is a SiP (System-in-package) the SPI1 controller on the MCU
is connected to the modem. As the pinctrl details for this in the
SoC dtsi file as these pins are not exposed in the pindata XMLs from
NXP.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Set SPI0 controller to default to being disabled in SoC dtsi files and
having the board dtsi files enable it. The only board that wasn't doing
this already was the frdm_kw41z.dts.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add clocks node and clocks to stm32l5 series.
PLL binding is reused from stm32l4 series.
Matching binding is updated to document that.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks nodes for F0/F3/G0/G4 series.
For F0 and G0 series, update compatible for rcc node
to specify use of dedicated "st,stm32f0-rcc" compatible.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove default pll settings to ensure pll users are correctly
configuring all prescalers on purpose and avoid surprises.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds flash clock settings in device tree for stm32h7
series such that the stm32h7 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The current serial driver uses hard code configuration. Rework driver
to use pinctrl and enable full configuration from device tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Provided nodes reflect the clock tree of each series.
Clock nodes are disabled by default but populated with default
start up configuration. Main reason is the we don't want to
impact boards using Kconfig based clock configuration for now.
Exception to these rules:
- syslck: Default enabled, clock frequency and clock source not
provided
- pll: clock source not provided
This is made on purpose so that errors are triggered if parameters
essential to the board configuration are not provided.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
i2s1 is not present in all stm32f4 series. So moving the i2s1 node
from the top level stm32f4 dtsi file to the stm32fxx specific dtsi
files. Also in stm32f429zi, the sequence starts from i2s2, this commit
helps in having the right channel number.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
STM32G0 is supported by the st,stm32-dma-v2 driver.
This commit adds dma1 and dmamux dts bindings
for stm32g03x, stm32g05x and stm32g07x.
For stm32g0bx additionally dma2 is added.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This patch adds flash clock settings in device tree for stm32wb
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32l4
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32l1
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32g4
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32g0
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Enabling pwm on timer3 for stm32l1 series in dtsi.
Adding other timer nodes for pwm capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Renesas RCar Gen3 series have up to 8 GPIOs
bank.
Add bank 5 and bank 6, that is used to manage user led and
switches on different demo board.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The Compare match timer can be found on Renesas
RCar Gen3 soc series.
It depends on clock controller to supply clock to the
CMT module.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.
- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2
Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).
This first SoC definition is just enough to print Hello World in a
ram console.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Enabling PWM on timer1 for STM32F2 platform in dtsi.
Adding other timers nodes for PWM capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Define the FLASH_CCFG memory region from a devicetree partition instead
of from math in the linker file. Removing the special math case results
in the FLASH_CCFG region overlapping the FLASH region, but the linker
accepts this until the FLASH region actually starts placing variables
in the FLASH_CCFG region.
As a result, applications that don't fit in (FLASH_SIZE - 88) bytes will
still fail to link, just with an overlapping memory region error instead
of an overflow error.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Move the definition of the two IPC RAM blocks from `#define`'s in family
linker scripts to proper devicetree nodes. Use the devicetree nodes to
generate the memory regions.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Fixed the name of nodes in in espi-vw, miwu-wui, and miwu-int
device-tree node. This CL fixed missing nodes in CL d3a94fa8ab.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The following is the interrupt priority plan for ec application.
The original IRQ priority map in Chromium EC is:
- IRQ priority 0:
|-ITIM IRQ for Warning watchdog.
-IRQ priority 1:
|-UART IRQ for signle byte FIFO in npcx5 series.
(Ignore it since UART has 16 bytes FIFO in npcx7 and later series.)
-IRQ priority 2:
|-SHI IRQ for FIFO FULL and Half FULL event.
|-MIWU IRQ for SHI CS. (Wake-Up ASAP for handling data from SPI bus.)
-IRQ priority 3:
|-All MIWU IRQs for GPIO, MTC and eSPI VW events.
|-ITIM IRQ for task scheduling.
|-ITIM IRQ for time-out.
(No need in Zephyr since 64-bit timer support.)
IRQ priority 4:
|-All UART FIFO IRQs
|-All I2C controller IRQs
|-ADC IRQ for conversion event.
|-ESPI IRQ for generic eSPI bus events.
|-Host KBC IBF/OBE IRQs
|-Host PM IBF/OBE IRQs
|-Host port80 IRQ
|-PECI IRQ
IRQ priority 5:
|-Keyboard RAW IRQ
|-PS2 IRQ
Then, this CL arranges the priority of npcx interrupts in Zephyr as:
IRQ priority 0:
|-Reserved it for further requirements.
IRQ priority 1:
|-SHI IRQ for FIFO FULL and Half FULL event.
| (Will modify it in ec repo.)
|-MIWU IRQ for SHI CS (Will modify it in ec repo.)
IRQ priority 2:
|-MIWU IRQ for GPIO, MTC, T0 timer and eSPI VW events.
|-ITIM IRQ for task scheduling.
IRQ priority 3:
|-All UART FIFO IRQs
|-All I2C controller IRQs
|-ADC IRQ for conversion event.
|-ESPI IRQ for generic eSPI bus events.
|-Host KBC IBF/OBE IRQs
|-Host PM IBF/OBE IRQs
|-Host port80 IRQ
IRQ priority 4:
|-Keyboard RAW IRQ. (Will modify it in ec repo.)
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Cortex M0 Series only have two interrupt priority bits,
nevertheless all series set the priority per default to the invalid
value of 7.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fixed the name of nodes in device-tree files by following rules:
If object is 'phandles', use underscores for object name.
If not, such as 'node' or 'property', use hyphens for object name.
This CL also applies normal style for all nodes in npcx device-tree
files.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The adc1 of the stm32f373 uses an address space and a bus that are
different from the other microncontrollers of the f3 family. So, let's
remove the adc1 node from the stm32f3.dtsi and add it directly, with
respective correct values, in each of the SoC variant files.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
STM32L011 and STM32L031 do not support USART1.
This commit moves the definition of the node to only
be present for MCUs which support the peripheral.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
TIM7 peripheral was defined for all STM32L4 chips
in the device tree when not every chip supports it.
This commit moves the node so that only chips
which support the peripheral have the node defined.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
The device tree includes CAN node can1 for all
STM32L4 chips when in fact they don't all support it.
This affects STM32L412xx and STM32L422xx.
Fixes#33896
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit creates two new files in the device tree
1. stm32l412X8.dtsi
2. stm32l412XB.dtsi
This will specifcally add stm32l412X8 to the device tree
which was not supported before. Also the memory
for stm32l412XB was not defined specifically before.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
Add remaining NXP KE1xF SoC dtsi files to support out-of-tree boards
using other variants of the KE1xF than the single in-tree board.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add dts files for the specific chip instances that are used on the
boards in prep of having pin data in devicetree. The pin data will
be specific to the given chip instance so we need to distinguish
unique chips for the same SoC as the pin mux will differ.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch introduces the support of the Low Power Timer
for the STM32L5xx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enabling I2C-1,2,3 support for STM32F2 platforms in dtsi.
This has been tested with mpu6050 sample application on I2C-1.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Enabling SPI support for STM32F2 platforms in dtsi.
This has been tested with test_spi_loopback on SPI-1.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This CL introduces the Power Switch Logic (PSL) pads which detect the
wake-up events and turn on/off core power supply (VCC1) for ultra-low
-power consumption in npcx device-tree file.
By adding PSL input-pad objects, psl_in1, psl_in2, and so on, into
'psl-in-pads' property and configuring their 'flag' properties, the
related driver will configure them via soc specific functions later.
For example, if PSL input 1 pad that is plan to detect a 'falling edge'
event, this property should be:
vsby-psl-in-list {
psl-in-pads = <&psl_in1>;
};
And the flag property in psl_in1 should change to
&psl_in1 {
flag = <NPCX_PSL_FALLING_EDGE>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add dmamux1 dts bindings for stm32h7
series. Note that there is no dedicated
clock to enable for dmamux1 so we set the
clock of dma1. This is the way linux handle
this.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Fix the clocks bindings of dma1 and dma2
for stm32h7 series. This is wrong probably
due to copy and paste.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
In the change to DTS driven clock divider values wrong values
were used in the dts file.
Fixes: #33559
Signed-off-by: David Leach <david.leach@nxp.com>
Add initial support for the Cortex-M55 Core which is an implementation
of the Armv8.1-M mainline architecture and includes support for the
M‑profile Vector Extension (MVE).
The support is based on the Cortex-M33 support that already exists in
Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Restructures dts files(value line definitions are no longer included by
others), and adds additional devices(g05x and g0bx).
All newly added timer pwm prescalers are set to 0.
lpuart1 is moved from stm32g0.dtsi to stm32g031.dtsi, as it is not
available on stm32g0x0 soc.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
"interrupt-names: combined" propterty is only used for stm32 i2c driver,
remove all other existing occurences for stm32g0(adc, lpuart, usart).
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add optional maximum-speed parameter to USB nodes. This affects all
defined stm32l4xx, except stm32l4rx and stm32l4sx
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
This parameter is defined for stm32f405 which and is included into
stm32f469. The include order is as follows:
st/f4/stm32f4.dtsi
st/f4/stm32f401.dtsi
st/f4/stm32f405.dtsi <-- ram_size defined here
st/f4/stm32f407.dtsi
st/f4/stm32f427.dtsi
st/f4/stm32f429.dtsi
st/f4/stm32f469.dtsi
Refer to Application Note AN4879 from ST to view ram size for each MCU.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
Introduce PSoC-6 pinctrl infraestructure and definitions. This add
files to handle devicetree entries and following modifications:
- add pinctrl bindings
- update gpio bindings with pin-cells
- add pinctrl node and move gpio nodes inside
- declare pinctrl for current uart entries
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add GPIO definitions to QuickLogic EOS S3 devicetree.
Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
In some stm32 series systick was disabled in order to
allow alternate use of lptim timer as kernel low power ticker.
Doing this, dts based definition of CORTEX_M_SYSTICK Kconfig symbol
is disabled and CORTEX_M_SYSTICK was redefined with 'default y'
in stm32 soc files which makes things more complex to handle to
alternate with LPTIM activation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To keep the generic DMA device name as defined
in the dma framework config, renamed paxdma device
label to "DMA_1".
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.
The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
add CAN_1 and CAN_2 hw modules support
Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add device tree nodes for the Digital-to-Analog (DAC) modules present
in the NXP Kinetis K2x series.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Change dfe-ant-num propert name to dfe-antenna-num.
The change is conde to keep the same naming style
for all properies, like dfe-pdu-antenna property.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Add initialization of GPIOs that are used for antenna switching.
GPIOs provided to DFE extension in Radio peripheral, to drive
antenna switching, should be initialized in GPIO peripheral beforehand.
The initialization is optional and may be disabled by Kconfig.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Add quadspi node in stm32f7.dtsi and quadspi support to boards
stm32f746g_disco and stm32f769i_disco.
Note! Does not support DMA.
Signed-off-by: Helge Juul <helge@fastmail.com>
NPCX chip allows firmware to select the JTAG0/1 via bit 2/1 in the
DEVALT5 register. However, the selection logic is reverse
(i.e. 0:select; 1:not select.)
This change fixes the wrong setting of the invert field.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I2c080feaa7647e940463d9491b61a342c84a6141
The size of System Configuration register cannot exceed 0x70. Otherwise,
it will overlap the Debug Interface register which starts from
0x400c3074.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add device tree nodes for QDEC peripheral instances
for nRF5340 Application core.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We've removed the need for label properties from the pinmux devicetree
nodes on all other controllers and its not required for the TI one, so
remove it from the .dts and drop label being required in the binding.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add ESPI SAF features to the Microchip eSPI driver as
a separate file. ESPI SAF depends upon the core eSPI
driver adding the ability to attach the system SPI
flash to the EC eSPI endpoint instead of the host
eSPI controller.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
nxp_k2x.dtsi: Corrects Multipurpose Clock Generator binding
to utilize nxp,kinetis-mcg. Assign MCG to FlexTimer devices.
Enable FlexTimer clocks via System Integration Module clock
gate control registers.
Kconfig.defconfig.mk22f12: Enable default use of
CLOCK_CONTROL_MCUX_MCG when CLOCK_CONTROL is selected.
Signed-off-by: Ryan Holleran <rhollerar@gmail.com>
This CL moves def_lvol_io_list device-tree node from npcx7m6fb_evb.dts
to npcx7m6fb.dtsi. The benefit of it is that we needn't add
def_lvol_io_list node for each board dts file if there are no 1.8V
io-pads on the platform. If so, add them in the specific board dts file
directly.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In the wake of the removal of nRF5340 PDK board we also
remove the support for the nRF5340 Engineering A SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The compatible for the ARMv8 timer should have been arm,armv8-timer and
not arm,arm-timer. The dts binding file name was correct, just the
compatible was wrong. Rename dts, binding, and associated code to use
arm,armv8-timer.
Fixes#31946
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The arm64 timer node has not reg property and thus shouldn't be a
child of the SoC MMIO node. Move the arm,arm-timer up one level
to address this warning.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
i2c_shell uses "I2C_" label prefix to get the device. However, NPCX
uses controller-port architecture. Users should access the ports
instead of the controllers. Change I2C_CTRLX & I2CX_PORTX to I2CCTRL_X
& I2C_X_PORT_X to guarantee i2c_shell could get the correct device by
autocomplete.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Older LPC platforms use Flash IAP with a command style firmware command.
Tested on LPC54114 platform.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Reworks the NXP FlexSPI device tree bindings to configure controller and
device properties needed for an upcoming FlexSPI flash driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
gpt has internal divider, add dedicated attributes
nxp,gptfreq is added as required one
gpt can customize the gpt freq
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Timer 1 has two interrupts on STM32F0: TIM1_BRK_UP_TRG_COM_IRQn (13) and
TIM1_CC_IRQn (14). "brk" interrupt name does not reflect all the events
supported by the interrupt, so it has been renamed to "brk_up_trg_com".
On all other series except G0 timer 1 has a specific interrupt for each
event, so in such case "brk" is just fine.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
PSoC-6 SoC needs that user define the nvic interrupt number to bind
with the peripheral interrupt line for the Cortex-M0+ CPU. It uses
a multiplex before any NVIC interrupt line. The interrupt vector is
selected using interrupt-parent property with the intmux_chN number
reference.
Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt.
A tipical use is GPIO interrupt handle and user is responsable to
define interrupt line, priority and take care of enable same peripheral
instance on both CPUs only when appropriated.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
The psoc6.dtsi file declare a reference to nvic. Since it was proper
defined at psoc6_cm0/4.dtsi files this entry is redundant. Drop the
useless entry.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Enable slave support for I2C device instances. Slave mode is
interrupt based, wheras master mode is still based on polling.
Remove ENI bit in master configuration since it is not needed for
master mode.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Add the girq and girq-bit fields to the binding. This allows
encoding GIRQ related information inside device tree.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Add radio peripheral to nrf52833 DTS including antenna matrix
congiuration for Direction Finding extennsion.
Add appropriate binding file for nRF radio peripheral.
There is no default antenna matrix configuration. Antennas number
and GPIOS mapping to DFEGPIOS is project specific.
Complete configuration must be provided by end user as overaly.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This commit add support for i2c on imx6sx.
I2C support is based on imx7d and requires NXP HAL.
The Device Tree binding is also changed to better reflect that i2c
driver support both imx6sx and imx7d.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This property is required information for extracting PSEL bits relevant
to peripheral pinmux from this node.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
'reg' attribute removed from overall stm32l1 dts,
so eeprom size has to be specified for each SoC
in stm32l1x series.
Adds remaining stm32l1x SoCs that didn't have eeprom size specified yet.
Eeprom size added in stm32l151Xb-a & stm32l151X8-a dtsi files,
(based on device overview in datasheet DocID024330 Rev 5).
Eeprom size added in stm32l151Xb dtsi file (based on
device overview in datasheet DocID17659 Rev 12).
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add device tree description for qspi node on STM32L4 and
signals on whole family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
STM32L152xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, EEPROM size (8Kib) and amount of interrupts
(57, see STM32Cube). Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
after 7c699348a8
Convert drivers to new DT device macros
now the device name is aligned with label so we need
align them to default config
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
The npcx7m6fb dts defines i2c controller and ports, where the controller
is a property in the port node definition and the device nodes should be
defined as subnodes of the port.
This changes the binding definitions to reflect that, defining the port
as an i2c-controller so that in can inherit sub-nodes for i2c devices,
and the controller as a generic node.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add binding for the Nordic ECB (AES electronic codebook mode
encryption) peripheral and corresponding devicetree nodes for
nRF SoCs that feature this peripheral.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Since MDK was updated and now it contains the definition of QDEC
peripheral for nRF52805, the DT node representing this peripheral
can be processed normally.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
"st,mem2mem" property is supposed to be limited to dma-v1.
Remove its use in dma-v2 components.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
