Intial support of pinctrl driver for Renesas RX MCU
family.
This support base on using Renesas RX driver package in
hal_renesas layer
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
for high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
Initial support of clock control driver for RX MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
The qemu-system-rx is based on RX62N, this commit added
support for the RX62N SOC layer. MCU is using RXv1 core and
system timer running at 6MHz
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add initial support for Renesas RZ/G2LC (r9a07g044c22gbg), a 361-pin
package variant of RZ/G2L
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Due to a change in linker script cortex_a_r/scripts/linker.ld
, the _image_ram_start has been changed so the Zephyr image
cannot be copied from flash to ram as expected
and cannot run properly.
It is replaced by CONFIG_SRAM_BASE_ADDRESS, the _image_ram_size is also
replaced by _flash_used as a preventive measure.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Updated `CMakeLists.txt` and `Kconfig` to integrate power management
for RA8D1, RA8M1, and RA8T1.
Modified `Kconfig.defconfig` to configure ULPT timer as the system timer
when power management is enabled:
- Adjusted `SYS_CLOCK_HW_CYCLES_PER_SEC` and `SYS_CLOCK_TICKS_PER_SEC`
for ULPT timer.
- Disabled `CORTEX_M_SYSTICK` when ULPT timer is used as the system timer.
Implemented power management logic in the new `power.c` file for:
- RA8D1 (`soc/renesas/ra/ra8d1/power.c`)
- RA8M1 (`soc/renesas/ra/ra8m1/power.c`)
- RA8T1 (`soc/renesas/ra/ra8t1/power.c`)
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/T2M
Corrected space in the comment.
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Renesas takes over the maintainer of SoC Renesas RZ/T2M to unify with
other RZ devices
- Move soc/renesas/rzt2m to soc/renesas/rz
- Support xSPI boot mode to boot code from flash
- Change to use HAL Renesas
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Check if the option bits DT nodes are enabled before including them in
the linker script for all RA SoCs. These must be disabled for targets
that provide a separate bootloader.
This commit adds the DT_NODE_HAS_STATUS_OKAY gates to all RA-series SoC
linker scripts, converting existing ones to the new macro.
The changes in this commit have been mechanically generated using find
and awk tools.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
- Add new device tree source include file for DA14697 SoC
- Update Kconfig and soc.yml to support the new device
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
This is the initial commit to support pinctrl driver for Renesas RZ/A3UL
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Due to historical reasons, there were two implementations of
R7FA4M1AB3CFM. However, the migration has been completed,
so the old one is now being removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This is the initial commit to support PINCTRL driver for Renesas RZ/T2L
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/N2L
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Enabling Dcache on RA8D1 will cause many issue with data coherence
in driver.
This commit disable Dcache for RA8D1 as temporary solution, user
can enable it but should be aware of data coherence issue
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Add Flash HP support for ra6-cm4, ra6-cm33, ra4-cm33 (except
r7fa4w1ad2cng)
- Add config to set the minimal size of data which can be written
for RA4E2, RA4M2, RA4M3, RA6E1, RA6E2, RA6M1, RA6M2, RA6M3, RA6M4,
RA6M5
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for a new SoC Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Remove the renesas,ra-pinctrl driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
