driver: timer: Support for RX system timer
This commit add a system timer driver for Renesas RX using the CMT peripheral. The driver supports both system ticks and high-resolution cycle counting - Configures CMT0 as the system tick timer - Configures CMT1 as a free-running cycle timer for precise time tracking - Handles timer overflows to maintain a continuous cycle count. - Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64() for high-resolution timing - Supports Zephyr tickless kernel mode by tracking elapsed cycles - Enables interrupt-based tick announcement using CMT0 Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com> Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
This commit is contained in:
Duy Nguyen
Benjamin Cabé
parent
2f0715262d
commit
ad42e4d87d
9 changed files with 332 additions and 7 deletions
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@ -32,6 +32,7 @@ zephyr_library_sources_ifdef(CONFIG_NATIVE_SIM_TIMER native_sim_timer.c)
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zephyr_library_sources_ifdef(CONFIG_NPCX_ITIM_TIMER npcx_itim_timer.c)
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zephyr_library_sources_ifdef(CONFIG_NRF_GRTC_TIMER nrf_grtc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_NRF_RTC_TIMER nrf_rtc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RENESAS_RX_TIMER_CMT renesas_rx_cmt.c)
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zephyr_library_sources_ifdef(CONFIG_RCAR_CMT_TIMER rcar_cmt_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_ULPT_TIMER renesas_ra_ulpt_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RISCV_MACHINE_TIMER riscv_machine_timer.c)
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@ -90,6 +90,7 @@ source "drivers/timer/Kconfig.npcx_itim"
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source "drivers/timer/Kconfig.nrf_rtc"
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source "drivers/timer/Kconfig.nrf_grtc"
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source "drivers/timer/Kconfig.nrf_xrtc"
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source "drivers/timer/Kconfig.renesas_rx"
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source "drivers/timer/Kconfig.rcar_cmt"
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source "drivers/timer/Kconfig.riscv_machine"
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source "drivers/timer/Kconfig.rv32m1_lptmr"
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13
drivers/timer/Kconfig.renesas_rx
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13
drivers/timer/Kconfig.renesas_rx
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@ -0,0 +1,13 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config RENESAS_RX_TIMER_CMT
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bool "Renesas RX timer CMT"
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default y
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depends on DT_HAS_RENESAS_RX_TIMER_CMT_ENABLED
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the Renesas RX
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platform provides the standard "system clock driver" interfaces.
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If unchecked, no timer will be used.
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227
drivers/timer/renesas_rx_cmt.c
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227
drivers/timer/renesas_rx_cmt.c
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@ -0,0 +1,227 @@
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "zephyr/sys_clock.h"
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#include <zephyr/arch/cpu.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/irq.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/drivers/clock_control/renesas_rx_cgc.h>
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#define DT_DRV_COMPAT renesas_rx_timer_cmt
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#define CMT_NODE DT_NODELABEL(cmt)
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#define CMT0_NODE DT_NODELABEL(cmt0)
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#define CMT1_NODE DT_NODELABEL(cmt1)
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#define ICU_NODE DT_NODELABEL(icu)
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#define ICU_IR_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, IR)
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#define ICU_IER_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, IER)
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#define ICU_IPR_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, IPR)
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#define ICU_FIR_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, FIR)
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#define ICU_IR ((volatile uint8_t *)ICU_IR_ADDR)
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#define CMT0_IRQ_NUM DT_IRQ_BY_NAME(CMT0_NODE, cmi, irq)
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#define CMT1_IRQ_NUM DT_IRQ_BY_NAME(CMT1_NODE, cmi, irq)
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#define COUNTER_MAX 0x0000ffff
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#define CYCLES_PER_SEC (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)
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#define TICKS_PER_SEC (CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#define CYCLES_PER_TICK (CYCLES_PER_SEC / TICKS_PER_SEC)
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#define CYCLES_CYCLE_TIMER (COUNTER_MAX + 1)
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#define MSTPCR_ADDR ((volatile uint32_t *)0x00080010) /* MSTPCR register address */
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#define MSTP_CMT0_BIT (1 << 15) /* Bit 15 controls MSTPA15 (CMT0) */
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static const struct clock_control_rx_subsys_cfg cmt_clk_cfg = {
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.mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(0), 0, mstp),
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.stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(0), 0, stop_bit),
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};
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struct timer_rx_cfg {
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volatile uint16_t *cmstr;
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volatile uint16_t *cmcr;
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volatile uint16_t *cmcnt;
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volatile uint16_t *cmcor;
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};
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static const struct timer_rx_cfg tick_timer_cfg = {
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.cmstr = (uint16_t *)DT_REG_ADDR_BY_NAME(CMT_NODE, CMSTR0),
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.cmcr = (uint16_t *)DT_REG_ADDR_BY_NAME(CMT0_NODE, CMCR),
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.cmcnt = (uint16_t *)DT_REG_ADDR_BY_NAME(CMT0_NODE, CMCNT),
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.cmcor = (uint16_t *)DT_REG_ADDR_BY_NAME(CMT0_NODE, CMCOR)};
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static const struct timer_rx_cfg cycle_timer_cfg = {
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.cmstr = (uint16_t *)DT_REG_ADDR_BY_NAME(CMT_NODE, CMSTR0),
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.cmcr = (uint16_t *)DT_REG_ADDR_BY_NAME(CMT1_NODE, CMCR),
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.cmcnt = (uint16_t *)DT_REG_ADDR_BY_NAME(CMT1_NODE, CMCNT),
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.cmcor = (uint16_t *)DT_REG_ADDR_BY_NAME(CMT1_NODE, CMCOR)};
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#ifdef CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER
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typedef uint64_t cycle_t;
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#define CYCLE_COUNT_MAX (0xffffffffffffffff)
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#else
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typedef uint32_t cycle_t;
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#define CYCLE_COUNT_MAX (0xffffffff)
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#endif
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static cycle_t cycle_count;
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static uint16_t clock_cycles_per_tick;
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static volatile cycle_t announced_cycle_count;
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static struct k_spinlock lock;
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#if defined(CONFIG_TEST)
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const int32_t z_sys_timer_irq_for_test = CMT0_IRQ_NUM;
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#endif
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static cycle_t cmt1_elapsed(void)
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{
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uint32_t val1 = (uint32_t)(*cycle_timer_cfg.cmcnt);
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uint8_t cmt_ir = ICU_IR[29];
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uint32_t val2 = (uint32_t)(*cycle_timer_cfg.cmcnt);
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if ((1 == cmt_ir) || (val1 > val2)) {
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cycle_count += CYCLES_CYCLE_TIMER;
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ICU_IR[29] = 0;
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}
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return (val2 + cycle_count);
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t ret = (uint32_t)cmt1_elapsed();
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k_spin_unlock(&lock, key);
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return ret;
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}
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#ifdef CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER
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uint64_t sys_clock_cycle_get_64(void)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint64_t ret = (uint64_t)cmt1_elapsed();
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k_spin_unlock(&lock, key);
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return ret;
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}
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#endif /* CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER */
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uint32_t sys_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* Always return 0 for tickful operation */
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t ret;
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cycle_t current_cycle_count;
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current_cycle_count = cmt1_elapsed();
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if (current_cycle_count < announced_cycle_count) {
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/* cycle_count overflowed */
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ret = (uint32_t)((current_cycle_count +
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(CYCLE_COUNT_MAX - announced_cycle_count + 1)) /
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CYCLES_PER_TICK);
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} else {
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ret = (uint32_t)((current_cycle_count - announced_cycle_count) / CYCLES_PER_TICK);
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}
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k_spin_unlock(&lock, key);
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return ret;
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}
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static void cmt0_isr(void)
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{
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k_ticks_t dticks;
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cycle_t current_cycle_count;
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k_spinlock_key_t key = k_spin_lock(&lock);
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current_cycle_count = cmt1_elapsed();
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if (current_cycle_count < announced_cycle_count) {
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/* cycle_count overflowed */
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dticks = (k_ticks_t)((current_cycle_count +
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(CYCLE_COUNT_MAX - announced_cycle_count + 1)) /
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CYCLES_PER_TICK);
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} else {
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dticks = (k_ticks_t)((current_cycle_count - announced_cycle_count) /
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CYCLES_PER_TICK);
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}
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announced_cycle_count = (current_cycle_count / CYCLES_PER_TICK) * CYCLES_PER_TICK;
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k_spin_unlock(&lock, key);
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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sys_clock_announce(1);
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} else {
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sys_clock_announce(dticks);
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}
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}
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static int sys_clock_driver_init(void)
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{
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const struct device *clk = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(0)));
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int ret;
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if (!device_is_ready(clk)) {
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return -ENODEV;
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}
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ret = clock_control_on(clk, (clock_control_subsys_t)&cmt_clk_cfg);
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if (ret < 0) {
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return ret;
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}
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*tick_timer_cfg.cmcr = 0x00C0; /* enable CMT0 interrupt */
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*cycle_timer_cfg.cmcr = 0x00C0; /* enable CMT1 interrupt */
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clock_cycles_per_tick = (uint16_t)(CYCLES_PER_TICK);
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*tick_timer_cfg.cmcor = clock_cycles_per_tick - 1;
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*cycle_timer_cfg.cmcor = (uint16_t)COUNTER_MAX;
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IRQ_CONNECT(CMT0_IRQ_NUM, 0x01, cmt0_isr, NULL, 0);
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irq_enable(CMT0_IRQ_NUM);
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*tick_timer_cfg.cmstr = 0x0003; /* start cmt0,1 */
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return 0;
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && idle && ticks == K_TICKS_FOREVER) {
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*tick_timer_cfg.cmstr = 0x0000; /* stop cmt0,1 */
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return;
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}
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#if defined(CONFIG_TICKLESS_KERNEL)
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/*
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* By default, it is implemented as a no operation.
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* Implement the processing as needed.
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*/
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#endif /* CONFIG_TICKLESS_KERNEL */
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}
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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23
dts/bindings/timer/renesas,rx-timer-cmt-start-control.yaml
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23
dts/bindings/timer/renesas,rx-timer-cmt-start-control.yaml
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@ -0,0 +1,23 @@
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# Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RX timer node
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compatible: "renesas,rx-timer-cmt-start-control"
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include: base.yaml
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properties:
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reg:
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required: true
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clocks:
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required: true
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clock-frequency:
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type: int
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required: true
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description: |
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Clock frequency information for Timer operation
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This value need to be set at PCLKB/8
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13
dts/bindings/timer/renesas,rx-timer-cmt.yaml
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13
dts/bindings/timer/renesas,rx-timer-cmt.yaml
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@ -0,0 +1,13 @@
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# Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RX timer node
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compatible: "renesas,rx-timer-cmt"
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include: base.yaml
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properties:
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reg:
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required: true
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@ -71,13 +71,38 @@
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};
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};
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cmt0: timer@88004 {
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compatible = "renesas,rx-timer-cmt";
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reg = <0x00088004 0x02>,
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<0x00088000 0x02>,
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<0x00088002 0x02>,
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<0x00088006 0x02>;
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status = "disabled";
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cmt: timer@88000 {
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compatible = "renesas,rx-timer-cmt-start-control";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00088000 0x02>;
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clocks = <&pclkb MSTPA 15>;
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reg-names = "CMSTR0";
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status = "okay";
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cmt0: timer@88002 {
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compatible = "renesas,rx-timer-cmt";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00088002 0x02>,
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<0x00088004 0x02>,
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<0x00088006 0x02>;
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reg-names = "CMCR", "CMCNT", "CMCOR";
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interrupts = <28 1>;
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interrupt-names = "cmi";
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status = "okay";
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};
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cmt1: timer@88008 {
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compatible = "renesas,rx-timer-cmt";
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reg = <0x00088008 0x02>,
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<0x0008800A 0x02>,
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<0x0008800C 0x02>;
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reg-names = "CMCR", "CMCNT", "CMCOR";
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interrupts = <29 1>;
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interrupt-names = "cmi";
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status = "disabled";
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};
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};
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ofsm: ofsm@ffffff80 {
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@ -3,6 +3,17 @@
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if SOC_SERIES_RX130
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DT_CMT_PATH := $(dt_nodelabel_path,cmt)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_CMT_PATH),clock-frequency)
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# SYS_CLOCK_TICKS_PER_SEC is set to 100 if PCLKB is 48MHz or less.
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# (PCLKB = SYS_CLOCK_HW_CYCLES_PER_SEC * 8)
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config SYS_CLOCK_TICKS_PER_SEC
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default 100 if SYS_CLOCK_HW_CYCLES_PER_SEC <= 6000000
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default 1000
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config INITIALIZATION_STACK_SIZE
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default 512
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@ -3,6 +3,17 @@
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if SOC_SERIES_RX62N
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DT_CMT_PATH := $(dt_nodelabel_path,cmt)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_CMT_PATH),clock-frequency)
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# SYS_CLOCK_TICKS_PER_SEC is set to 100 if PCLKB is 48MHz or less.
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# (PCLKB = SYS_CLOCK_HW_CYCLES_PER_SEC * 8)
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config SYS_CLOCK_TICKS_PER_SEC
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default 100 if SYS_CLOCK_HW_CYCLES_PER_SEC <= 6000000
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default 10000
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config INITIALIZATION_STACK_SIZE
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default 512
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