soc: renesas: ra: Move configs from board deconfig into SoC deconfig

- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
This commit is contained in:
Quy Tran 2025-01-21 13:23:08 +07:00 committed by Benjamin Cabé
commit 292f7454d4
46 changed files with 180 additions and 82 deletions

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@ -1,8 +1,6 @@
# Copyright (c) 2024 TOKITA Hiroshi
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

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@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

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@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

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@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

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@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

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@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

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@ -1,14 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

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@ -1,14 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

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@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

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@ -1,14 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_BUILD_OUTPUT_HEX=y

View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

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@ -1,17 +1,11 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y

View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,7 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_BUILD_OUTPUT_HEX=y

View file

@ -141,6 +141,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <48000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

View file

@ -155,6 +155,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <100000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

View file

@ -215,6 +215,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <100000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

View file

@ -226,6 +226,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <100000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

View file

@ -117,6 +117,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <48000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

View file

@ -194,6 +194,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <200000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

View file

@ -153,6 +153,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <200000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

View file

@ -108,6 +108,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <120000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

View file

@ -140,6 +140,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <120000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

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@ -199,6 +199,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <120000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

View file

@ -302,6 +302,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <200000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

View file

@ -354,6 +354,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <200000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

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@ -155,6 +155,7 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <480000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

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@ -125,6 +125,7 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <480000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

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@ -122,6 +122,7 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <480000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

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@ -6,4 +6,15 @@ if SOC_SERIES_RA2A1
config NUM_IRQS
default 32
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA2A1

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@ -6,6 +6,17 @@ if SOC_SERIES_RA4E2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

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@ -6,6 +6,17 @@ if SOC_SERIES_RA4M2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

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@ -6,6 +6,17 @@ if SOC_SERIES_RA4M3
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

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@ -6,4 +6,15 @@ if SOC_SERIES_RA4W1
config NUM_IRQS
default 32
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA4W1

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@ -6,6 +6,17 @@ if SOC_SERIES_RA6E1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

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@ -6,6 +6,17 @@ if SOC_SERIES_RA6E2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

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@ -6,6 +6,17 @@ if SOC_SERIES_RA6M1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M3
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M4
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M5
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8D1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8M1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8T1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128