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soc: renesas: ra: Move configs from board deconfig into SoC deconfig

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- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
This commit is contained in:
Quy Tran 2025-01-21 13:23:08 +07:00 • committed by Benjamin Cabé
commit 292f7454d4
46 changed files with 180 additions and 82 deletions
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5
boards/renesas/ek_ra2a1/ek_ra2a1_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 TOKITA Hiroshi
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/ek_ra4e2/ek_ra4e2_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/ek_ra4m2/ek_ra4m2_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/ek_ra4m3/ek_ra4m3_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/ek_ra4w1/ek_ra4w1_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
View file

@ -1,14 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

5
boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
View file

@ -1,14 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

5
boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
View file

@ -1,14 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

5
boards/renesas/ek_ra8d1/ek_ra8d1_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_BUILD_OUTPUT_HEX=y

5
boards/renesas/ek_ra8m1/ek_ra8m1_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

6
boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
View file

@ -1,17 +1,11 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
# Enable Console
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y

5
boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,6 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CLOCK_CONTROL=y

6
boards/renesas/mck_ra8t1/mck_ra8t1_defconfig
View file

@ -1,8 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
# Enable GPIO
CONFIG_GPIO=y
@ -11,7 +9,3 @@ CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_BUILD_OUTPUT_HEX=y

1
dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
View file

@ -141,6 +141,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <48000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
View file

@ -155,6 +155,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <100000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
View file

@ -215,6 +215,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <100000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
View file

@ -226,6 +226,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <100000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
View file

@ -117,6 +117,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <48000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
View file

@ -194,6 +194,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <200000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
View file

@ -153,6 +153,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <200000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
View file

@ -108,6 +108,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <120000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
View file

@ -140,6 +140,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <120000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
View file

@ -199,6 +199,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <120000000>;
div = <2>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
View file

@ -302,6 +302,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <200000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
View file

@ -354,6 +354,7 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <200000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
View file

@ -155,6 +155,7 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <480000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
View file

@ -125,6 +125,7 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <480000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

1
dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
View file

@ -122,6 +122,7 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <480000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";

11
soc/renesas/ra/ra2a1/Kconfig.defconfig
View file

@ -6,4 +6,15 @@ if SOC_SERIES_RA2A1
config NUM_IRQS
default 32
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA2A1

11
soc/renesas/ra/ra4e2/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA4E2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra4m2/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA4M2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra4m3/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA4M3
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra4w1/Kconfig.defconfig
View file

@ -6,4 +6,15 @@ if SOC_SERIES_RA4W1
config NUM_IRQS
default 32
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA4W1

11
soc/renesas/ra/ra6e1/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6E1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra6e2/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6E2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra6m1/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra6m2/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra6m3/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M3
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra6m4/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M4
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra6m5/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M5
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra8d1/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8D1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra8m1/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8M1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

11
soc/renesas/ra/ra8t1/Kconfig.defconfig
View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8T1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128