soc: renesas: ra: Move configs from board deconfig into SoC deconfig
- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig into SoC deconfig - Add clock-frequency in dts to get config SYS_CLOCK_HW_CYCLES_PER_SEC from dts Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
This commit is contained in:
parent
ad04319673
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292f7454d4
46 changed files with 180 additions and 82 deletions
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@ -1,8 +1,6 @@
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# Copyright (c) 2024 TOKITA Hiroshi
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
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# Enable GPIO
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CONFIG_GPIO=y
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@ -11,6 +9,3 @@ CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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@ -1,8 +1,6 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
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# Enable GPIO
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CONFIG_GPIO=y
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@ -11,6 +9,3 @@ CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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@ -1,8 +1,6 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
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# Enable GPIO
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CONFIG_GPIO=y
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@ -11,6 +9,3 @@ CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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@ -1,8 +1,6 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
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# Enable GPIO
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CONFIG_GPIO=y
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@ -11,6 +9,3 @@ CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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@ -1,8 +1,6 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
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# Enable GPIO
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CONFIG_GPIO=y
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@ -11,6 +9,3 @@ CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
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# Enable GPIO
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CONFIG_GPIO=y
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@ -11,6 +9,3 @@ CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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@ -1,14 +1,9 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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# Enable Console
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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# Enable Console
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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@ -1,8 +1,6 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
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# Enable GPIO
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CONFIG_GPIO=y
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@ -11,6 +9,3 @@ CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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@ -1,8 +1,6 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
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# Enable GPIO
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CONFIG_GPIO=y
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@ -11,6 +9,3 @@ CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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@ -1,14 +1,9 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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# Enable Console
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_BUILD_OUTPUT_HEX=y
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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@ -1,17 +1,11 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_BUILD_OUTPUT_HEX=y
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# Enable Console
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_CLOCK_CONTROL=y
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_CLOCK_CONTROL=y
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_BUILD_OUTPUT_HEX=y
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@ -141,6 +141,7 @@
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <48000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <100000000>;
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <100000000>;
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <100000000>;
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <48000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <200000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <200000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <120000000>;
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <120000000>;
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <120000000>;
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <200000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <200000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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cpuclk: cpuclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <480000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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cpuclk: cpuclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <480000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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cpuclk: cpuclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <480000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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config NUM_IRQS
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default 32
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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endif # SOC_SERIES_RA2A1
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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# Set to the minimal size of data which can be written.
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config FLASH_FILL_BUFFER_SIZE
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default 128
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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# Set to the minimal size of data which can be written.
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config FLASH_FILL_BUFFER_SIZE
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default 128
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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# Set to the minimal size of data which can be written.
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config FLASH_FILL_BUFFER_SIZE
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default 128
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config NUM_IRQS
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default 32
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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endif # SOC_SERIES_RA4W1
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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# Set to the minimal size of data which can be written.
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config FLASH_FILL_BUFFER_SIZE
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default 128
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
|
@ -6,6 +6,17 @@ if SOC_SERIES_RA6M1
|
|||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
|
@ -6,6 +6,17 @@ if SOC_SERIES_RA6M2
|
|||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
|
@ -6,6 +6,17 @@ if SOC_SERIES_RA6M3
|
|||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
|
@ -6,6 +6,17 @@ if SOC_SERIES_RA6M4
|
|||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
|
@ -6,6 +6,17 @@ if SOC_SERIES_RA6M5
|
|||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
|
@ -6,6 +6,17 @@ if SOC_SERIES_RA8D1
|
|||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
|
@ -6,6 +6,17 @@ if SOC_SERIES_RA8M1
|
|||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
|
@ -6,6 +6,17 @@ if SOC_SERIES_RA8T1
|
|||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
# Set to the minimal size of data which can be written.
|
||||
config FLASH_FILL_BUFFER_SIZE
|
||||
default 128
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue