soc: renesas: ra: Add minimal support for ra4l1

Add minimal support for RA4L1 SoC and devicetree

Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
This commit is contained in:
Thao Luong 2025-01-12 23:35:48 +07:00 committed by Benjamin Cabé
commit 0b97890163
10 changed files with 1005 additions and 0 deletions

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/renesas/ra/ra4/r7fa4l1bx.dtsi>
/ {
soc {
flash-controller@407e0000 {
reg = <0x407e0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "renesas,ra-nv-flash";
reg = <0x0 DT_SIZE_K(512)>;
write-block-size = <8>;
erase-block-size = <2048>;
renesas,programming-enable;
};
flash1: flash@8000000 {
compatible = "renesas,ra-nv-flash";
reg = <0x8000000 DT_SIZE_K(8)>;
write-block-size = <1>;
erase-block-size = <256>;
renesas,programming-enable;
};
};
};
};

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>
#include <zephyr/dt-bindings/pwm/ra_pwm.h>
#include <freq.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";
reg = <0xe000ed90 0x40>;
};
};
};
soc {
interrupt-parent = <&nvic>;
system: system@4001e000 {
compatible = "renesas,ra-system";
reg = <0x4001e000 0x1000>;
status = "okay";
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(64)>;
};
ioport0: gpio@4001f000 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f000 0x20>;
port = <0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport1: gpio@4001f020 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f020 0x20>;
port = <1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport2: gpio@4001f040 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f040 0x20>;
port = <2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport3: gpio@4001f060 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f060 0x20>;
port = <3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport4: gpio@4001f080 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f080 0x20>;
port = <4>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport5: gpio@4001f0a0 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f0a0 0x20>;
port = <5>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport6: gpio@4001f0c0 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f0c0 0x20>;
port = <6>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport7: gpio@4001f0e0 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f0e0 0x20>;
port = <7>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport8: gpio@4001f100 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x4001f100 0x20>;
port = <8>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
pinctrl: pin-controller@4001F800 {
compatible = "renesas,ra-pinctrl-pfs";
reg = <0x4001F800 0x3c0>;
status = "okay";
};
sci0: sci@40118000 {
compatible = "renesas,ra-sci";
reg = <0x40118000 0x100>;
clocks = <&pclka MSTPB 31>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <0>;
status = "disabled";
};
};
sci1: sci@40118100 {
compatible = "renesas,ra-sci";
reg = <0x40118100 0x100>;
clocks = <&pclka MSTPB 30>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <1>;
status = "disabled";
};
};
sci3: sci@40118300 {
compatible = "renesas,ra-sci";
reg = <0x40118300 0x100>;
clocks = <&pclka MSTPB 38>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <3>;
status = "disabled";
};
};
sci4: sci@40118400 {
compatible = "renesas,ra-sci";
reg = <0x40118400 0x100>;
clocks = <&pclka MSTPB 27>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <4>;
status = "disabled";
};
};
sci5: sci@40118500 {
compatible = "renesas,ra-sci";
interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40118500 0x100>;
clocks = <&pclka MSTPB 26>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <5>;
status = "disabled";
};
};
sci9: sci@40118900 {
compatible = "renesas,ra-sci";
interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40118900 0x100>;
clocks = <&pclka MSTPB 22>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <9>;
status = "disabled";
};
};
spi0: spi@4011a000 {
compatible = "renesas,ra-spi";
#address-cells = <1>;
#size-cells = <0>;
channel = <0>;
interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x4011a000 0x100>;
status = "disabled";
};
adc0: adc@40170000 {
compatible = "renesas,ra-adc";
interrupts = <38 1>;
interrupt-names = "scanend";
reg = <0x40170000 0x100>;
#io-channel-cells = <1>;
vref-mv = <3300>;
channel-count = <16>;
channel-available-mask = <0x3fe007f>;
status = "disabled";
};
iic0: iic0@4009f000 {
compatible = "renesas,ra-iic";
channel = <0>;
reg = <0x4009f000 0x100>;
status = "disabled";
};
pwm0: pwm0@40169000 {
compatible = "renesas,ra-pwm";
divider = <RA_PWM_SOURCE_DIV_1>;
channel = <RA_PWM_CHANNEL_0>;
clocks = <&pclkd MSTPE 31>;
reg = <0x40169000 0x100>;
#pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm1@40169100 {
compatible = "renesas,ra-pwm";
divider = <RA_PWM_SOURCE_DIV_1>;
channel = <RA_PWM_CHANNEL_1>;
clocks = <&pclkd MSTPE 30>;
reg = <0x40169100 0x100>;
#pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm2@40169200 {
compatible = "renesas,ra-pwm";
divider = <RA_PWM_SOURCE_DIV_1>;
channel = <RA_PWM_CHANNEL_2>;
clocks = <&pclkd MSTPE 29>;
reg = <0x40169200 0x100>;
#pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm3@40169300 {
compatible = "renesas,ra-pwm";
divider = <RA_PWM_SOURCE_DIV_1>;
channel = <RA_PWM_CHANNEL_3>;
clocks = <&pclkd MSTPE 28>;
reg = <0x40169300 0x100>;
#pwm-cells = <3>;
status = "disabled";
};
pwm4: pwm4@40169400 {
compatible = "renesas,ra-pwm";
divider = <RA_PWM_SOURCE_DIV_1>;
channel = <RA_PWM_CHANNEL_4>;
clocks = <&pclkd MSTPE 27>;
reg = <0x40169400 0x100>;
#pwm-cells = <3>;
status = "disabled";
};
pwm5: pwm5@40169500 {
compatible = "renesas,ra-pwm";
divider = <RA_PWM_SOURCE_DIV_1>;
channel = <RA_PWM_CHANNEL_5>;
clocks = <&pclkd MSTPE 26>;
reg = <0x40169500 0x100>;
#pwm-cells = <3>;
status = "disabled";
};
canfd_global: canfd_global@400b0000 {
compatible = "renesas,ra-canfd-global";
interrupts = <40 1>, <41 1>;
interrupt-names = "rxf", "glerr";
clocks = <&pclkb 0 0>, <&pclka 0 0>;
clock-names = "opclk", "ramclk";
reg = <0x400b0000 0x2000>;
status = "disabled";
canfd0: canfd0 {
compatible = "renesas,ra-canfd";
channel = <0>;
interrupts = <43 12>, <44 12>, <45 12>;
interrupt-names = "err", "tx", "rx";
clocks = <&canfdclk MSTPC 27>;
clock-names = "dllclk";
status = "disabled";
};
};
option_setting_ofs: option_setting_ofs@100a100 {
compatible = "zephyr,memory-region";
reg = <0x0100a100 0x18>;
zephyr,memory-region = "OPTION_SETTING_OFS";
status = "okay";
};
option_setting_sas: option_setting_sas@100a134 {
compatible = "zephyr,memory-region";
reg = <0x0100a134 0xcc>;
zephyr,memory-region = "OPTION_SETTING_SAS";
status = "okay";
};
option_setting_s: option_setting_s@100a200 {
compatible = "zephyr,memory-region";
reg = <0x0100a200 0x100>;
zephyr,memory-region = "OPTION_SETTING_S";
status = "okay";
};
port_irq0: external-interrupt@40006000 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006000 0x1>;
channel = <0>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq1: external-interrupt@40006001 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006001 0x1>;
channel = <1>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq2: external-interrupt@40006002 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006002 0x1>;
channel = <2>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq3: external-interrupt@40006003 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006003 0x1>;
channel = <3>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq4: external-interrupt@40006004 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006004 0x1>;
channel = <4>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq5: external-interrupt@40006005 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006005 0x1>;
channel = <5>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq6: external-interrupt@40006006 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006006 0x1>;
channel = <6>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq7: external-interrupt@40006007 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006007 0x1>;
channel = <7>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq8: external-interrupt@40006008 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006008 0x1>;
channel = <8>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq9: external-interrupt@40006009 {
compatible = "renesas,ra-external-interrupt";
reg = <0x40006009 0x1>;
channel = <9>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq10: external-interrupt@4000600a {
compatible = "renesas,ra-external-interrupt";
reg = <0x4000600a 0x1>;
channel = <10>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq11: external-interrupt@4000600b {
compatible = "renesas,ra-external-interrupt";
reg = <0x4000600b 0x1>;
channel = <11>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq12: external-interrupt@4000600c {
compatible = "renesas,ra-external-interrupt";
reg = <0x4000600c 0x1>;
channel = <12>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq13: external-interrupt@4000600d {
compatible = "renesas,ra-external-interrupt";
reg = <0x4000600d 0x1>;
channel = <13>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq14: external-interrupt@4000600e {
compatible = "renesas,ra-external-interrupt";
reg = <0x4000600e 0x1>;
channel = <14>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
port_irq15: external-interrupt@4000600f {
compatible = "renesas,ra-external-interrupt";
reg = <0x4000600f 0x1>;
channel = <15>;
renesas,sample-clock-div = <64>;
#port-irq-cells = <0>;
status = "disabled";
};
};
clocks: clocks {
#address-cells = <1>;
#size-cells = <1>;
xtal: clock-main-osc {
compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(8)>;
#clock-cells = <0>;
status = "disabled";
};
hoco: clock-hoco {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(48)>;
#clock-cells = <0>;
};
loco: clock-loco {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
moco: clock-moco {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(8)>;
#clock-cells = <0>;
};
subclk: clock-subclk {
compatible = "renesas,ra-cgc-subclk";
clock-frequency = <32768>;
#clock-cells = <0>;
status = "disabled";
};
pll: pll {
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL */
clocks = <&xtal>;
div = <1>;
mul = <10 0>;
status = "disabled";
};
pclkblock: pclkblock@40084000 {
compatible = "renesas,ra-cgc-pclk-block";
reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
<0x4008400c 4>, <0x40084010 4>;
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
clocks = <&pll>;
status = "okay";
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <80000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
div = <1>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
div = <2>;
#clock-cells = <2>;
status = "okay";
};
clkout: clkout {
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
uclk: uclk {
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
canfdclk: canfdclk {
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
i3cclk: i3cclk {
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
uarta0: uarta0 {
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
uarta1: uarta1 {
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
&ioport0 {
port-irqs = <&port_irq6 &port_irq7 &port_irq8
&port_irq9 &port_irq10 &port_irq11>;
port-irq-names = "port-irq6",
"port-irq7",
"port-irq8",
"port-irq9",
"port-irq10",
"port-irq11";
port-irq6-pins = <0>;
port-irq7-pins = <1>;
port-irq8-pins = <2>;
port-irq9-pins = <4>;
port-irq10-pins = <10>;
port-irq11-pins = <11>;
};
&ioport1 {
port-irqs = <&port_irq0 &port_irq1 &port_irq2
&port_irq3 &port_irq4>;
port-irq-names = "port-irq0",
"port-irq1",
"port-irq2",
"port-irq3",
"port-irq4";
port-irq0-pins = <5>;
port-irq1-pins = <1 4>;
port-irq2-pins = <0>;
port-irq3-pins = <10>;
port-irq4-pins = <11>;
};
&ioport2 {
port-irqs = <&port_irq0 &port_irq1 &port_irq2
&port_irq3 &port_irq12>;
port-irq-names = "port-irq0",
"port-irq1",
"port-irq2",
"port-irq3",
"port-irq12";
port-irq0-pins = <6>;
port-irq1-pins = <5>;
port-irq2-pins = <13>;
port-irq3-pins = <12>;
port-irq12-pins = <8>;
};
&ioport3 {
port-irqs = <&port_irq5 &port_irq6
&port_irq8 &port_irq9>;
port-irq-names = "port-irq5",
"port-irq6",
"port-irq8",
"port-irq9";
port-irq5-pins = <2>;
port-irq6-pins = <1>;
port-irq8-pins = <5>;
port-irq9-pins = <4>;
};
&ioport4 {
port-irqs = <&port_irq0 &port_irq4 &port_irq5
&port_irq6 &port_irq7 &port_irq8
&port_irq9 &port_irq14 &port_irq15>;
port-irq-names = "port-irq0",
"port-irq4",
"port-irq5",
"port-irq6",
"port-irq7",
"port-irq8",
"port-irq9",
"port-irq14",
"port-irq15";
port-irq0-pins = <0>;
port-irq4-pins = <2 11>;
port-irq5-pins = <1 10>;
port-irq6-pins = <9>;
port-irq7-pins = <8>;
port-irq8-pins = <15>;
port-irq9-pins = <14>;
port-irq14-pins = <3>;
port-irq15-pins = <4>;
};
&ioport5 {
port-irqs = <&port_irq11 &port_irq12 &port_irq13
&port_irq14>;
port-irq-names = "port-irq11",
"port-irq12",
"port-irq13",
"port-irq14";
port-irq11-pins = <1>;
port-irq12-pins = <2>;
port-irq13-pins = <6>;
port-irq14-pins = <5>;
};
&ioport7 {
port-irqs = <&port_irq11>;
port-irq-names = "port-irq11";
port-irq11-pins = <8>;
};

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
)
zephyr_linker_sources(SECTIONS sections.ld)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RA4L1
select ARM
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select FPU
select ARMV8_M_DSP
select HAS_SWO
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select XIP
select SOC_EARLY_INIT_HOOK

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_RA4L1
config NUM_IRQS
default 64
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA4L1

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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RA4L1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA4L1 series
config SOC_R7FA4L1BD4CFP
bool
select SOC_SERIES_RA4L1
help
R7FA4L1BD4CFP
config SOC_SERIES
default "ra4l1" if SOC_SERIES_RA4L1
config SOC
default "r7fa4l1bd4cfp" if SOC_R7FA4L1BD4CFP

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/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
*(.fsp_dtc_vector_table)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
SECTION_PROLOGUE(.option_setting_ofs,,)
{
__OPTION_SETTING_OFS_Start = .;
KEEP(*(.option_setting_ofs0))
. = __OPTION_SETTING_OFS_Start + 0x04;
KEEP(*(.option_setting_ofs2))
. = __OPTION_SETTING_OFS_Start + 0x10;
KEEP(*(.option_setting_dualsel))
__OPTION_SETTING_OFS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
SECTION_PROLOGUE(.option_setting_sas,,)
{
__OPTION_SETTING_SAS_Start = .;
KEEP(*(.option_setting_sas))
__OPTION_SETTING_SAS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
SECTION_PROLOGUE(.option_setting_s,,)
{
__OPTION_SETTING_S_Start = .;
KEEP(*(.option_setting_ofs1_sec))
. = __OPTION_SETTING_S_Start + 0x04;
KEEP(*(.option_setting_ofs3_sec))
. = __OPTION_SETTING_S_Start + 0x10;
KEEP(*(.option_setting_banksel_sec))
. = __OPTION_SETTING_S_Start + 0x40;
KEEP(*(.option_setting_bps_sec0))
. = __OPTION_SETTING_S_Start + 0x44;
KEEP(*(.option_setting_bps_sec1))
. = __OPTION_SETTING_S_Start + 0x48;
KEEP(*(.option_setting_bps_sec2))
. = __OPTION_SETTING_S_Start + 0x4C;
KEEP(*(.option_setting_bps_sec3))
. = __OPTION_SETTING_S_Start + 0x60;
KEEP(*(.option_setting_pbps_sec0))
. = __OPTION_SETTING_S_Start + 0x64;
KEEP(*(.option_setting_pbps_sec1))
. = __OPTION_SETTING_S_Start + 0x68;
KEEP(*(.option_setting_pbps_sec2))
. = __OPTION_SETTING_S_Start + 0x6C;
KEEP(*(.option_setting_pbps_sec3))
. = __OPTION_SETTING_S_Start + 0x80;
KEEP(*(.option_setting_ofs1_sel))
. = __OPTION_SETTING_S_Start + 0x84;
KEEP(*(.option_setting_ofs3_sel))
. = __OPTION_SETTING_S_Start + 0x90;
KEEP(*(.option_setting_banksel_sel))
. = __OPTION_SETTING_S_Start + 0xC0;
KEEP(*(.option_setting_bps_sel0))
. = __OPTION_SETTING_S_Start + 0xC4;
KEEP(*(.option_setting_bps_sel1))
. = __OPTION_SETTING_S_Start + 0xC8;
KEEP(*(.option_setting_bps_sel2))
. = __OPTION_SETTING_S_Start + 0xCC;
KEEP(*(.option_setting_bps_sel3))
__OPTION_SETTING_S_End = .;
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
#endif

View file

@ -0,0 +1,62 @@
/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Renesas RA4L1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#include "bsp_cfg.h"
#include "bsp_api.h"
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
*/
void soc_early_init_hook(void)
{
extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++) {
g_protect_counters[i] = 0;
}
#if FSP_PRIV_TZ_USE_SECURE_REGS
/* Disable protection using PRCR register. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
/* Initialize peripherals to secure mode for flat projects */
R_PSCU->PSARB = 0;
R_PSCU->PSARC = 0;
R_PSCU->PSARD = 0;
R_PSCU->PSARE = 0;
R_CPSCU->ICUSARG = 0;
R_CPSCU->ICUSARH = 0;
R_CPSCU->ICUSARI = 0;
/* Enable protection using PRCR register. */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
}

View file

@ -0,0 +1,16 @@
/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the Renesas RA4L1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA4L1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA4L1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA4L1_SOC_H_ */

View file

@ -11,6 +11,9 @@ family:
- name: ra4e2
socs:
- name: r7fa4e2b93cfm
- name: ra4l1
socs:
- name: r7fa4l1bd4cfp
- name: ra4m1
socs:
- name: r7fa4m1ab3cfm