soc: renesas: ra8d1: Enable I cache and D cache
Enabling I cache and D cache in RA8D1 init hook to improve code execution performance Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
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2 changed files with 27 additions and 0 deletions
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@ -10,4 +10,7 @@ config NUM_IRQS
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config FLASH_FILL_BUFFER_SIZE
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default 128
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config CACHE_MANAGEMENT
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default y
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endif # SOC_SERIES_RA8D1
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@ -17,10 +17,14 @@
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#include <zephyr/arch/arm/nmi.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/barrier.h>
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#include <zephyr/cache.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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#include <bsp_api.h>
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#define CCR_CACHE_ENABLE (SCB_CCR_IC_Msk | SCB_CCR_BP_Msk | SCB_CCR_LOB_Msk)
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uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
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volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
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@ -34,4 +38,24 @@ void soc_early_init_hook(void)
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{
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SystemCoreClock = BSP_MOCO_HZ;
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g_protect_pfswe_counter = 0;
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SCB->CCR = (uint32_t)CCR_CACHE_ENABLE;
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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/* Apply Arm Cortex-M85 errata workarounds for D-Cache
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* Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register.
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* Set bit 16 in ACTLR to 1.
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* See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641
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* Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0,
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* Document ID: SDEN-2236668).
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*/
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MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk;
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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ICB->ACTLR |= (1U << 16U);
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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sys_cache_data_enable();
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}
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