drivers: pinctrl: Add support for RZ/T2M

This is the initial commit to support pinctrl driver for Renesas RZ/T2M
Corrected space in the comment.

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This commit is contained in:
Hieu Nguyen 2025-02-06 05:49:21 +00:00 committed by Benjamin Cabé
commit 303376a76b
8 changed files with 48 additions and 5 deletions

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@ -0,0 +1,23 @@
/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzt-common.h>
&pinctrl {
/omit-if-no-ref/ sci0_default: sci0_default {
sci0-pinmux {
pinmux = <RZT_PINMUX(PORT_16, 5, 1)>, /* TXD */
<RZT_PINMUX(PORT_16, 6, 2)>; /* RXD */
};
};
/omit-if-no-ref/ irq2_default: irq2_default{
irq2-pinmux{
pinmux = <RZT_PINMUX(PORT_10, 5, 0)>;
input-enable;
};
};
};

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@ -94,5 +94,10 @@
};
};
};
pinctrl: pinctrl@800a0000 {
compatible = "renesas,rzt-pinctrl";
reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
};
};
};

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@ -2,7 +2,9 @@
# SPDX-License-Identifier: Apache-2.0
description: |
The Renesas RZ/T2L pin controller is a node responsible for controlling
Renesas RZ/T pin controller
The Renesas RZ/T pin controller is a node responsible for controlling
pin function selection and pin properties, such as routing the TX and RX of UART0
to pin 5 and pin 6 of port 16.

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@ -101,4 +101,4 @@
#define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_*/
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_ */

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@ -42,4 +42,4 @@
*/
#define RZT_PINMUX(port, pin, func) (port | pin | (func << 4))
#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZT_COMMON_H_*/
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZT_COMMON_H_ */

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@ -101,4 +101,4 @@ typedef struct pinctrl_soc_pin_t {
#ifdef __cplusplus
}
#endif
#endif /*ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_*/
#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_ */

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@ -65,4 +65,4 @@ typedef struct pinctrl_soc_pin_t {
}
#endif
#endif /*ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZT_H_*/
#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZT_H_ */

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@ -0,0 +1,13 @@
/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_RENESAS_RZ_RZT2M_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RENESAS_RZ_RZT2M_PINCTRL_SOC_H_
#include <pinctrl_rzt.h>
#endif /* ZEPHYR_SOC_RENESAS_RZ_RZT2M_PINCTRL_SOC_H_ */