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drivers: pinctrl: Add support for RZ/G3S

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This is the initial commit to support pinctrl driver for Renesas RZ/G3S

Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit is contained in:
Nhut Nguyen 2024-11-04 09:42:23 +00:00 • committed by Benjamin Cabé
commit 25ed9c9d99
11 changed files with 406 additions and 0 deletions
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38
boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi Normal file
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@ -0,0 +1,38 @@
/*
* Copyright (c) 2024 EPAM Systems
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>
&pinctrl {
/omit-if-no-ref/ scif0_pins: scif0 {
scif0-pinmux {
pinmux = <RZG_PINMUX(PORT_06, 3, 1)>, /* TXD */
<RZG_PINMUX(PORT_06, 4, 1)>; /* RXD */
};
};
/omit-if-no-ref/ scif1_pins: scif1 {
scif1-pinmux {
pinmux = <RZG_PINMUX(PORT_14, 0, 1)>, /* TXD */
<RZG_PINMUX(PORT_14, 1, 1)>; /* RXD */
};
};
/omit-if-no-ref/ scif3_pins: scif3 {
scif3-pinmux {
pinmux = <RZG_PINMUX(PORT_17, 3, 7)>, /* TXD */
<RZG_PINMUX(PORT_17, 2, 7)>; /* RXD */
};
};
/omit-if-no-ref/ scif5_pins: scif5 {
scif5-pinmux {
pinmux = <RZG_PINMUX(PORT_15, 1, 6)>, /* RXD */
<RZG_PINMUX(PORT_15, 2, 6)>; /* TXD */
};
};
};

1
drivers/pinctrl/renesas/CMakeLists.txt
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@ -5,5 +5,6 @@
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZ rz/pinctrl_renesas_rz.c)
add_subdirectory_ifdef(CONFIG_PINCTRL_RCAR_PFC rcar)

9
drivers/pinctrl/renesas/rz/Kconfig
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@ -1,4 +1,5 @@
# Copyright (c) 2023 Antmicro <www.antmicro.com>
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config PINCTRL_RZT2M
@ -7,3 +8,11 @@ config PINCTRL_RZT2M
depends on DT_HAS_RENESAS_RZT2M_PINCTRL_ENABLED
help
Renesas RZ/T2M pinctrl driver
config PINCTRL_RENESAS_RZ
bool "Renesas RZ pin controller driver"
default y
depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED
select USE_RZ_FSP_IOPORT
help
Enable Renesas RZ pinctrl driver.

25
drivers/pinctrl/renesas/rz/pinctrl_renesas_rz.c Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include "r_ioport.h"
static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
uint32_t cfg = *(uint32_t *)&pin->config;
R_IOPORT_PinCfg(NULL, pin->port_pin, cfg);
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(pins++);
}
return 0;
}

8
dts/arm/renesas/rz/rzg/r9a08g045.dtsi
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@ -30,6 +30,14 @@
};
};
};
soc {
pinctrl: pin-controller@41030000 {
compatible = "renesas,rzg-pinctrl";
reg = <0x41030000 DT_SIZE_K(64)>;
reg-names = "pinctrl";
};
};
};
&nvic {

95
dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml Normal file
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@ -0,0 +1,95 @@
# Copyright (c) 2024 Epam Systems
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: |
Below generic example shows of supported pinctrl definitions:
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl_rzg3s.h>
example_pins: device_pin {
device-pinmux {
pinmux = <RZG_PINMUX(PORT_08, 1, 5)>,
<RZG_PINMUX(PORT_08, 2, 5)>;
bias_pull_up;
renesas,filter = RZG_FILTER_SET(RZG_FILNUM_8_STAGE,RZG_FILCLKSEL_DIV_18000);
drive-strength = <1>;
};
device-spins {
pins = <BSP_IO_XSPI_IO0>, <BSP_IO_XSPI_IO4>;
input-enable;
renesas,filter = RZG_FILTER_SET(RZG_FILNUM_8_STAGE,RZG_FILCLKSEL_DIV_18000);
drive-strength = <2>;
};
};
compatible: renesas,rzg-pinctrl
include: base.yaml
properties:
reg:
required: true
reg-names:
required: true
child-binding:
description: |
This RZG pins mux/cfg nodes description.
child-binding:
description: |
The RZG pinmux/pincfg configuration nodes description.
include:
- name: pincfg-node.yaml
property-allowlist:
- bias-disable
- bias-high-impedance
- bias-pull-down
- bias-pull-up
- bias-pull-pin-default
- drive-strength
- input-enable
- input-disable
- output-enable
- power-source
- low-power-enable
- low-power-disable
properties:
pinmux:
type: array
description: |
Pinmux configuration node.
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZG_PINMUX()
helper macro in pinctrl_rzg.h
pins:
type: array
description: |
Special Purpose pins configuration node.
Values are define in pinctrl_rzg.h.
Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,...
drive-strength:
type: int
default: 0
description: |
Maximum sink or source current in mA for pin which shell be selected
depending on device and pin group.
renesas,filter:
type: int
default: 0
description: |
Digital Noise Filter configuration for a pin which shell be defined
using RZG_FILTER_SET() helper macro in pinctrl_rzg.h to specify
FILNUM_m and FILCLKSEL_m. With 24Mhz external clock:
- min debounce time will be 166.666ns for FILNUM_m=0 and FILCLKSEL_m=0
- max debounce time will be 24ms for FILNUM_m=3 and FILCLKSEL_m=3.
This property intentionally redefined to avoid unnecessary conversation from usec to
FILNUM_m and FILCLKSEL_m values depending on external clock value as this configuration
is static.

104
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h Normal file
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@ -0,0 +1,104 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_
/* Superset list of all possible IO ports. */
#define PORT_00 0x0000 /* IO port 0 */
#define PORT_01 0x1000 /* IO port 1 */
#define PORT_02 0x1100 /* IO port 2 */
#define PORT_03 0x1200 /* IO port 3 */
#define PORT_04 0x1300 /* IO port 4 */
#define PORT_05 0x0100 /* IO port 5 */
#define PORT_06 0x0200 /* IO port 6 */
#define PORT_07 0x1400 /* IO port 7 */
#define PORT_08 0x1500 /* IO port 8 */
#define PORT_09 0x1600 /* IO port 9 */
#define PORT_10 0x1700 /* IO port 10 */
#define PORT_11 0x0300 /* IO port 11 */
#define PORT_12 0x0400 /* IO port 12 */
#define PORT_13 0x0500 /* IO port 13 */
#define PORT_14 0x0600 /* IO port 14 */
#define PORT_15 0x0700 /* IO port 15 */
#define PORT_16 0x0800 /* IO port 16 */
#define PORT_17 0x0900 /* IO port 17 */
#define PORT_18 0x0A00 /* IO port 18 */
/*
* Create the value contain port/pin/function information
*
* port: port number BSP_IO_PORT_00..BSP_IO_PORT_18
* pin: pin number
* func: pin function
*/
#define RZG_PINMUX(port, pin, func) (port | pin | (func << 4))
/* Special purpose port */
#define BSP_IO_NMI 0xFFFF0000 /* NMI */
#define BSP_IO_TMS_SWDIO 0xFFFF0100 /* TMS_SWDIO */
#define BSP_IO_TDO 0xFFFF0101 /* TDO */
#define BSP_IO_AUDIO_CLK1 0xFFFF0200 /* AUDIO_CLK1 */
#define BSP_IO_AUDIO_CLK2 0xFFFF0201 /* AUDIO_CLK2 */
#define BSP_IO_XSPI_SPCLK 0xFFFF0400 /* XSPI_SPCLK */
#define BSP_IO_XSPI_RESET_N 0xFFFF0401 /* XSPI_RESET_N */
#define BSP_IO_XSPI_WP_N 0xFFFF0402 /* XSPI_WP_N */
#define BSP_IO_XSPI_DS 0xFFFF0403 /* XSPI_DS */
#define BSP_IO_XSPI_CS0_N 0xFFFF0404 /* XSPI_CS0_N */
#define BSP_IO_XSPI_CS1_N 0xFFFF0405 /* XSPI_CS1_N */
#define BSP_IO_XSPI_IO0 0xFFFF0500 /* XSPI_IO0 */
#define BSP_IO_XSPI_IO1 0xFFFF0501 /* XSPI_IO1 */
#define BSP_IO_XSPI_IO2 0xFFFF0502 /* XSPI_IO2 */
#define BSP_IO_XSPI_IO3 0xFFFF0503 /* XSPI_IO3 */
#define BSP_IO_XSPI_IO4 0xFFFF0504 /* XSPI_IO4 */
#define BSP_IO_XSPI_IO5 0xFFFF0505 /* XSPI_IO5 */
#define BSP_IO_XSPI_IO6 0xFFFF0506 /* XSPI_IO6 */
#define BSP_IO_XSPI_IO7 0xFFFF0507 /* XSPI_IO7 */
#define BSP_IO_WDTOVF_PERROUT 0xFFFF0600 /* WDTOVF_PERROUT */
#define BSP_IO_I3C_SDA 0xFFFF0900 /* I3C_SDA */
#define BSP_IO_I3C_SCL 0xFFFF0901 /* I3C_SCL */
#define BSP_IO_SD0_CLK 0xFFFF1000 /* CD0_CLK */
#define BSP_IO_SD0_CMD 0xFFFF1001 /* CD0_CMD */
#define BSP_IO_SD0_RST_N 0xFFFF1002 /* CD0_RST_N */
#define BSP_IO_SD0_DATA0 0xFFFF1100 /* SD0_DATA0 */
#define BSP_IO_SD0_DATA1 0xFFFF1101 /* SD0_DATA1 */
#define BSP_IO_SD0_DATA2 0xFFFF1102 /* SD0_DATA2 */
#define BSP_IO_SD0_DATA3 0xFFFF1103 /* SD0_DATA3 */
#define BSP_IO_SD0_DATA4 0xFFFF1104 /* SD0_DATA4 */
#define BSP_IO_SD0_DATA5 0xFFFF1105 /* SD0_DATA5 */
#define BSP_IO_SD0_DATA6 0xFFFF1106 /* SD0_DATA6 */
#define BSP_IO_SD0_DATA7 0xFFFF1107 /* SD0_DATA7 */
#define BSP_IO_SD1_CLK 0xFFFF1200 /* SD1_CLK */
#define BSP_IO_SD1_CMD 0xFFFF1201 /* SD1_CMD */
#define BSP_IO_SD1_DATA0 0xFFFF1300 /* SD1_DATA0 */
#define BSP_IO_SD1_DATA1 0xFFFF1301 /* SD1_DATA1 */
#define BSP_IO_SD1_DATA2 0xFFFF1302 /* SD1_DATA2 */
#define BSP_IO_SD1_DATA3 0xFFFF1303 /* SD1_DATA3 */
/*FILNUM*/
#define RZG_FILNUM_4_STAGE 0
#define RZG_FILNUM_8_STAGE 1
#define RZG_FILNUM_12_STAGE 2
#define RZG_FILNUM_16_STAGE 3
/*FILCLKSEL*/
#define RZG_FILCLKSEL_NOT_DIV 0
#define RZG_FILCLKSEL_DIV_9000 1
#define RZG_FILCLKSEL_DIV_18000 2
#define RZG_FILCLKSEL_DIV_36000 3
#define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_*/

9
modules/Kconfig.renesas_fsp
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@ -104,3 +104,12 @@ config USE_RA_FSP_ETHER
Enable RA FSP Ethernet driver
endif # HAS_RENESAS_RA_FSP
if HAS_RENESAS_RZ_FSP
config USE_RZ_FSP_IOPORT
bool
help
Enable RZ FSP IOPORT driver
endif

2
soc/renesas/rz/CMakeLists.txt
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@ -1,4 +1,6 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories_ifdef(CONFIG_HAS_RENESAS_RZ_FSP common)
add_subdirectory(${SOC_SERIES})

104
soc/renesas/rz/common/pinctrl_rzg.h Normal file
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@ -0,0 +1,104 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_
#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
#include <zephyr/types.h>
#include "r_ioport.h"
#ifdef __cplusplus
extern "C" {
#endif
/*Porting*/
typedef struct pinctrl_cfg_data_t {
uint32_t reserved: 4;
uint32_t pupd_reg: 6;
uint32_t iolh_reg: 6;
uint32_t pmc_reg: 2;
uint32_t ien_reg: 1;
uint32_t filonoff_reg: 1;
uint32_t filnum_reg: 2;
uint32_t filclksel_reg: 2;
uint32_t pfc_reg: 3;
} pinctrl_cfg_data_t;
typedef struct pinctrl_soc_pin_t {
bsp_io_port_pin_t port_pin;
pinctrl_cfg_data_t config;
} pinctrl_soc_pin_t;
/* Iterate over each pinctrl-n phandle child */
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx), \
Z_PINCTRL_STATE_PIN_CHILD_INIT)
/* Iterate over each pinctrl-n phandle child */
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())};
#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id) \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux), \
(DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)), \
()) \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \
(DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_SPECIAL_PINS_INIT)), \
())
#define RZG_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4))
#define RZG_GET_FUNC(pinmux) ((pinmux & 0xF0) >> 4)
#define RZG_GET_PU_PD(node_id) \
DT_PROP(node_id, bias_pull_up) == 1 ? 1U : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U : 0U)
#define RZG_GET_FILNUM(node_id) ((DT_PROP(node_id, renesas_filter) >> 2) & 0x3)
#define RZG_GET_FILCLKSEL(node_id) (DT_PROP(node_id, renesas_filter) & 0x3)
#define RZG_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1))
/* Process pinmux cfg */
#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \
{ \
.port_pin = RZG_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)), \
.config = \
{ \
.reserved = 0, \
.pupd_reg = RZG_GET_PU_PD(node_id), \
.iolh_reg = DT_PROP(node_id, drive_strength), \
.pmc_reg = 1, \
.ien_reg = DT_PROP(node_id, input_enable), \
.filonoff_reg = RZG_FILTER_ON_OFF(node_id), \
.filnum_reg = RZG_GET_FILNUM(node_id), \
.filclksel_reg = RZG_GET_FILCLKSEL(node_id), \
.pfc_reg = \
(RZG_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)) - \
1), \
}, \
},
#define Z_PINCTRL_SPECIAL_PINS_INIT(node_id, state_prop, idx) \
{ \
.port_pin = DT_PROP_BY_IDX(node_id, state_prop, idx), \
.config = \
{ \
.reserved = 0, \
.pupd_reg = RZG_GET_PU_PD(node_id), \
.iolh_reg = DT_PROP(node_id, drive_strength), \
.pmc_reg = 0, \
.ien_reg = DT_PROP(node_id, input_enable), \
.filonoff_reg = RZG_FILTER_ON_OFF(node_id), \
.filnum_reg = RZG_GET_FILNUM(node_id), \
.filclksel_reg = RZG_GET_FILCLKSEL(node_id), \
.pfc_reg = 0, \
}, \
},
#ifdef __cplusplus
}
#endif
#endif /*ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_*/

11
soc/renesas/rz/rzg3s/pinctrl_soc.h Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_RENESAS_RZ_RZG3S_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RENESAS_RZ_RZG3S_PINCTRL_SOC_H_
#include <pinctrl_rzg.h>
#endif /* ZEPHYR_SOC_RENESAS_RZ_RZG3S_PINCTRL_SOC_H_ */