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soc: renesas: ra: ra6m5: clear NVIC->ITNS at startup for non TZ

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Otherwise, interrupts will trigger a very funny fault
See https://github.com/arduino/ArduinoCore-renesas/blob/main/cores/arduino/main.cpp#L49-L57

Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
This commit is contained in:
Martino Facchin 2025-02-05 18:03:21 +01:00 • committed by Benjamin Cabé
commit f6f2e57ab9
1 changed files with 10 additions and 3 deletions
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13
soc/renesas/ra/ra6m5/soc.c
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@ -57,9 +57,16 @@ void soc_early_init_hook(void)
R_PSCU->PSARD = 0;
R_PSCU->PSARE = 0;
R_CPSCU->ICUSARG = 0;
R_CPSCU->ICUSARH = 0;
R_CPSCU->ICUSARI = 0;
/* The secure Attribute managed within the ARM CPU NVIC must match the
* security attribution of IELSEn registers (Reference section 13.2.9
* in the RA6M4 manual R01UH0890EJ0050).
*/
uint32_t volatile *p_icusarg = &R_CPSCU->ICUSARG;
for (int i = 0; i < BSP_ICU_VECTOR_MAX_ENTRIES / NUM_BITS(uint32_t); i++) {
p_icusarg[i] = 0;
NVIC->ITNS[i] = 0;
}
/* Enable protection using PRCR register. */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);