soc: renesas: ra2l1: Add initial support for Renesas RA2L1 SOC series
Add basic support for Renesas RA2L1 SOC series. Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com> Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
This commit is contained in:
Thao Luong
Fabio Baltieri
parent
18acd4ce40
commit
168284a8cc
13 changed files with 611 additions and 0 deletions
12
dts/arm/renesas/ra/ra2/r7fa2l1x9.dtsi
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12
dts/arm/renesas/ra/ra2/r7fa2l1x9.dtsi
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/**
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* Copyright (c) 2024 MUNIC SA
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*
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* Renesas R7FA2AL1x9 MCU device tree
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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&flash0 {
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reg = <0x0 DT_SIZE_K(128)>;
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};
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11
dts/arm/renesas/ra/ra2/r7fa2l1xb.dtsi
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11
dts/arm/renesas/ra/ra2/r7fa2l1xb.dtsi
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/**
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* Copyright (c) 2024 MUNIC SA
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*
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* Renesas R7FA2AL1AB MCU device tree
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&flash0 {
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reg = <0x0 DT_SIZE_K(256)>;
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};
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88
dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi
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88
dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi
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/**
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* Copyright (c) 2024 MUNIC SA
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* Copyright (c) 2024-2025 Renesas Electronics Corporation
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*
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* Renesas R7FA2AL1AxxxFP MCU device tree for 100 pins socket
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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/ {
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clocks: clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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xtal: clock-main-osc {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pclkblock: pclkblock@4001e01c {
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compatible = "renesas,ra-cgc-pclk-block";
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reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
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<0x40047008 4>;
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reg-names = "MSTPA", "MSTPB","MSTPC",
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"MSTPD";
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#clock-cells = <0>;
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clocks = <&hoco>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <48000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};
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234
dts/arm/renesas/ra/ra2/ra2l1.dtsi
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234
dts/arm/renesas/ra/ra2/ra2l1.dtsi
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/**
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* Copyright (c) 2021-2024 MUNIC SA
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* Renesas RA2L1 MCU series device tree
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m23";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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interrupt-parent = <&nvic>;
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 0x8000>;
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};
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system: system@4001e000 {
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compatible = "renesas,ra-system";
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reg = <0x4001e000 0x1000>;
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status = "okay";
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};
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flcn: flash-controller@407ec000 {
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reg = <0x407ec000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: code@0 {
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compatible = "soc-nv-flash";
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/* "reg" property should be defined in the
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* chip specific .dtsi file
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*/
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};
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flash1: data@40100000 {
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compatible = "soc-nv-flash";
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reg = <0x40100000 DT_SIZE_K(8)>;
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};
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};
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ioport0: gpio@40040000 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040000 0x20>;
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port = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport1: gpio@40040020 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040020 0x20>;
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port = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport2: gpio@40040040 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040040 0x20>;
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port = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport3: gpio@40040060 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040060 0x20>;
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port = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport4: gpio@40040080 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040080 0x20>;
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port = <4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport5: gpio@400400a0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400400a0 0x20>;
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port = <5>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport6: gpio@400400c0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400400c0 0x20>;
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port = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport7: gpio@400400e0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400400e0 0x20>;
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port = <7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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pinctrl: pin-controller@40040800 {
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compatible = "renesas,ra-pinctrl-pfs";
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reg = <0x40040800 0x3c0>;
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status = "okay";
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};
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sci0: sci0@40070000 {
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compatible = "renesas,ra-sci";
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interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070000 0x100>;
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clocks = <&pclkb MSTPB 31>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <0>;
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status = "disabled";
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};
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};
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sci1: sci1@40070020 {
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compatible = "renesas,ra-sci";
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reg = <0x40070020 0x100>;
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clocks = <&pclkb MSTPB 30>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <1>;
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status = "disabled";
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};
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};
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sci2: sci2@40070040 {
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compatible = "renesas,ra-sci";
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reg = <0x40070040 0x100>;
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clocks = <&pclkb MSTPB 29>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <2>;
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status = "disabled";
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};
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};
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sci3: sci3@40070060 {
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compatible = "renesas,ra-sci";
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reg = <0x40070060 0x100>;
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clocks = <&pclkb MSTPB 28>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <3>;
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status = "disabled";
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};
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};
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sci9: sci9@40070120 {
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compatible = "renesas,ra-sci";
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interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070120 0x100>;
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clocks = <&pclkb MSTPB 22>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <9>;
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status = "disabled";
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};
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};
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id_code: id_code@1010018 {
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compatible = "zephyr,memory-region";
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reg = <0x01010018 0x20>;
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zephyr,memory-region = "ID_CODE";
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};
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15
soc/renesas/ra/ra2l1/CMakeLists.txt
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15
soc/renesas/ra/ra2l1/CMakeLists.txt
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# Copyright (c) 2022-2024 MUNIC SA
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(ROM_START opt_set_mem.ld)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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14
soc/renesas/ra/ra2l1/Kconfig
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14
soc/renesas/ra/ra2l1/Kconfig
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# Copyright (c) 2024 MUNIC SA
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA2L1
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select ARM
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select CPU_CORTEX_M23
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select CPU_HAS_ARM_MPU
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select HAS_RENESAS_RA_FSP
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select CPU_CORTEX_M_HAS_VTOR
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select CPU_CORTEX_M_HAS_SYSTICK
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select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
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select HAS_SWO
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select SOC_EARLY_INIT_HOOK
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20
soc/renesas/ra/ra2l1/Kconfig.defconfig
Normal file
20
soc/renesas/ra/ra2l1/Kconfig.defconfig
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# Copyright (c) 2024 MUNIC SA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA2L1
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config NUM_IRQS
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default 32
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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endif # SOC_SERIES_RA2L1
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21
soc/renesas/ra/ra2l1/Kconfig.soc
Normal file
21
soc/renesas/ra/ra2l1/Kconfig.soc
Normal file
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# Copyright (c) 2024 MUNIC SA
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA2L1
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bool
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select SOC_FAMILY_RENESAS_RA
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config SOC_R7FA2L1A9XXFP
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bool
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select SOC_SERIES_RA2L1
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config SOC_R7FA2L1ABXXFP
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bool
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select SOC_SERIES_RA2L1
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config SOC_SERIES
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default "ra2l1" if SOC_SERIES_RA2L1
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config SOC
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default "r7fa2l1a9xxfp" if SOC_R7FA2L1A9XXFP
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default "r7fa2l1abxxfp" if SOC_R7FA2L1ABXXFP
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11
soc/renesas/ra/ra2l1/opt_set_mem.ld
Normal file
11
soc/renesas/ra/ra2l1/opt_set_mem.ld
Normal file
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM Registers start at address 0x00000400 */
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. = 0x400;
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KEEP(*(.rom_registers*))
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/* Reserving 0x100 bytes of space for ROM registers. */
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. = 0x500;
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123
soc/renesas/ra/ra2l1/sections.ld
Normal file
123
soc/renesas/ra/ra2l1/sections.ld
Normal file
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
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{
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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*(.fsp_dtc_vector_table)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
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SECTION_PROLOGUE(.option_setting_ofs,,)
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{
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__OPTION_SETTING_OFS_Start = .;
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KEEP(*(.option_setting_ofs0))
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. = __OPTION_SETTING_OFS_Start + 0x04;
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KEEP(*(.option_setting_ofs2))
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. = __OPTION_SETTING_OFS_Start + 0x10;
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KEEP(*(.option_setting_dualsel))
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__OPTION_SETTING_OFS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
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||||
|
||||
SECTION_PROLOGUE(.option_setting_sas,,)
|
||||
{
|
||||
__OPTION_SETTING_SAS_Start = .;
|
||||
KEEP(*(.option_setting_sas))
|
||||
__OPTION_SETTING_SAS_End = .;
|
||||
} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
|
||||
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
|
||||
|
||||
SECTION_PROLOGUE(.option_setting_ns,,)
|
||||
{
|
||||
__OPTION_SETTING_NS_Start = .;
|
||||
KEEP(*(.option_setting_ofs1))
|
||||
. = __OPTION_SETTING_NS_Start + 0x04;
|
||||
KEEP(*(.option_setting_ofs3))
|
||||
. = __OPTION_SETTING_NS_Start + 0x10;
|
||||
KEEP(*(.option_setting_banksel))
|
||||
. = __OPTION_SETTING_NS_Start + 0x40;
|
||||
KEEP(*(.option_setting_bps0))
|
||||
. = __OPTION_SETTING_NS_Start + 0x44;
|
||||
KEEP(*(.option_setting_bps1))
|
||||
. = __OPTION_SETTING_NS_Start + 0x48;
|
||||
KEEP(*(.option_setting_bps2))
|
||||
. = __OPTION_SETTING_NS_Start + 0x4C;
|
||||
KEEP(*(.option_setting_bps3))
|
||||
. = __OPTION_SETTING_NS_Start + 0x60;
|
||||
KEEP(*(.option_setting_pbps0))
|
||||
. = __OPTION_SETTING_NS_Start + 0x64;
|
||||
KEEP(*(.option_setting_pbps1))
|
||||
. = __OPTION_SETTING_NS_Start + 0x68;
|
||||
KEEP(*(.option_setting_pbps2))
|
||||
. = __OPTION_SETTING_NS_Start + 0x6C;
|
||||
KEEP(*(.option_setting_pbps3))
|
||||
__OPTION_SETTING_NS_End = .;
|
||||
} GROUP_LINK_IN(OPTION_SETTING) = 0xFF
|
||||
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
|
||||
|
||||
SECTION_PROLOGUE(.option_setting_s,,)
|
||||
{
|
||||
__OPTION_SETTING_S_Start = .;
|
||||
KEEP(*(.option_setting_ofs1_sec))
|
||||
. = __OPTION_SETTING_S_Start + 0x04;
|
||||
KEEP(*(.option_setting_ofs3_sec))
|
||||
. = __OPTION_SETTING_S_Start + 0x10;
|
||||
KEEP(*(.option_setting_banksel_sec))
|
||||
. = __OPTION_SETTING_S_Start + 0x40;
|
||||
KEEP(*(.option_setting_bps_sec0))
|
||||
. = __OPTION_SETTING_S_Start + 0x44;
|
||||
KEEP(*(.option_setting_bps_sec1))
|
||||
. = __OPTION_SETTING_S_Start + 0x48;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = __OPTION_SETTING_S_Start + 0x4C;
|
||||
KEEP(*(.option_setting_bps_sec3))
|
||||
. = __OPTION_SETTING_S_Start + 0x60;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = __OPTION_SETTING_S_Start + 0x64;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = __OPTION_SETTING_S_Start + 0x68;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = __OPTION_SETTING_S_Start + 0x6C;
|
||||
KEEP(*(.option_setting_pbps_sec3))
|
||||
. = __OPTION_SETTING_S_Start + 0x80;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0x84;
|
||||
KEEP(*(.option_setting_ofs3_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0x90;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0xC0;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = __OPTION_SETTING_S_Start + 0xC4;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = __OPTION_SETTING_S_Start + 0xC8;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
. = __OPTION_SETTING_S_Start + 0xCC;
|
||||
KEEP(*(.option_setting_bps_sel3))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
|
||||
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
|
||||
|
||||
SECTION_PROLOGUE(.id_code,,)
|
||||
{
|
||||
KEEP(*(.id_code*))
|
||||
} GROUP_LINK_IN(ID_CODE)
|
||||
|
||||
#endif
|
||||
41
soc/renesas/ra/ra2l1/soc.c
Normal file
41
soc/renesas/ra/ra2l1/soc.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2023-2024 MUNIC SA
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Renesas RA2L1 family processor
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/arch/cpu.h>
|
||||
#include <cmsis_core.h>
|
||||
#include <zephyr/arch/arm/nmi.h>
|
||||
#include <zephyr/irq.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
#include "bsp_cfg.h"
|
||||
#include <bsp_api.h>
|
||||
|
||||
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
|
||||
|
||||
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
|
||||
|
||||
/**
|
||||
* @brief Perform basic hardware initialization at boot.
|
||||
*
|
||||
* This needs to be run from the very beginning.
|
||||
*/
|
||||
void soc_early_init_hook(void)
|
||||
{
|
||||
|
||||
SystemCoreClock = BSP_MOCO_HZ;
|
||||
g_protect_pfswe_counter = 0;
|
||||
|
||||
}
|
||||
17
soc/renesas/ra/ra2l1/soc.h
Normal file
17
soc/renesas/ra/ra2l1/soc.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2021-2024 MUNIC SA
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Renesas RA2L1 family MCU
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_
|
||||
#define ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_
|
||||
|
||||
#include <bsp_api.h>
|
||||
|
||||
#endif /* ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_ */
|
||||
|
|
@ -4,6 +4,10 @@ family:
|
|||
- name: ra2a1
|
||||
socs:
|
||||
- name: r7fa2a1ab3cfm
|
||||
- name: ra2l1
|
||||
socs:
|
||||
- name: r7fa2l1a9xxfp
|
||||
- name: r7fa2l1abxxfp
|
||||
- name: ra4e1
|
||||
socs:
|
||||
- name: r7fa4e10d2cfm
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue