soc: renesas: ra2l1: Add initial support for Renesas RA2L1 SOC series

Add basic support for Renesas RA2L1 SOC series.

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
This commit is contained in:
Thao Luong 2025-01-14 23:15:32 +07:00 committed by Fabio Baltieri
commit 168284a8cc
13 changed files with 611 additions and 0 deletions

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/**
* Copyright (c) 2024 MUNIC SA
*
* Renesas R7FA2AL1x9 MCU device tree
*
* SPDX-License-Identifier: Apache-2.0
*
*/
&flash0 {
reg = <0x0 DT_SIZE_K(128)>;
};

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/**
* Copyright (c) 2024 MUNIC SA
*
* Renesas R7FA2AL1AB MCU device tree
*
* SPDX-License-Identifier: Apache-2.0
*/
&flash0 {
reg = <0x0 DT_SIZE_K(256)>;
};

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/**
* Copyright (c) 2024 MUNIC SA
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* Renesas R7FA2AL1AxxxFP MCU device tree for 100 pins socket
*
* SPDX-License-Identifier: Apache-2.0
*
*/
/ {
clocks: clocks {
#address-cells = <1>;
#size-cells = <1>;
xtal: clock-main-osc {
compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(20)>;
#clock-cells = <0>;
status = "disabled";
};
hoco: clock-hoco {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(48)>;
#clock-cells = <0>;
};
moco: clock-moco {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(8)>;
#clock-cells = <0>;
};
loco: clock-loco {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
subclk: clock-subclk {
compatible = "renesas,ra-cgc-subclk";
clock-frequency = <32768>;
#clock-cells = <0>;
status = "disabled";
};
pclkblock: pclkblock@4001e01c {
compatible = "renesas,ra-cgc-pclk-block";
reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
<0x40047008 4>;
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD";
#clock-cells = <0>;
clocks = <&hoco>;
status = "okay";
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clock-frequency = <48000000>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
div = <1>;
#clock-cells = <2>;
status = "okay";
};
clkout: clkout {
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
};
};
};

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/**
* Copyright (c) 2021-2024 MUNIC SA
* Copyright (c) 2024 Renesas Electronics Corporation
*
* Renesas RA2L1 MCU series device tree
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <freq.h>
#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m23";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";
reg = <0xe000ed90 0x40>;
};
};
};
soc {
interrupt-parent = <&nvic>;
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x8000>;
};
system: system@4001e000 {
compatible = "renesas,ra-system";
reg = <0x4001e000 0x1000>;
status = "okay";
};
flcn: flash-controller@407ec000 {
reg = <0x407ec000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
flash0: code@0 {
compatible = "soc-nv-flash";
/* "reg" property should be defined in the
* chip specific .dtsi file
*/
};
flash1: data@40100000 {
compatible = "soc-nv-flash";
reg = <0x40100000 DT_SIZE_K(8)>;
};
};
ioport0: gpio@40040000 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x40040000 0x20>;
port = <0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport1: gpio@40040020 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x40040020 0x20>;
port = <1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport2: gpio@40040040 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x40040040 0x20>;
port = <2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport3: gpio@40040060 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x40040060 0x20>;
port = <3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport4: gpio@40040080 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x40040080 0x20>;
port = <4>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport5: gpio@400400a0 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x400400a0 0x20>;
port = <5>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport6: gpio@400400c0 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x400400c0 0x20>;
port = <6>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport7: gpio@400400e0 {
compatible = "renesas,ra-gpio-ioport";
reg = <0x400400e0 0x20>;
port = <7>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
pinctrl: pin-controller@40040800 {
compatible = "renesas,ra-pinctrl-pfs";
reg = <0x40040800 0x3c0>;
status = "okay";
};
sci0: sci0@40070000 {
compatible = "renesas,ra-sci";
interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40070000 0x100>;
clocks = <&pclkb MSTPB 31>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <0>;
status = "disabled";
};
};
sci1: sci1@40070020 {
compatible = "renesas,ra-sci";
reg = <0x40070020 0x100>;
clocks = <&pclkb MSTPB 30>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <1>;
status = "disabled";
};
};
sci2: sci2@40070040 {
compatible = "renesas,ra-sci";
reg = <0x40070040 0x100>;
clocks = <&pclkb MSTPB 29>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <2>;
status = "disabled";
};
};
sci3: sci3@40070060 {
compatible = "renesas,ra-sci";
reg = <0x40070060 0x100>;
clocks = <&pclkb MSTPB 28>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <3>;
status = "disabled";
};
};
sci9: sci9@40070120 {
compatible = "renesas,ra-sci";
interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40070120 0x100>;
clocks = <&pclkb MSTPB 22>;
status = "disabled";
uart {
compatible = "renesas,ra-sci-uart";
channel = <9>;
status = "disabled";
};
};
id_code: id_code@1010018 {
compatible = "zephyr,memory-region";
reg = <0x01010018 0x20>;
zephyr,memory-region = "ID_CODE";
status = "okay";
};
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};

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# Copyright (c) 2022-2024 MUNIC SA
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
)
zephyr_linker_sources(ROM_START opt_set_mem.ld)
zephyr_linker_sources(SECTIONS sections.ld)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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# Copyright (c) 2024 MUNIC SA
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RA2L1
select ARM
select CPU_CORTEX_M23
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CPU_CORTEX_M_HAS_VTOR
select CPU_CORTEX_M_HAS_SYSTICK
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select HAS_SWO
select SOC_EARLY_INIT_HOOK

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# Copyright (c) 2024 MUNIC SA
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_RA2L1
config NUM_IRQS
default 32
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA2L1

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# Copyright (c) 2024 MUNIC SA
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RA2L1
bool
select SOC_FAMILY_RENESAS_RA
config SOC_R7FA2L1A9XXFP
bool
select SOC_SERIES_RA2L1
config SOC_R7FA2L1ABXXFP
bool
select SOC_SERIES_RA2L1
config SOC_SERIES
default "ra2l1" if SOC_SERIES_RA2L1
config SOC
default "r7fa2l1a9xxfp" if SOC_R7FA2L1A9XXFP
default "r7fa2l1abxxfp" if SOC_R7FA2L1ABXXFP

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/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM Registers start at address 0x00000400 */
. = 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = 0x500;

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/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
*(.fsp_dtc_vector_table)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
SECTION_PROLOGUE(.option_setting_ofs,,)
{
__OPTION_SETTING_OFS_Start = .;
KEEP(*(.option_setting_ofs0))
. = __OPTION_SETTING_OFS_Start + 0x04;
KEEP(*(.option_setting_ofs2))
. = __OPTION_SETTING_OFS_Start + 0x10;
KEEP(*(.option_setting_dualsel))
__OPTION_SETTING_OFS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
SECTION_PROLOGUE(.option_setting_sas,,)
{
__OPTION_SETTING_SAS_Start = .;
KEEP(*(.option_setting_sas))
__OPTION_SETTING_SAS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
SECTION_PROLOGUE(.option_setting_ns,,)
{
__OPTION_SETTING_NS_Start = .;
KEEP(*(.option_setting_ofs1))
. = __OPTION_SETTING_NS_Start + 0x04;
KEEP(*(.option_setting_ofs3))
. = __OPTION_SETTING_NS_Start + 0x10;
KEEP(*(.option_setting_banksel))
. = __OPTION_SETTING_NS_Start + 0x40;
KEEP(*(.option_setting_bps0))
. = __OPTION_SETTING_NS_Start + 0x44;
KEEP(*(.option_setting_bps1))
. = __OPTION_SETTING_NS_Start + 0x48;
KEEP(*(.option_setting_bps2))
. = __OPTION_SETTING_NS_Start + 0x4C;
KEEP(*(.option_setting_bps3))
. = __OPTION_SETTING_NS_Start + 0x60;
KEEP(*(.option_setting_pbps0))
. = __OPTION_SETTING_NS_Start + 0x64;
KEEP(*(.option_setting_pbps1))
. = __OPTION_SETTING_NS_Start + 0x68;
KEEP(*(.option_setting_pbps2))
. = __OPTION_SETTING_NS_Start + 0x6C;
KEEP(*(.option_setting_pbps3))
__OPTION_SETTING_NS_End = .;
} GROUP_LINK_IN(OPTION_SETTING) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
SECTION_PROLOGUE(.option_setting_s,,)
{
__OPTION_SETTING_S_Start = .;
KEEP(*(.option_setting_ofs1_sec))
. = __OPTION_SETTING_S_Start + 0x04;
KEEP(*(.option_setting_ofs3_sec))
. = __OPTION_SETTING_S_Start + 0x10;
KEEP(*(.option_setting_banksel_sec))
. = __OPTION_SETTING_S_Start + 0x40;
KEEP(*(.option_setting_bps_sec0))
. = __OPTION_SETTING_S_Start + 0x44;
KEEP(*(.option_setting_bps_sec1))
. = __OPTION_SETTING_S_Start + 0x48;
KEEP(*(.option_setting_bps_sec2))
. = __OPTION_SETTING_S_Start + 0x4C;
KEEP(*(.option_setting_bps_sec3))
. = __OPTION_SETTING_S_Start + 0x60;
KEEP(*(.option_setting_pbps_sec0))
. = __OPTION_SETTING_S_Start + 0x64;
KEEP(*(.option_setting_pbps_sec1))
. = __OPTION_SETTING_S_Start + 0x68;
KEEP(*(.option_setting_pbps_sec2))
. = __OPTION_SETTING_S_Start + 0x6C;
KEEP(*(.option_setting_pbps_sec3))
. = __OPTION_SETTING_S_Start + 0x80;
KEEP(*(.option_setting_ofs1_sel))
. = __OPTION_SETTING_S_Start + 0x84;
KEEP(*(.option_setting_ofs3_sel))
. = __OPTION_SETTING_S_Start + 0x90;
KEEP(*(.option_setting_banksel_sel))
. = __OPTION_SETTING_S_Start + 0xC0;
KEEP(*(.option_setting_bps_sel0))
. = __OPTION_SETTING_S_Start + 0xC4;
KEEP(*(.option_setting_bps_sel1))
. = __OPTION_SETTING_S_Start + 0xC8;
KEEP(*(.option_setting_bps_sel2))
. = __OPTION_SETTING_S_Start + 0xCC;
KEEP(*(.option_setting_bps_sel3))
__OPTION_SETTING_S_End = .;
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
SECTION_PROLOGUE(.id_code,,)
{
KEEP(*(.id_code*))
} GROUP_LINK_IN(ID_CODE)
#endif

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/*
* Copyright (c) 2023-2024 MUNIC SA
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Renesas RA2L1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#include "bsp_cfg.h"
#include <bsp_api.h>
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
*/
void soc_early_init_hook(void)
{
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
}

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/*
* Copyright (c) 2021-2024 MUNIC SA
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the Renesas RA2L1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_ */

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@ -4,6 +4,10 @@ family:
- name: ra2a1
socs:
- name: r7fa2a1ab3cfm
- name: ra2l1
socs:
- name: r7fa2l1a9xxfp
- name: r7fa2l1abxxfp
- name: ra4e1
socs:
- name: r7fa4e10d2cfm