drivers: pinctrl: Support pinctrl driver for Renesas RX
Intial support of pinctrl driver for Renesas RX MCU family. This support base on using Renesas RX driver package in hal_renesas layer Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com> Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This commit is contained in:
Duy Nguyen
Benjamin Cabé
parent
ad42e4d87d
commit
2aa071c7ad
9 changed files with 788 additions and 0 deletions
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@ -3,6 +3,7 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RX rx/pinctrl_renesas_rx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZ rz/pinctrl_renesas_rz.c)
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11
drivers/pinctrl/renesas/rx/Kconfig
Normal file
11
drivers/pinctrl/renesas/rx/Kconfig
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@ -0,0 +1,11 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_RENESAS_RX
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bool "Renesas RX series pin controller driver"
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default y
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depends on DT_HAS_RENESAS_RX_PINCTRL_ENABLED
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select USE_RX_RDP_MPC
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select USE_RX_RDP_GPIO
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help
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Enable Renesas RX series pin controller driver.
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153
drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c
Normal file
153
drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c
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@ -0,0 +1,153 @@
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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/* Renesas FIT module for iodefine.h data structures */
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#include "platform.h"
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#include "r_gpio_rx_if.h"
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#include "r_mpc_rx_if.h"
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#define PORT_POS (8)
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extern const uint8_t g_gpio_open_drain_n_support[];
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extern const uint8_t g_gpio_pull_up_support[];
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extern const uint8_t g_gpio_dscr_support[];
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static bool gpio_pin_function_check(uint8_t const *check_array, uint8_t port_number,
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uint8_t pin_number)
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{
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if ((check_array[port_number] & (1 << pin_number)) != 0) {
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return true;
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} else {
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return false;
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}
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}
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static int pinctrl_configure_pullup(const pinctrl_soc_pin_t *pin, uint32_t value)
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{
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gpio_port_pin_t port_pin;
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bool pin_check;
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int ret = 0;
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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pin_check = gpio_pin_function_check(g_gpio_pull_up_support, pin->port_num, pin->pin_num);
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if (pin_check) {
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ret = R_GPIO_PinControl(port_pin, (value ? GPIO_CMD_IN_PULL_UP_ENABLE
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: GPIO_CMD_IN_PULL_UP_DISABLE));
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}
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return ret;
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}
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static int pinctrl_configure_dscr(const pinctrl_soc_pin_t *pin, uint32_t value)
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{
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gpio_port_pin_t port_pin;
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bool pin_check;
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int ret = 0;
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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pin_check = gpio_pin_function_check(g_gpio_dscr_support, pin->port_num, pin->pin_num);
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if (pin_check) {
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ret = R_GPIO_PinControl(port_pin,
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(value ? GPIO_CMD_DSCR_ENABLE : GPIO_CMD_DSCR_DISABLE));
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}
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return ret;
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}
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static int pinctrl_configure_opendrain(const pinctrl_soc_pin_t *pin, uint32_t value)
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{
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gpio_port_pin_t port_pin;
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bool pin_check;
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int ret = 0;
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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pin_check =
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gpio_pin_function_check(g_gpio_open_drain_n_support, pin->port_num, pin->pin_num);
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if (pin_check) {
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ret = R_GPIO_PinControl(
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port_pin, (value ? GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN : GPIO_CMD_OUT_CMOS));
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}
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return ret;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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gpio_port_pin_t port_pin;
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mpc_config_t pconfig = {
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.pin_function = 0x0,
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.irq_enable = false,
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.analog_enable = false,
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};
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int ret;
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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const pinctrl_soc_pin_t *pin = &pins[i];
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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/* Set PMR register to 0 before setting pin control register */
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ret = R_GPIO_PinControl(port_pin, GPIO_CMD_ASSIGN_TO_GPIO);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set output high */
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if (pin->cfg.output_high) {
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R_GPIO_PinWrite(port_pin, GPIO_LEVEL_HIGH);
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}
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/* Set port direction */
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if (pin->cfg.output_enable) {
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R_GPIO_PinDirectionSet(port_pin, GPIO_DIRECTION_OUTPUT);
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}
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/* Set pull-up */
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ret = pinctrl_configure_pullup(pin, pin->cfg.bias_pull_up);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set open-drain */
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ret = pinctrl_configure_opendrain(pin, pin->cfg.drive_open_drain);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set drive-strength */
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ret = pinctrl_configure_dscr(pin, pin->cfg.drive_strength);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set pin function */
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pconfig.analog_enable = pin->cfg.analog_enable;
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pconfig.pin_function = pin->cfg.psels;
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ret = R_MPC_Write(port_pin, &pconfig);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set MODE */
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if (pin->cfg.pin_mode) {
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ret = R_GPIO_PinControl(port_pin, GPIO_CMD_ASSIGN_TO_PERIPHERAL);
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if (ret != 0) {
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return -EINVAL;
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}
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}
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}
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return 0;
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}
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105
dts/bindings/pinctrl/renesas,rx-pinctrl.yaml
Normal file
105
dts/bindings/pinctrl/renesas,rx-pinctrl.yaml
Normal file
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@ -0,0 +1,105 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: |
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description: |
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The Renesas RX pin controller is a node responsible for controlling
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pin function selection and pin properties
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as shown in this example:
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/* You can put this in places like a board-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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*/
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/* include pre-defined combinations for the SoC variant used by the board */
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#include <dt-bindings/pinctrl/renesas/rx-pinctrl.h>
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&pinctrl {
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sci1_default: sci1_default {
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group1 {
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psels = <RX_PSEL(RX_PSEL_SCI_1, 2, 6)>; /* TX */
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drive-strength = "medium";
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};
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group2 {
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psels = <RX_PSEL(RX_PSEL_SCI_1, 3, 0)>; /* RX */
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drive-strength = "medium";
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};
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};
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};
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The 'sci1_default' child node encodes the pin configurations for a
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particular state of a device; in this case, the default (that is, active)
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state.
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As shown, pin configurations are organized in groups within each child node.
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Each group can specify a list of pin function selections in the 'psels'
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property.
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A group can also specify shared pin properties common to all the specified
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pins, such as the 'input-enable' property in group 2. Here is a list of
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supported standard pin properties:
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- bias-disable: Disable pull-up/down (default, not required).
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- bias-pull-up: Enable pull-up resistor.
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- input-enable: Enable input from the pin.
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- drive-strength: Set the drive strength of the pin. Possible
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values are: normal, high.
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To link pin configurations with a device, use a pinctrl-N property for some
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number N, like this example you could place in your board's DTS file:
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#include "board-pinctrl.dtsi"
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&sci1 {
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pinctrl-0 = <&uart0_default>;
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pinctrl-1 = <&uart0_sleep>;
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pinctrl-names = "default", "sleep";
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};
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compatible: "renesas,rx-pinctrl"
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include: base.yaml
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child-binding:
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description: |
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Definitions for a pinctrl state.
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child-binding:
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-disable
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- bias-pull-up
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- input-enable
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- output-enable
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- output-high
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- drive-open-drain
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properties:
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psels:
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required: true
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type: array
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description: |
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An array of pins sharing the same group properties. Each
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element of the array is an integer constructed from the
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pin number and the alternative function of the pin.
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drive-strength:
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type: string
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enum:
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- "normal"
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- "high"
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default: "normal"
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description: |
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The drive strength of a pin. The default value is normal, as this
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is the power on reset value.
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renesas,analog-enable:
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type: boolean
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description: enable analog input
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25
dts/bindings/pinctrl/renesas,rx-pinmux.yaml
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25
dts/bindings/pinctrl/renesas,rx-pinmux.yaml
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Rensas RX Pinmux (Multi Function Pin Controller, MPC)
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compatible: "renesas,rx-pinmux"
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include: base.yaml
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properties:
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reg:
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required: true
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"#pinmux-cells":
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type: int
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required: true
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const: 2
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description: number of items in a pinmux specifier
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pinmux-cells:
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- pin
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- function
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child-binding:
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include: pincfg-node.yaml
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@ -10,6 +10,7 @@
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#include <mem.h>
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#include <zephyr/dt-bindings/clock/rx_clock.h>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h>
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/ {
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#address-cells = <1>;
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397
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h
Normal file
397
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h
Normal file
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PINCTRL_RX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PINCTRL_RX_H_
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#define RX_PORT_NUM_POS 0
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#define RX_PORT_NUM_MASK 0x1f
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#define RX_PIN_NUM_POS 5
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#define RX_PIN_NUM_MASK 0xf
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#define RX_PSEL_MASK 0x1f
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#define RX_PSEL_POS 9
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#define RX_PSEL_SCI_1 0xA
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#define RX_PSEL_SCI_6 0xB
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#define RX_PSEL_TMR 0x5
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#define RX_PSEL_POE 0x7
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/* P0nPFS */
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#define RX_PSEL_P0nPFS_HIZ 0x0
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#define RX_PSEL_P0nPFS_ADTRG0 0x1
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/* P1nPFS */
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#define RX_PSEL_P1nPFS_MTIOC0B 0x01
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#define RX_PSEL_P1nPFS_MTIOC3A 0x01
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#define RX_PSEL_P1nPFS_MTIOC3C 0x01
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#define RX_PSEL_P1nPFS_MTCLKA 0x02
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#define RX_PSEL_P1nPFS_MTCLKB 0x02
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#define RX_PSEL_P1nPFS_MTIOC3B 0x02
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#define RX_PSEL_P1nPFS_MTIOC3D 0x02
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#define RX_PSEL_P1nPFS_TMCI1 0x5
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#define RX_PSEL_P1nPFS_TMO1 0x5
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#define RX_PSEL_P1nPFS_TMCI2 0x5
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#define RX_PSEL_P1nPFS_TMO2 0x5
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#define RX_PSEL_P1nPFS_TMRI2 0x5
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#define RX_PSEL_P1nPFS_TMO3 0x5
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#define RX_PSEL_P1nPFS_RTCOUT 0x7
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#define RX_PSEL_P1nPFS_POE8 0x7
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#define RX_PSEL_P1nPFS_ADTRG0 0x9
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#define RX_PSEL_P1nPFS_RXD1 0xA
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#define RX_PSEL_P1nPFS_SMISO1 0xA
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#define RX_PSEL_P1nPFS_SSCL1 0xA
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#define RX_PSEL_P1nPFS_TXD1 0xA
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#define RX_PSEL_P1nPFS_SMOSI1 0xA
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#define RX_PSEL_P1nPFS_SSDA1 0xA
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#define RX_PSEL_P1nPFS_CTS1 0xB
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#define RX_PSEL_P1nPFS_RTS1 0xB
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#define RX_PSEL_P1nPFS_SS1 0xB
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#define RX_PSEL_P1nPFS_MOSIA 0xD
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#define RX_PSEL_P1nPFS_MISOA 0xD
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#define RX_PSEL_P1nPFS_SCL 0xF
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#define RX_PSEL_P1nPFS_SDA 0xF
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#define RX_PSEL_P1nPFS_TS5 0x19
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#define RX_PSEL_P1nPFS_TS6 0x19
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/* P2nPFS */
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#define RX_PSEL_P2nPFS_MTIOC1A 0x01
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#define RX_PSEL_P2nPFS_MTIOC1B 0x01
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#define RX_PSEL_P2nPFS_MTIOC2A 0x01
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#define RX_PSEL_P2nPFS_MTIOC2B 0x01
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#define RX_PSEL_P2nPFS_MTIOC3B 0x01
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#define RX_PSEL_P2nPFS_MTIOC3D 0x01
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#define RX_PSEL_P2nPFS_MTIOC4A 0x01
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#define RX_PSEL_P2nPFS_MTIOC4C 0x01
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#define RX_PSEL_P2nPFS_MTCLKA 0x02
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#define RX_PSEL_P2nPFS_MTCLKB 0x02
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#define RX_PSEL_P2nPFS_MTCLKC 0x02
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#define RX_PSEL_P2nPFS_MTCLKD 0x02
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#define RX_PSEL_P2nPFS_TMCI0 0x5
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#define RX_PSEL_P2nPFS_TMO0 0x5
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#define RX_PSEL_P2nPFS_TMRI0 0x5
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#define RX_PSEL_P2nPFS_TMO1 0x5
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#define RX_PSEL_P2nPFS_TMRI1 0x5
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#define RX_PSEL_P2nPFS_TMCI3 0x5
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#define RX_PSEL_P2nPFS_ADTRG0 0x9
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#define RX_PSEL_P2nPFS_RXD0 0xA
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#define RX_PSEL_P2nPFS_SMISO0 0xA
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#define RX_PSEL_P2nPFS_SSCL0 0xA
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#define RX_PSEL_P2nPFS_TXD0 0xA
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#define RX_PSEL_P2nPFS_SMOSI0 0xA
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#define RX_PSEL_P2nPFS_SSDA0 0xA
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#define RX_PSEL_P2nPFS_SCK0 0xA
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#define RX_PSEL_P2nPFS_TXD1 0xA
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#define RX_PSEL_P2nPFS_SMOSI1 0xA
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#define RX_PSEL_P2nPFS_SSDA1 0xA
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#define RX_PSEL_P2nPFS_SCK1 0xA
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#define RX_PSEL_P2nPFS_CTS0 0xB
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#define RX_PSEL_P2nPFS_RTS0 0xB
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#define RX_PSEL_P2nPFS_SS0 0xB
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#define RX_PSEL_P2nPFS_TS3 0x19
|
||||
#define RX_PSEL_P2nPFS_TS4 0x19
|
||||
|
||||
/* P3nPFS */
|
||||
#define RX_PSEL_P3nPFS_MTIOC0A 0x01
|
||||
#define RX_PSEL_P3nPFS_MTIOC0C 0x01
|
||||
#define RX_PSEL_P3nPFS_MTIOC0D 0x01
|
||||
#define RX_PSEL_P3nPFS_MTIOC4B 0x01
|
||||
#define RX_PSEL_P3nPFS_MTIOC4D 0x01
|
||||
|
||||
#define RX_PSEL_P3nPFS_TMCI2 0x5
|
||||
#define RX_PSEL_P3nPFS_TMO3 0x5
|
||||
#define RX_PSEL_P3nPFS_TMRI3 0x5
|
||||
#define RX_PSEL_P3nPFS_TMCI3 0x5
|
||||
|
||||
#define RX_PSEL_P3nPFS_RTCOUT 0x7
|
||||
#define RX_PSEL_P3nPFS_POE2 0x7
|
||||
#define RX_PSEL_P3nPFS_POE3 0x7
|
||||
#define RX_PSEL_P3nPFS_POE8 0x7
|
||||
|
||||
#define RX_PSEL_P3nPFS_RXD1 0xA
|
||||
#define RX_PSEL_P3nPFS_SMISO1 0xA
|
||||
#define RX_PSEL_P3nPFS_SSCL1 0xA
|
||||
|
||||
#define RX_PSEL_P3nPFS_CTS1 0xB
|
||||
#define RX_PSEL_P3nPFS_RTS1 0xB
|
||||
#define RX_PSEL_P3nPFS_SS1 0xB
|
||||
#define RX_PSEL_P3nPFS_RXD6 0xB
|
||||
#define RX_PSEL_P3nPFS_SMISO6 0xB
|
||||
#define RX_PSEL_P3nPFS_SSCL6 0xB
|
||||
#define RX_PSEL_P3nPFS_TXD6 0xB
|
||||
#define RX_PSEL_P3nPFS_SMOSI6 0xB
|
||||
#define RX_PSEL_P3nPFS_SSDA6 0xB
|
||||
#define RX_PSEL_P3nPFS_SCK6 0xB
|
||||
|
||||
#define RX_PSEL_P3nPFS_TS0 0x19
|
||||
#define RX_PSEL_P3nPFS_TS1 0x19
|
||||
#define RX_PSEL_P3nPFS_TS2 0x19
|
||||
|
||||
/* P5nPFS */
|
||||
#define RX_PSEL_P5nPFS_MTIOC4B 0x01
|
||||
#define RX_PSEL_P5nPFS_MTIOC4D 0x01
|
||||
|
||||
#define RX_PSEL_P5nPFS_TMCI1 0x5
|
||||
#define RX_PSEL_P5nPFS_TMO3 0x5
|
||||
|
||||
#define RX_PSEL_P5nPFS_TS11 0x19
|
||||
#define RX_PSEL_P5nPFS_TS12 0x19
|
||||
|
||||
#define RX_PSEL_P5nPFS_PMC0 0x19
|
||||
#define RX_PSEL_P5nPFS_PMC1 0x19
|
||||
|
||||
/* PAnPFS */
|
||||
#define RX_PSEL_PAnPFS_MTIOC4A 0x01
|
||||
#define RX_PSEL_PAnPFS_MTIOC0B 0x01
|
||||
#define RX_PSEL_PAnPFS_MTIOC0D 0x01
|
||||
#define RX_PSEL_PAnPFS_MTIOC5U 0x01
|
||||
#define RX_PSEL_PAnPFS_MTIOC5V 0x01
|
||||
|
||||
#define RX_PSEL_PAnPFS_MTCLKA 0x02
|
||||
#define RX_PSEL_PAnPFS_MTCLKB 0x02
|
||||
#define RX_PSEL_PAnPFS_MTCLKC 0x02
|
||||
#define RX_PSEL_PAnPFS_MTCLKD 0x02
|
||||
|
||||
#define RX_PSEL_PAnPFS_TMRI0 0x5
|
||||
#define RX_PSEL_PAnPFS_TMCI3 0x5
|
||||
|
||||
#define RX_PSEL_PAnPFS_POE2 0x7
|
||||
#define RX_PSEL_PAnPFS_CACREF 0x7
|
||||
|
||||
#define RX_PSEL_PAnPFS_RXD5 0xA
|
||||
#define RX_PSEL_PAnPFS_SMISO5 0xA
|
||||
#define RX_PSEL_PAnPFS_SSCL5 0xA
|
||||
#define RX_PSEL_PAnPFS_TXD5 0xA
|
||||
#define RX_PSEL_PAnPFS_SMOSI5 0xA
|
||||
#define RX_PSEL_PAnPFS_SSDA5 0xA
|
||||
#define RX_PSEL_PAnPFS_SCK5 0xA
|
||||
|
||||
#define RX_PSEL_PAnPFS_CTS5 0xB
|
||||
#define RX_PSEL_PAnPFS_RTS5 0xB
|
||||
#define RX_PSEL_PAnPFS_SS5 0xB
|
||||
|
||||
#define RX_PSEL_PAnPFS_SSLA0 0xD
|
||||
#define RX_PSEL_PAnPFS_SSLA1 0xD
|
||||
#define RX_PSEL_PAnPFS_SSLA2 0xD
|
||||
#define RX_PSEL_PAnPFS_SSLA3 0xD
|
||||
#define RX_PSEL_PAnPFS_RSPCKA 0xD
|
||||
#define RX_PSEL_PAnPFS_MOSIA 0xD
|
||||
#define RX_PSEL_PAnPFS_MISOA 0xD
|
||||
|
||||
#define RX_PSEL_PAnPFS_TS26 0x19
|
||||
#define RX_PSEL_PAnPFS_TS27 0x19
|
||||
#define RX_PSEL_PAnPFS_TS28 0x19
|
||||
#define RX_PSEL_PAnPFS_TS29 0x19
|
||||
#define RX_PSEL_PAnPFS_TS30 0x19
|
||||
#define RX_PSEL_PAnPFS_TS31 0x19
|
||||
#define RX_PSEL_PAnPFS_TS32 0x19
|
||||
|
||||
/* PBnPFS */
|
||||
#define RX_PSEL_PBnPFS_MTIOC0A 0x01
|
||||
#define RX_PSEL_PBnPFS_MTIOC0C 0x01
|
||||
#define RX_PSEL_PBnPFS_MTIOC2A 0x01
|
||||
#define RX_PSEL_PBnPFS_MTIOC3B 0x01
|
||||
#define RX_PSEL_PBnPFS_MTIOC3D 0x01
|
||||
#define RX_PSEL_PBnPFS_MTIOC5W 0x01
|
||||
|
||||
#define RX_PSEL_PBnPFS_MTIOC1B 0x02
|
||||
#define RX_PSEL_PBnPFS_MTIOC4A 0x02
|
||||
#define RX_PSEL_PBnPFS_MTIOC4C 0x02
|
||||
|
||||
#define RX_PSEL_PBnPFS_TMO0 0x5
|
||||
#define RX_PSEL_PBnPFS_TMRI1 0x5
|
||||
#define RX_PSEL_PBnPFS_TMCI0 0x5
|
||||
|
||||
#define RX_PSEL_PBnPFS_POE1 0x7
|
||||
#define RX_PSEL_PBnPFS_POE3 0x7
|
||||
|
||||
#define RX_PSEL_PBnPFS_RXD9 0xA
|
||||
#define RX_PSEL_PBnPFS_SMISO9 0xA
|
||||
#define RX_PSEL_PBnPFS_SSCL9 0xA
|
||||
#define RX_PSEL_PBnPFS_TXD9 0xA
|
||||
#define RX_PSEL_PBnPFS_SMOSI9 0xA
|
||||
#define RX_PSEL_PBnPFS_SSDA9 0xA
|
||||
#define RX_PSEL_PBnPFS_SCK9 0xA
|
||||
|
||||
#define RX_PSEL_PBnPFS_CTS6 0xB
|
||||
#define RX_PSEL_PBnPFS_RTS6 0xB
|
||||
#define RX_PSEL_PBnPFS_SS6 0xB
|
||||
#define RX_PSEL_PBnPFS_CTS9 0xB
|
||||
#define RX_PSEL_PBnPFS_RTS9 0xB
|
||||
#define RX_PSEL_PBnPFS_SS9 0xB
|
||||
#define RX_PSEL_PBnPFS_RXD6 0xB
|
||||
#define RX_PSEL_PBnPFS_SMISO6 0xB
|
||||
#define RX_PSEL_PBnPFS_SSCL6 0xB
|
||||
#define RX_PSEL_PBnPFS_TXD6 0xB
|
||||
#define RX_PSEL_PBnPFS_SMOSI6 0xB
|
||||
#define RX_PSEL_PBnPFS_SSDA6 0xB
|
||||
#define RX_PSEL_PBnPFS_SCK6 0xB
|
||||
|
||||
#define RX_PSEL_PBnPFS_RSPCKA 0xD
|
||||
|
||||
#define RX_PSEL_PBnPFS_CMPOB1 0x10
|
||||
|
||||
#define RX_PSEL_PBnPFS_TS18 0x19
|
||||
#define RX_PSEL_PBnPFS_TS19 0x19
|
||||
#define RX_PSEL_PBnPFS_TS20 0x19
|
||||
#define RX_PSEL_PBnPFS_TS21 0x19
|
||||
#define RX_PSEL_PBnPFS_TS22 0x19
|
||||
#define RX_PSEL_PBnPFS_TS23 0x19
|
||||
#define RX_PSEL_PBnPFS_TS24 0x19
|
||||
#define RX_PSEL_PBnPFS_TS25 0x19
|
||||
|
||||
/* PCnPFS */
|
||||
#define RX_PSEL_PCnPFS_MTIOC3A 0x01
|
||||
#define RX_PSEL_PCnPFS_MTIOC3B 0x01
|
||||
#define RX_PSEL_PCnPFS_MTIOC3C 0x01
|
||||
#define RX_PSEL_PCnPFS_MTIOC3D 0x01
|
||||
#define RX_PSEL_PCnPFS_MTIOC4B 0x01
|
||||
#define RX_PSEL_PCnPFS_MTIOC4D 0x01
|
||||
|
||||
#define RX_PSEL_PCnPFS_MTCLKA 0x02
|
||||
#define RX_PSEL_PCnPFS_MTCLKB 0x02
|
||||
#define RX_PSEL_PCnPFS_MTCLKC 0x02
|
||||
#define RX_PSEL_PCnPFS_MTCLKD 0x02
|
||||
|
||||
#define RX_PSEL_PCnPFS_TMCI1 0x5
|
||||
#define RX_PSEL_PCnPFS_TMO2 0x5
|
||||
#define RX_PSEL_PCnPFS_TMRI2 0x5
|
||||
#define RX_PSEL_PCnPFS_TMCI2 0x5
|
||||
|
||||
#define RX_PSEL_PCnPFS_POE0 0x7
|
||||
#define RX_PSEL_PCnPFS_CACREF 0x7
|
||||
|
||||
#define RX_PSEL_PCnPFS_RXD5 0xA
|
||||
#define RX_PSEL_PCnPFS_SMISO5 0xA
|
||||
#define RX_PSEL_PCnPFS_SSCL5 0xA
|
||||
#define RX_PSEL_PCnPFS_TXD5 0xA
|
||||
#define RX_PSEL_PCnPFS_SMOSI5 0xA
|
||||
#define RX_PSEL_PCnPFS_SSDA5 0xA
|
||||
#define RX_PSEL_PCnPFS_SCK5 0xA
|
||||
#define RX_PSEL_PCnPFS_RXD8 0xA
|
||||
#define RX_PSEL_PCnPFS_SMISO8 0xA
|
||||
#define RX_PSEL_PCnPFS_SSCL8 0xA
|
||||
#define RX_PSEL_PCnPFS_TXD8 0xA
|
||||
#define RX_PSEL_PCnPFS_SMOSI8 0xA
|
||||
#define RX_PSEL_PCnPFS_SSDA8 0xA
|
||||
#define RX_PSEL_PCnPFS_SCK8 0xA
|
||||
|
||||
#define RX_PSEL_PCnPFS_CTS5 0xB
|
||||
#define RX_PSEL_PCnPFS_RTS5 0xB
|
||||
#define RX_PSEL_PCnPFS_SS5 0xB
|
||||
#define RX_PSEL_PCnPFS_CTS8 0xB
|
||||
#define RX_PSEL_PCnPFS_RTS8 0xB
|
||||
#define RX_PSEL_PCnPFS_SS8 0xB
|
||||
|
||||
#define RX_PSEL_PCnPFS_SSLA0 0xD
|
||||
#define RX_PSEL_PCnPFS_SSLA1 0xD
|
||||
#define RX_PSEL_PCnPFS_SSLA2 0xD
|
||||
#define RX_PSEL_PCnPFS_SSLA3 0xD
|
||||
#define RX_PSEL_PCnPFS_RSPCKA 0xD
|
||||
#define RX_PSEL_PCnPFS_MOSIA 0xD
|
||||
#define RX_PSEL_PCnPFS_MISOA 0xD
|
||||
|
||||
#define RX_PSEL_PCnPFS_TS13 0x19
|
||||
#define RX_PSEL_PCnPFS_TS14 0x19
|
||||
#define RX_PSEL_PCnPFS_TS15 0x19
|
||||
#define RX_PSEL_PCnPFS_TS16 0x19
|
||||
#define RX_PSEL_PCnPFS_TS17 0x19
|
||||
#define RX_PSEL_PCnPFS_TSCAP 0x19
|
||||
|
||||
/* PDnPFS */
|
||||
#define RX_PSEL_PDnPFS_MTIOC4B 0x01
|
||||
#define RX_PSEL_PDnPFS_MTIOC4D 0x01
|
||||
#define RX_PSEL_PDnPFS_MTIOC5W 0x01
|
||||
#define RX_PSEL_PDnPFS_MTIOC5V 0x01
|
||||
#define RX_PSEL_PDnPFS_MTIOC5U 0x01
|
||||
|
||||
#define RX_PSEL_PDnPFS_POE0 0x7
|
||||
#define RX_PSEL_PDnPFS_POE1 0x7
|
||||
#define RX_PSEL_PDnPFS_POE2 0x7
|
||||
#define RX_PSEL_PDnPFS_POE3 0x7
|
||||
#define RX_PSEL_PDnPFS_POE8 0x7
|
||||
|
||||
#define RX_PSEL_PDnPFS_RXD6 0xB
|
||||
#define RX_PSEL_PDnPFS_SMISO6 0xB
|
||||
#define RX_PSEL_PDnPFS_SSCL6 0xB
|
||||
#define RX_PSEL_PDnPFS_TXD6 0xB
|
||||
#define RX_PSEL_PDnPFS_SMOSI6 0xB
|
||||
#define RX_PSEL_PDnPFS_SSDA6 0xB
|
||||
#define RX_PSEL_PDnPFS_SCK6 0xB
|
||||
|
||||
/* PEnPFS */
|
||||
#define RX_PSEL_PEnPFS_MTIOC4A 0x01
|
||||
#define RX_PSEL_PEnPFS_MTIOC4B 0x01
|
||||
#define RX_PSEL_PEnPFS_MTIOC4C 0x01
|
||||
#define RX_PSEL_PEnPFS_MTIOC4D 0x01
|
||||
|
||||
#define RX_PSEL_PEnPFS_MTIOC1A 0x02
|
||||
#define RX_PSEL_PEnPFS_MTIOC2B 0x02
|
||||
|
||||
#define RX_PSEL_PEnPFS_POE8 0x7
|
||||
|
||||
#define RX_PSEL_PEnPFS_CLKOUT 0x9
|
||||
|
||||
#define RX_PSEL_PEnPFS_RXD12 0xC
|
||||
#define RX_PSEL_PEnPFS_SMISO12 0xC
|
||||
#define RX_PSEL_PEnPFS_SSCL12 0xC
|
||||
#define RX_PSEL_PEnPFS_TXD12 0xC
|
||||
#define RX_PSEL_PEnPFS_SMOSI12 0xC
|
||||
#define RX_PSEL_PEnPFS_SSDA12 0xC
|
||||
#define RX_PSEL_PEnPFS_SCK12 0xC
|
||||
#define RX_PSEL_PEnPFS_TXDX12 0xC
|
||||
#define RX_PSEL_PEnPFS_RXDX12 0xC
|
||||
#define RX_PSEL_PEnPFS_SIOX12 0xC
|
||||
#define RX_PSEL_PEnPFS_CTS12 0xC
|
||||
#define RX_PSEL_PEnPFS_RTS12 0xC
|
||||
#define RX_PSEL_PEnPFS_SS12 0xC
|
||||
|
||||
#define RX_PSEL_PEnPFS_CMPOB0 0X10
|
||||
|
||||
#define RX_PSEL_PEnPFS_TS33 0X19
|
||||
#define RX_PSEL_PEnPFS_TS34 0x19
|
||||
#define RX_PSEL_PEnPFS_TS35 0x19
|
||||
|
||||
/* PHnPFS */
|
||||
#define RX_PSEL_PHnPFS_TMO0 0x05
|
||||
#define RX_PSEL_PHnPFS_TMRI0 0x05
|
||||
#define RX_PSEL_PHnPFS_TMCI0 0x05
|
||||
|
||||
#define RX_PSEL_PHnPFS_CACREF 0x7
|
||||
|
||||
#define RX_PSEL_PHnPFS_TS7 0x19
|
||||
#define RX_PSEL_PHnPFS_TS8 0x19
|
||||
#define RX_PSEL_PHnPFS_TS9 0x19
|
||||
#define RX_PSEL_PHnPFS_TS10 0x19
|
||||
|
||||
/* PJnPFS */
|
||||
#define RX_PSEL_PJnPFS_MTIOC3A 0x01
|
||||
#define RX_PSEL_PJnPFS_MTIOC3C 0x01
|
||||
|
||||
#define RX_PSEL_PJnPFS_CTS6 0xB
|
||||
#define RX_PSEL_PJnPFS_TTS6 0xB
|
||||
#define RX_PSEL_PJnPFS_SS6 0xB
|
||||
|
||||
#define RX_PSEL(psel, port_num, pin_num) \
|
||||
(psel << RX_PSEL_POS | pin_num << RX_PIN_NUM_POS | port_num << RX_PORT_NUM_POS)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SOC_RX_COMMON_H_ */
|
||||
|
|
@ -249,4 +249,14 @@ config HAS_RENESAS_RX_RDP
|
|||
|
||||
if HAS_RENESAS_RX_RDP
|
||||
|
||||
config USE_RX_RDP_MPC
|
||||
bool
|
||||
help
|
||||
Enable RX RDP MPC driver
|
||||
|
||||
config USE_RX_RDP_GPIO
|
||||
bool
|
||||
help
|
||||
Enable RX RDP MPC driver
|
||||
|
||||
endif # HAS_RENESAS_RX_RDP
|
||||
|
|
|
|||
85
soc/renesas/rx/include/pinctrl_soc.h
Normal file
85
soc/renesas/rx/include/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_RENESAS_RX_COMMON_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_RENESAS_RX_COMMON_PINCTRL_SOC_H_
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h>
|
||||
|
||||
#define PORT_POS (8)
|
||||
|
||||
#define PIN_MODE_GPIO (0)
|
||||
#define PIN_MODE_PERIPHERAL (1)
|
||||
|
||||
struct rx_pin_config {
|
||||
bool pin_mode;
|
||||
bool analog_enable;
|
||||
bool output_enable;
|
||||
bool output_high;
|
||||
bool bias_pull_up;
|
||||
bool drive_open_drain;
|
||||
uint8_t drive_strength;
|
||||
uint8_t psels;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Type to hold a renesas ra pin's pinctrl configuration.
|
||||
*/
|
||||
struct rx_pinctrl_soc_pin {
|
||||
/** Port number 0..5, A..E, H, J */
|
||||
uint32_t port_num: 5;
|
||||
/** Pin number 0..7 */
|
||||
uint32_t pin_num: 4;
|
||||
/** config pin */
|
||||
struct rx_pin_config cfg;
|
||||
};
|
||||
|
||||
typedef struct rx_pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name.
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
{ \
|
||||
.port_num = RX_GET_PORT_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||
.pin_num = RX_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||
.cfg = \
|
||||
{ \
|
||||
.pin_mode = PIN_MODE_PERIPHERAL, \
|
||||
.analog_enable = DT_PROP(node_id, renesas_analog_enable), \
|
||||
.output_enable = DT_PROP(node_id, output_enable), \
|
||||
.output_high = DT_PROP(node_id, output_high), \
|
||||
.bias_pull_up = DT_PROP(node_id, bias_pull_up), \
|
||||
.drive_open_drain = DT_PROP(node_id, drive_open_drain), \
|
||||
.drive_strength = DT_ENUM_IDX(node_id, drive_strength), \
|
||||
.psels = RX_GET_PSEL(DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||
}, \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, psels, \
|
||||
Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
#define RX_GET_PORT_NUM(pinctrl) (((pinctrl) >> RX_PORT_NUM_POS) & RX_PORT_NUM_MASK)
|
||||
#define RX_GET_PIN_NUM(pinctrl) (((pinctrl) >> RX_PIN_NUM_POS) & RX_PIN_NUM_MASK)
|
||||
|
||||
#define RX_GET_PSEL(pinctrl) (((pinctrl) >> RX_PSEL_POS) & RX_PSEL_MASK)
|
||||
|
||||
#endif /* ZEPHYR_SOC_RENESAS_RX_COMMON_PINCTRL_SOC_H_ */
|
||||
Loading…
Add table
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Reference in a new issue