dts: arm: renesas: ra4: Use renesas,ra-pinctrl-pfs driver
Switch the pinctrl driver to renesas,ra-pinctrl-pfs which can be used with FSP. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
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af2021ea4c
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397c48a13e
4 changed files with 31 additions and 14 deletions
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@ -144,7 +144,7 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
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const enum gpio_int_trig trig = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1);
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const struct gpio_ra_config *config = dev->config;
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struct gpio_ra_data *data = dev->data;
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struct pinctrl_ra_pin pincfg = {0};
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struct ra_pinctrl_soc_pin pincfg = {0};
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if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
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/* Pin cannot be configured as input and output */
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@ -155,25 +155,25 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
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}
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if (flags & GPIO_OUTPUT) {
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pincfg.config |= BIT(PmnPFS_PDR_POS);
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pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos);
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}
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if (flags & GPIO_PULL_UP) {
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pincfg.config |= BIT(PmnPFS_PCR_POS);
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pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos);
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}
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if ((flags & GPIO_SINGLE_ENDED) && (flags & GPIO_LINE_OPEN_DRAIN)) {
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pincfg.config |= BIT(PmnPFS_NCODR_POS);
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pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos);
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}
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if (flags & GPIO_INT_ENABLE) {
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pincfg.config |= BIT(PmnPFS_ISEL_POS);
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pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos);
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}
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pincfg.config &= ~BIT(PmnPFS_PMR_POS);
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pincfg.cfg &= ~BIT(R_PFS_PORT_PIN_PmnPFS_PMR_Pos);
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pincfg.pin = pin;
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pincfg.port = config->port;
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pincfg.pin_num = pin;
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pincfg.port_num = config->port;
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if (flags & GPIO_INT_ENABLE) {
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const struct gpio_ra_irq_info *irq_info;
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@ -230,7 +230,7 @@ static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio
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{
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const struct gpio_ra_config *config = dev->config;
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const struct gpio_ra_irq_info *irq_info;
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struct pinctrl_ra_pin pincfg;
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struct ra_pinctrl_soc_pin pincfg;
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ra_isr_handler cb;
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const void *cbarg;
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uint32_t intcfg;
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@ -239,22 +239,22 @@ static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio
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memset(flags, 0, sizeof(gpio_flags_t));
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err = pinctrl_ra_query_config(config->port, pin, &pincfg);
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err = ra_pinctrl_query_config(config->port, pin, &pincfg);
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if (err < 0) {
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return err;
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}
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if (pincfg.config & BIT(PmnPFS_PDR_POS)) {
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if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos)) {
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*flags |= GPIO_OUTPUT;
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} else {
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*flags |= GPIO_INPUT;
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}
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if (pincfg.config & BIT(PmnPFS_ISEL_POS)) {
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if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos)) {
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*flags |= GPIO_INT_ENABLE;
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}
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if (pincfg.config & BIT(PmnPFS_PCR_POS)) {
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if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos)) {
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*flags |= GPIO_PULL_UP;
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}
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@ -26,3 +26,16 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
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return 0;
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}
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int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg)
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{
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if (port >= RA_PINCTRL_PORT_NUM || pin >= RA_PINCTRL_PIN_NUM) {
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return -EINVAL;
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}
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pincfg->port_num = port;
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pincfg->pin_num = pin;
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pincfg->cfg = R_PFS->PORT[port].PIN[pin].PmnPFS;
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return 0;
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}
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@ -240,7 +240,7 @@
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};
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pinctrl: pinctrl@40040800 {
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compatible = "renesas,ra-pinctrl";
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compatible = "renesas,ra-pinctrl-pfs";
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reg = <0x40040800 0x500 0x40040d03 0x1>;
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reg-names = "pfs", "pmisc_pwpr";
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status = "okay";
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@ -12,6 +12,8 @@
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
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#define RA_PINCTRL_PORT_NUM ARRAY_SIZE(((R_PFS_Type *)0)->PORT)
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#define RA_PINCTRL_PIN_NUM ARRAY_SIZE(((R_PFS_PORT_Type *)0)->PIN)
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/**
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* @brief Type to hold a renesas ra pin's pinctrl configuration.
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*/
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@ -26,6 +28,8 @@ struct ra_pinctrl_soc_pin {
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typedef struct ra_pinctrl_soc_pin pinctrl_soc_pin_t;
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int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg);
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/**
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* @brief Utility macro to initialize each pin.
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*
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