soc: renesas: Add support for Renesas RZ/G3S
This adds minimal support for a new SoC Renesas RZ/G3S Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com> Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
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13 changed files with 189 additions and 0 deletions
37
dts/arm/renesas/rz/rzg/r9a08g045.dtsi
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37
dts/arm/renesas/rz/rzg/r9a08g045.dtsi
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/*
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* Copyright (c) 2024 EPAM Systems
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <mem.h>
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/ {
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compatible = "renesas,r9a08g045";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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clock-frequency = <250000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <7>;
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};
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@ -8,6 +8,11 @@ config HAS_RENESAS_RA_FSP
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help
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Enable Renesas RA FSP support
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config HAS_RENESAS_RZ_FSP
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bool
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help
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Enable Renesas RZ FSP support
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if HAS_RENESAS_RA_FSP
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config USE_RA_FSP_SCI_B_UART
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4
soc/renesas/rz/CMakeLists.txt
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4
soc/renesas/rz/CMakeLists.txt
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(${SOC_SERIES})
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8
soc/renesas/rz/Kconfig
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8
soc/renesas/rz/Kconfig
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_RENESAS_RZ
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rsource "*/Kconfig"
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endif # SOC_FAMILY_RENESAS_RZ
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8
soc/renesas/rz/Kconfig.defconfig
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8
soc/renesas/rz/Kconfig.defconfig
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_RENESAS_RZ
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rsource "*/Kconfig.defconfig"
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endif # SOC_FAMILY_RENESAS_RZ
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10
soc/renesas/rz/Kconfig.soc
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10
soc/renesas/rz/Kconfig.soc
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_RENESAS_RZ
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bool
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config SOC_FAMILY
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default "renesas_rz" if SOC_FAMILY_RENESAS_RZ
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rsource "*/Kconfig.soc"
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8
soc/renesas/rz/rzg3s/CMakeLists.txt
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8
soc/renesas/rz/rzg3s/CMakeLists.txt
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(soc.c)
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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11
soc/renesas/rz/rzg3s/Kconfig
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soc/renesas/rz/rzg3s/Kconfig
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# Copyright (c) 2024 EPAM Systems
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RZG3S
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select ARM
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select HAS_RENESAS_RZ_FSP
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select CPU_CORTEX_M_HAS_DWT
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select SOC_EARLY_INIT_HOOK
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29
soc/renesas/rz/rzg3s/Kconfig.defconfig
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soc/renesas/rz/rzg3s/Kconfig.defconfig
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# Copyright (c) 2024 EPAM Systems
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RZG3S
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config NUM_IRQS
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default 480
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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config FLASH_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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config SYS_CLOCK_EXISTS
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default y
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# This is required to support debug with xSPI boot when Zephyr already booted by TF-A
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config INIT_ARCH_HW_AT_BOOT
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default y
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config BUILD_OUTPUT_S19
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default y
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endif # SOC_SERIES_RZG3S
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24
soc/renesas/rz/rzg3s/Kconfig.soc
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24
soc/renesas/rz/rzg3s/Kconfig.soc
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RZG3S
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bool
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select SOC_FAMILY_RENESAS_RZ
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help
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Renesas RZ/G3S series
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config SOC_SERIES
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default "rzg3s" if SOC_SERIES_RZG3S
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config SOC_R9A08G045S33GBG
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bool
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select SOC_SERIES_RZG3S
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help
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R9A08G045S33GBG
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config SOC_R9A08G045S33GBG_CM33
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bool
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select SOC_R9A08G045S33GBG
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config SOC
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default "r9a08g045s33gbg" if SOC_R9A08G045S33GBG
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25
soc/renesas/rz/rzg3s/soc.c
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25
soc/renesas/rz/rzg3s/soc.c
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Renesas RZ/G3S Group
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*/
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#include <zephyr/init.h>
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#include <bsp_api.h>
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/* System core clock is set to 250 MHz by IPL of A55 */
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uint32_t SystemCoreClock = 250000000;
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void soc_early_init_hook(void)
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{
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bsp_clock_init();
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/* This delay is required to wait for the A55 to complete its setting first before */
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/* UART initialization of M33 */
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R_BSP_SoftwareDelay(CONFIG_UART_RENESAS_RZG_INIT_DELAY_MS, BSP_DELAY_UNITS_MILLISECONDS);
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}
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soc/renesas/rz/rzg3s/soc.h
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12
soc/renesas/rz/rzg3s/soc.h
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_
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#include <bsp_api.h>
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#endif /* ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ */
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8
soc/renesas/rz/soc.yml
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8
soc/renesas/rz/soc.yml
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family:
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- name: renesas_rz
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series:
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- name: rzg3s
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socs:
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- name: r9a08g045s33gbg
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cpuclusters:
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- name: cm33
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