dts: arm: renesas: ra: Add support for Renesas RA4E1 soc
Add support for r7fa4e10d2cfm, r7fa4e10d2cne soc Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
This commit is contained in:
parent
430c440416
commit
305ae84457
12 changed files with 561 additions and 0 deletions
32
dts/arm/renesas/ra/ra4/r7fa4e10d2cfm.dtsi
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32
dts/arm/renesas/ra/ra4/r7fa4e10d2cfm.dtsi
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@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <arm/renesas/ra/ra4/r7fa4e10x.dtsi>
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/ {
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soc {
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flash-controller@407e0000 {
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block-32kb-linear-end = <21>;
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flash0: flash@0 {
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compatible = "renesas,ra-nv-flash";
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reg = <0x0 DT_SIZE_K(512)>;
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write-block-size = <128>;
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erase-block-size = <8192>;
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renesas,programming-enable;
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};
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flash1: flash@8000000 {
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compatible = "renesas,ra-nv-flash";
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reg = <0x8000000 DT_SIZE_K(8)>;
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write-block-size = <4>;
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erase-block-size = <64>;
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renesas,programming-enable;
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};
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};
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};
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};
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32
dts/arm/renesas/ra/ra4/r7fa4e10d2cne.dtsi
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32
dts/arm/renesas/ra/ra4/r7fa4e10d2cne.dtsi
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@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <arm/renesas/ra/ra4/r7fa4e10x.dtsi>
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/ {
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soc {
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flash-controller@407e0000 {
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block-32kb-linear-end = <21>;
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flash0: flash@0 {
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compatible = "renesas,ra-nv-flash";
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reg = <0x0 DT_SIZE_K(512)>;
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write-block-size = <128>;
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erase-block-size = <8192>;
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renesas,programming-enable;
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};
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flash1: flash@8000000 {
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compatible = "renesas,ra-nv-flash";
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reg = <0x8000000 DT_SIZE_K(8)>;
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write-block-size = <4>;
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erase-block-size = <64>;
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renesas,programming-enable;
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};
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};
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};
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};
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261
dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi
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261
dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <zephyr/dt-bindings/pwm/ra_pwm.h>
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/delete-node/ &spi1;
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/delete-node/ &agt4;
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/delete-node/ &adc1;
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/delete-node/ &iic1;
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/ {
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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sci3: sci3@40118300 {
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compatible = "renesas,ra-sci";
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reg = <0x40118300 0x100>;
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clocks = <&pclka MSTPB 28>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <3>;
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status = "disabled";
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};
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};
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sci4: sci4@40118400 {
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compatible = "renesas,ra-sci";
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reg = <0x40118400 0x100>;
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clocks = <&pclka MSTPB 27>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <4>;
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status = "disabled";
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};
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};
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adc@40170000 {
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channel-count = <9>;
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channel-available-mask = <0x1381f>;
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};
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pwm2: pwm2@40169200 {
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compatible = "renesas,ra-pwm";
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divider = <RA_PWM_SOURCE_DIV_1>;
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channel = <RA_PWM_CHANNEL_2>;
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clocks = <&pclkd MSTPE 29>;
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reg = <0x40169200 0x100>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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trng: trng {
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compatible = "renesas,ra-sce9-rng";
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status = "disabled";
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};
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};
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clocks: clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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xtal: clock-main-osc {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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clocks = <&hoco>;
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div = <2>;
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mul = <20 0>;
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status = "disabled";
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};
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pll2: pll2 {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL2 */
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div = <2>;
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mul = <20 0>;
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status = "disabled";
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};
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pclkblock: pclkblock@40084000 {
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compatible = "renesas,ra-cgc-pclk-block";
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reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
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<0x4008400c 4>, <0x40084010 4>;
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reg-names = "MSTPA", "MSTPB", "MSTPC",
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"MSTPD", "MSTPE";
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#clock-cells = <0>;
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clocks = <&pll>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <100000000>;
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};
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&ioport0 {
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port-irqs = <&port_irq6 &port_irq7 &port_irq8
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&port_irq9 &port_irq13>;
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port-irq-names = "port-irq6",
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"port-irq7",
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"port-irq8",
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"port-irq9",
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"port-irq13";
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port-irq6-pins = <0>;
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port-irq7-pins = <1>;
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port-irq8-pins = <2>;
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port-irq9-pins = <4>;
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port-irq13-pins = <15>;
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};
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&ioport1 {
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port-irqs = <&port_irq0 &port_irq1 &port_irq2
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&port_irq3 &port_irq4>;
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port-irq-names = "port-irq0",
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"port-irq1",
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"port-irq2",
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"port-irq3",
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"port-irq4";
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port-irq0-pins = <5>;
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port-irq1-pins = <1 4>;
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port-irq2-pins = <0>;
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port-irq3-pins = <10>;
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port-irq4-pins = <11>;
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};
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&ioport2 {
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port-irqs = <&port_irq0 &port_irq1 &port_irq2
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&port_irq3>;
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port-irq-names = "port-irq0",
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"port-irq1",
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"port-irq2",
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"port-irq3";
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port-irq0-pins = <6>;
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port-irq1-pins = <5>;
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port-irq2-pins = <13>;
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port-irq3-pins = <12>;
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};
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&ioport3 {
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port-irqs = <&port_irq5 &port_irq6 &port_irq9>;
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port-irq-names = "port-irq5",
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"port-irq6",
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"port-irq9";
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port-irq5-pins = <2>;
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port-irq6-pins = <1>;
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port-irq9-pins = <4>;
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};
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&ioport4 {
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port-irqs = <&port_irq0 &port_irq4 &port_irq5
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&port_irq6 &port_irq7>;
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port-irq-names = "port-irq0",
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"port-irq4",
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"port-irq5",
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"port-irq6",
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"port-irq7";
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port-irq0-pins = <0>;
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port-irq4-pins = <2 11>;
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port-irq5-pins = <1 10>;
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port-irq6-pins = <9>;
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port-irq7-pins = <8>;
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};
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@ -8,6 +8,10 @@ compatible: "renesas,ra-cgc-pclk"
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include: [clock-controller.yaml, base.yaml]
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properties:
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clock-frequency:
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type: int
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description: clock frequency (Hz)
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div:
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type: int
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required: true
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12
soc/renesas/ra/ra4e1/CMakeLists.txt
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12
soc/renesas/ra/ra4e1/CMakeLists.txt
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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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16
soc/renesas/ra/ra4e1/Kconfig
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16
soc/renesas/ra/ra4e1/Kconfig
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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA4E1
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select ARM
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select CPU_HAS_ARM_MPU
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select CPU_CORTEX_M33
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select HAS_RENESAS_RA_FSP
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select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
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select CPU_CORTEX_M_HAS_DWT
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select ARMV8_M_DSP
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select CPU_HAS_FPU
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select FPU
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select HAS_SWO
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select XIP
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select SOC_EARLY_INIT_HOOK
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24
soc/renesas/ra/ra4e1/Kconfig.defconfig
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24
soc/renesas/ra/ra4e1/Kconfig.defconfig
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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA4E1
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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# Set to the minimal size of data which can be written.
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config FLASH_FILL_BUFFER_SIZE
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default 128
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endif # SOC_SERIES_RA4E1
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27
soc/renesas/ra/ra4e1/Kconfig.soc
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27
soc/renesas/ra/ra4e1/Kconfig.soc
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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA4E1
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA4E1 series
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config SOC_R7FA4E10D2CFM
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bool
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select SOC_SERIES_RA4E1
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help
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R7FA4E10D2CFM
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config SOC_R7FA4E10D2CNE
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bool
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select SOC_SERIES_RA4E1
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help
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R7FA4E10D2CNE
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config SOC_SERIES
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default "ra4e1" if SOC_SERIES_RA4E1
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config SOC
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default "r7fa4e10d2cfm" if SOC_R7FA4E10D2CFM
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default "r7fa4e10d2cne" if SOC_R7FA4E10D2CNE
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71
soc/renesas/ra/ra4e1/sections.ld
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71
soc/renesas/ra/ra4e1/sections.ld
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
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{
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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*(.fsp_dtc_vector_table)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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SECTION_PROLOGUE(.option_setting_ofs,,)
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{
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__OPTION_SETTING_OFS_Start = .;
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KEEP(*(.option_setting_ofs0))
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. = __OPTION_SETTING_OFS_Start + 0x04;
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KEEP(*(.option_setting_ofs2))
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. = __OPTION_SETTING_OFS_Start + 0x10;
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KEEP(*(.option_setting_dualsel))
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__OPTION_SETTING_OFS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
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SECTION_PROLOGUE(.option_setting_sas,,)
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{
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__OPTION_SETTING_SAS_Start = .;
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KEEP(*(.option_setting_sas))
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__OPTION_SETTING_SAS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
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SECTION_PROLOGUE(.option_setting_s,,)
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{
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__OPTION_SETTING_S_Start = .;
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KEEP(*(.option_setting_ofs1_sec))
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. = __OPTION_SETTING_S_Start + 0x04;
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KEEP(*(.option_setting_ofs3_sec))
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. = __OPTION_SETTING_S_Start + 0x10;
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KEEP(*(.option_setting_banksel_sec))
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. = __OPTION_SETTING_S_Start + 0x40;
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KEEP(*(.option_setting_bps_sec0))
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. = __OPTION_SETTING_S_Start + 0x44;
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KEEP(*(.option_setting_bps_sec1))
|
||||
. = __OPTION_SETTING_S_Start + 0x48;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = __OPTION_SETTING_S_Start + 0x4C;
|
||||
KEEP(*(.option_setting_bps_sec3))
|
||||
. = __OPTION_SETTING_S_Start + 0x60;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = __OPTION_SETTING_S_Start + 0x64;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = __OPTION_SETTING_S_Start + 0x68;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = __OPTION_SETTING_S_Start + 0x6C;
|
||||
KEEP(*(.option_setting_pbps_sec3))
|
||||
. = __OPTION_SETTING_S_Start + 0x80;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0x84;
|
||||
KEEP(*(.option_setting_ofs3_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0x90;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0xC0;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = __OPTION_SETTING_S_Start + 0xC4;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = __OPTION_SETTING_S_Start + 0xC8;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
. = __OPTION_SETTING_S_Start + 0xCC;
|
||||
KEEP(*(.option_setting_bps_sel3))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
|
62
soc/renesas/ra/ra4e1/soc.c
Normal file
62
soc/renesas/ra/ra4e1/soc.c
Normal file
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Renesas RA4E1 family processor
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/arch/cpu.h>
|
||||
#include <cmsis_core.h>
|
||||
#include <zephyr/arch/arm/nmi.h>
|
||||
#include <zephyr/irq.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
#include "bsp_cfg.h"
|
||||
#include <bsp_api.h>
|
||||
|
||||
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
|
||||
|
||||
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
|
||||
|
||||
/**
|
||||
* @brief Perform basic hardware initialization at boot.
|
||||
*
|
||||
* This needs to be run from the very beginning.
|
||||
*/
|
||||
void soc_early_init_hook(void)
|
||||
{
|
||||
extern volatile uint16_t g_protect_counters[];
|
||||
|
||||
for (uint32_t i = 0; i < 4; i++) {
|
||||
g_protect_counters[i] = 0;
|
||||
}
|
||||
|
||||
#if FSP_PRIV_TZ_USE_SECURE_REGS
|
||||
/* Disable protection using PRCR register. */
|
||||
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
|
||||
|
||||
/* Initialize peripherals to secure mode for flat projects */
|
||||
R_PSCU->PSARB = 0;
|
||||
R_PSCU->PSARC = 0;
|
||||
R_PSCU->PSARD = 0;
|
||||
R_PSCU->PSARE = 0;
|
||||
|
||||
R_CPSCU->ICUSARG = 0;
|
||||
R_CPSCU->ICUSARH = 0;
|
||||
R_CPSCU->ICUSARI = 0;
|
||||
|
||||
/* Enable protection using PRCR register. */
|
||||
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
|
||||
#endif
|
||||
|
||||
SystemCoreClock = BSP_MOCO_HZ;
|
||||
g_protect_pfswe_counter = 0;
|
||||
}
|
16
soc/renesas/ra/ra4e1/soc.h
Normal file
16
soc/renesas/ra/ra4e1/soc.h
Normal file
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Renesas RA4E1 family MCU
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_
|
||||
#define ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_
|
||||
|
||||
#include <bsp_api.h>
|
||||
|
||||
#endif /* ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_ */
|
|
@ -4,6 +4,10 @@ family:
|
|||
- name: ra2a1
|
||||
socs:
|
||||
- name: r7fa2a1ab3cfm
|
||||
- name: ra4e1
|
||||
socs:
|
||||
- name: r7fa4e10d2cfm
|
||||
- name: r7fa4e10d2cne
|
||||
- name: ra4e2
|
||||
socs:
|
||||
- name: r7fa4e2b93cfm
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue