This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
This commit changes the I2C instance to IOM.
IOM instance can be I2C or SPI. The choice of either
using I2C or SPI should be made in board DTS.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
/delete-node/ pointing at node labels needs to be out of the the tree
hierarchy, fixes the error:
devicetree error: zephyr/dts/arm/nordic/nrf52840_qfaa.dtsi:24 (column
16): parse error: expected node name
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This adds QSPI controller properties that allow tuning
chip select timings (needed for accessing QSPI at high speed)
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
RC32K/RCX/XTAL32K were present in device tree as fixed-clock.
Now calibration time for RCX and RC32K is added and settle time
for XTAL32K so additional binding is created.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
To better delimit renesas ranges dts, we need to use ranges folder.
It will also help maintainers to better delimit their files to
be notified about.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Since VWGPSM (Virtual Wire GPIO Target-to-Controller) registers are
introduced in npcx9 and later series, the CL moves the related DT nodes
from npcx-espi-vws-map.dtsi (Used for all npcx series) to the specific
dtsi files for npcx9 and npcx4 series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Rename the base device-tree for the AM62x M4F from a SK EVM specific
to a more generic name since this DT describes the M4F subsystem in
the AM62x SoC.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The existing i2c sda/slc pinctrl nodes serve as an input and output
for the USIC. This limits the number of pins that can be used for i2c
since the pin must be internally connected to both DOUT0 and DX0 signals
on the USIC (for the sda signal for example).
It is also possible to use separate pins to DOUT0 and DX0, but connect
the pins externally. Add these extra pinctrl nodes and document their
use in infineon,xmc4xxx-i2c.yaml.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In commit 541482ff20 the pinctrl alternate
function mask was increased to also include open-drain setting.
Revert this change because open-drain can already be set via property
drive-open-drain.
The commit also added separate pinctrl nodes for the i2c controller and
target modes. However, the alternate function settings
is the same in both modes, so keep only one and remove the mode
label.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Since the pwm_nrf_sw driver can now be used on all nRF SoCs, add its
corresponding DT node in the common file included by all those SoCs.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Rename the STM32H7 FDCAN node labels to match to naming used in the ST
reference manuals. This also matches the naming used in the STM32H7 FDCAN
clock and pinctrl macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 FDCAN node labels to match to naming used in the ST
reference manuals. This also matches the naming used in the STM32 FDCAN
pinctrl macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 bxCAN driver DTS compatible, Kconfig symbol, and
implementation file to match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add ipm driver to use Inter Processor Interrupts
on Xilinx ZynqMP platform. This patch also adds sample
application that shows use of xlnx ipm driver.
This driver uses default arm gic interrupt controller
and works only for lockstep mode of cortex-r5f
cluster for now.
In split mode the cortex-r5 cluster will
have two r5f cores and they are expected to work in AMP
mode. If both r5f cores run simultaneouly, only one of
the core is able to receive IPI interrupts at this time
and it will be the one that started later. In future
this limitation shall be removed.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
This change introduces a new PWM driver for all CC13/26xx SoC.
See the documentation in ti,cc13xx-cc26xx-timer-pwm.yaml for detailed
usage instructions.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Enable CANFD for rt11xx by including nxp,flexcan-fd
compatibility for all CANFD capable CAN with associated
properties.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
This commit instantiates the counter peripheral.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Make ethernet phys childs of the mdio device and move the mdio device up
a level on the tree. That makes the device hierarchy coherent with the
required initialization priority and allows keeping the sequence in
check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Devicetree specification v0.4, Section 2.3.1:
"The compatible string should consist only of lowercase letters, digits
and dashes, and should start with a letter."
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This state is never used in practice, even if handled by the PM
subsystem hooks. Shutdown-like states are always invoked manually, so
they don't need to be described in DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The `cpu-power-states` property needs to be defined at SoC dts files,
since it's a property of the SoC, not board.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
CPU idle states are not board specific. This patch moves Nuvoton idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves NXP idle states
to the core SoC dts files. Board can always tweak some state parameters
(if needed), but the definition belongs to core SoC dts files, same as
e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves Microchip MEC
idle states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves TI idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves STM32 idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Fixup support for DCS_LONG_WRITE command in DSI MCUX 2L driver. Since long
DCS commands may benefit from nonblocking I/O, add support for non blocking
transfers to the DSI driver.
This commit also corrects the interrupt number for the RT595, which uses
the DSI_MCUX_2L IP block.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Add Nuvoton numaker series flash memory controller(FMC) with erase,
read & write features of soc-flash. Also update Nuvoton manifest
to include zephyrproject-rtos/hal_nuvoton#6.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add the new RCC bindings to the dtsi files.
STM32F373 uses the RCC F1 bindings because the ADC prescaler is the same
on the two series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Current erroneous usages of dma-channels prop by lpc-dma nodes:
* dma-channels devicetree property should describe the number of
channels supported by the dma controller, not the number of channels
in use.
* LPC55SXX and RTXXX SOCs should be setting dma channels prop at SOC
level, not board level, since it is an SOC property, not a board
property.
* lpc55s28 has 23 channels for dma0, not 20.
* lpc55s28 has 10 channels for dma1, not 0.
* lpc55s69 has 23 channels for dma0, not 20.
* rt5xx has 37 channels for dma1, not 0.
* rt6xx has 33 channels for dma0, not 20.
* rt6xx has 33 channels for dma1, not 0.
Fix all of these issues
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Set the DMA number of otrigs DT property at the SOC level instead of the
board DTS because it is an SOC property and does not change on different
boards.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add basic device tree description fro stm32wba soc series.
This includes Flash/RAM clocks and clock control nodes
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
This change introduces the "_rtc_timer" suffix for the system tick timer
driver "compatible" property and aligns naming conventions with the
actual CC13/26xx SoC series product policy.
This frees up the "_rtc" namespace to introduce additional APIs based on
the same peripheral in the future (not part of this PR):
rtc: rtc@... {
compatible = "ti,cc13xx-cc26xx-rtc";
...
timer {
compatible = "ti,cc13xx-cc26xx-rtc-timer";
...
};
counter {
compatible = "ti,cc13xx-cc26xx-rtc-counter";
...
};
pps {
compatible = "ti,cc13xx-cc26xx-rtc-pps";
...
};
};
Or alternatively an MFD pattern with similar requirements.
Fixing the namespacing now makes sense standalone as it reduces the
chance of custom drivers being broken in the future.
Redundant extension of the mandatory system clock devicetree node is
replaced with a single `status = "okay"` which seems to be the more
sensible default to avoid user error when defining custom boards.
Knowledgeable users can still override this if really needed.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
The different references manuals of the STM32H7 family (RM099, RM0433,
RM0445 and RM0468) states that SDMMC2RTS and STMMC2EN are on bit 9 of
respectively RCC_AHB2RSTR and RCC_AHB2ENR (not on bit 8). Fixes the stm32h7
dts accordingly.
Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.
Use the board's debug connector (P6 / LPUART2) as default console.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Support pin control for NXP S32K3 devices and enable it by default on
mr_canhubk3 board configuration.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add Nuvoton numaker series UART support, including interrupt-driven,
also apply pinctrl and clock-control.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add Nuvoton numaker series clock controller support, including:
1. Do system clock initialization in z_arm_platform_init().
2. Support peripheral clock control API equivalent to BSP
CLK_EnableModuleClock()/CLK_SetModuleClock().
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move dt files related to SoC family and series to npcx folder. It only
leaves SoC dt file in `dts/arm/nuvoton folder` in case of confusion with
the other Nuvoton SoCs.
The dt files path will be:
dts/arm/nuvoton
|--npcx
| |--npcx7
| | |--npcx7-miwus-wui-map.dtsi
| | |--npcx7-alts-map.dtsi
| | |--.....
| +--npcx9
| | |--npcx9-miwus-wui-map.dtsi
| | |--npcx9-alts-map.dtsi
| | +--.....
| |--npcx-miwus-wui-map.dtsi
| |--npcx-alts-map.dtsi
| |--npcx.dtsi
| |--npcx7.dtsi
| |--npcx9.dtsi
|--npcx7m6fb.dtsi
|--npcx7m6fc.dtsi
|--npcx9m8f.dtsi
+--npcx9m3f.dtsi
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Move the two UART nodes so that they are under "soc" rather than "espi",
leave only xec-espi-host-dev nodes there.
The UART device can be used indepdently by the driver uart_mchp_xec.c
and it's normally initialized before before the espi one.
Moving the device node up a level so this does not trigger a false
positive on the build time priority checking.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Restructure the Bosch M_CAN driver backend to use per-instance Message RAM
configuration.
This removes the need for a common, artificial "can" devicetree node for
SoCs with multiple Bosch M_CAN-based CAN controllers and allows for
per-instance configuration of the number of e.g. standard (11-bit) and
extended (29-bit) filter elements.
As part of the restructure, software handling of CAN filter flags was moved
from per-flags bitfields to per-filter bitfields, solving an issue when
using more than 32 standard (11-bit) filter elements or more than 16
extended (29-bit) filter elements.
Fixes: #42030, #53417
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Switch the Bosch M_CAN devicetree binding to use a bosch,mram-cfg property
for specifying the memory layout of the Bosch M_CAN Message RAM. This is
identical to the Linux kernel devicetree binding for Bosch M_CAN IP core
based CAN controllers.
This introduces an offset cell which can be used for controllers with
shared Message RAM between Bosch M_CAN instances.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added Input/Output trigger mux address's as properties
that can be passed into the DMA driver. This is intended
to send INPUTMUX signals into the DMA.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Flash address is updated to 0x16000000, i.e. actual location instead of
remapped one. FLASH_BASE_ADDRESS is now set via dts.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
This selects default flash controller in device tree.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
This adds support for the USB interface for the
Renesas Smartbond DA1469x device family.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
RT1040 removes LPSPI3, and refers to the peripheral called LPSPI4 on
other RT devices as LPSPI3. Remove the default LPSPI3 peripheral and add
an `lpspi3` alias to LPSPI4.
Fixes#57942
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add missing USB-OTG control nodes. Like other STM32-platforms it's
disabled by default and uses the internal 48 MHz clock by default.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Update the default Flash and SRAM size to 1024kb and 288kb, Update the
mpn file overrides accordingly
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
cpu@0 node is not supported on some mpn's so it should be deleted from
the mpn files and not the package files.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
- Remove the spi node from an older commit since its replaced with the
SCB node now
- GPIO nodes should have been part of pinctrl
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Add new vref node to the DTS definitions of supported SoCs.
Extend DTS ADC channel properties where missing.
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
Introduce DesignWare ARC Data Fusion IP Subsystem(DFSS) SPI
driver for ARC boards, i.e. EMSDP, which uses DW SPI to controll
SPI-Flash and DFSS SPI to connect external devices. Both drivers
share most source code, but DFSS uses ARC auxiliary registers.
Move FIFO depth setting to device tree.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Add support board Pandora_STM32L475;
Drives that have been verified at present:
- GPIO
- PWM
- QSPI_FLASH_W25Q128
Signed-off-by: Tianshuang Ke <qinyun575@gmail.com>
Renesas Renesas SmartBond(tm) have two ADC blocks:
GPADC and SDADC.
This change adds drivers for both.
Each ADC supports only one channel setup, drivers allow
to have multiply channels in sequence. Switching
between ADC sources in done in software.
GPADC has 10 bit resolution (accuracy can be increase
with oversampling). Values up to 3.6V can be measured
on selected pins. V30 and VBAT1 can also be measured.
SDADC has 14 bit resolution and can take measurements
from 8 pins (single of differential) and VBAT.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
- The boards\arm\cy8cproto_063_ble board now has ADC enabled
- This includes overlay files for the test app and sample app
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Convert the NPCX keyboard scan driver to the input subsystem and add the
input to kscan compatibility driver to maintain functionality with the
current API.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add RT1040 SOC devicetree. This devicetree removes IP blocks absent on
the RT1040, and configures clock dividers correctly for the RT1040's
clock tree
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix PINT base address for LPC51xxx and 54xxx. These addresses were
incorrectly copied from the LPC55S69, which utilizes trustzone. Add the
relevant base address offset to the addresses.
Fixes#57334
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update LTDC driver to use LCDIF bindings, to simplify bindings
between LCD interface controller IP blocks.
Boards supporting the LTDC are also updated to use the properties as
declared by the new lcd controller binding
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Let the Bosch M_CAN front-end drivers supply their own register read/write
functions.
This is preparation for handling non-standard Bosch M_CAN register layouts
directly in the front-end and for accessing Bosch M_CAN IP cores over
peripheral busses.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Currently, the usb_dc_dw driver is not enabled for any platform.
Allow to build the driver for cyclonev_socdk. Subsequent patches
will allow the driver to be used on additional platforms.
Enable USB device controller and use use new snps,dwc2 compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Declare SCB nodes to be used as UART/SPI/I2C by the boards, Move
common declarations from psoc6_02 to the parent dtsi file
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
As recommended in AN4760 the memory region where the QSPI flash can be
memory mapped should be configured to be Strongly ordered memory. This
works around an issue where a speculative read from the CPU may cause
later problems with using the QSPI bus.
This avoids #57466.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
- Added initial version of Infineon CAT1 Flash driver
- Added binding file for infineon,cat1-flash-controller.yaml
- Added overlays for subsys/nvs and drivers/flash_shell
to support cy8cproto_063_ble, cy8cproto_062_4343w boards
- Defined erase-block-size in PSoC6 MPN dtsi.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Updated the code to to invoke reset using PCR block
z_mchp_xec_pcr_periph_reset() instead of resetting
using I2C Configuration register
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The SERCOM4 is hardwired to PB30/31, PC18/19 internally for the LoRa
radio. Move the pinctrl entries to SoC dts level. The same applies for
samr35.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In general, peripherals should be disabled by default and enabled at
board level when needed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add Silicon Labs xG24-PK6010A (BRD4187C radio plug-in board)
support to the efr32_radio board.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
Add Port 14/15 to device tree. These ports can only be configured as input.
Error out in gpio driver if user sets them as output.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
XMC4500 and XMC47/800 MCUs have a different memory layout. The
definitions have been moved to the derivative .dtsi of each MCU.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\cy8cproto_062_4343w board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
- Remove build asserts in favor of DT enums
- Remove power level property since it is unused by SDK
- Correct voltage ref value in DT to correspond to
chip specific values documented in reference manuals
instead of corresponding to SDK enum names.
- Fix SOC devicetrees affected by these changes.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Added a generic driver for RaspberryPi Pico PIO.
This driver is an intermediate driver for abstracting the PIO
device driver from physical pin configuration.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
- To link image loadable by MCUboot, zephyr,code-partition
must be set in the DTS.
- Move partition definitions from SoC DTS to the board DTS.
- Remove scratch partition since MCUboot does not recommend to use it.
- Increase bootloader partitions to 48K to fit recent MCUboot.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The newly added "power-amplifier-output" property for STM32WL SubGHz
radio nodes is mandatory.
Add the property to all affected modules and boards with the
appropriate value for the factory-default hardware configuration.
Add the "rfo-XX-max-power" properties to all affected modules and
boards with the appropriate value for the hardware configuration.
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
Adds address cells of size 1 and size cells of size 1 to GPREGRET
instances for Nordic devices.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds support for the `drivers.adc` test by adding an overlay
for the `efr32bg22_brd4184a` board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
EFR32MG24 uses the Secure Element's mailbox for entropy gathering
purposes. Reflect that in the device tree structure.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The efr32bg22-pinctrl.dtsi file was shared between bg22 and bg27 files.
It's better to name it efr32bg2x-pinctrl.dtsi.
Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
This commit splits device tree into more logical structure. Peripherals
which are on a board are in board dts files, while those which are parts of
a SoC are in SoC dtsi files.
Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
The general structure of efr32b27_sltb010a board is shared by more than one
board. This commit intrduces changes to the organization of board files,
which aim to take that into account.
Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
- Add initial version of Infineon CAT1 i2c driver.
- Add initial version of binding file for Infineon
CAT1 I2C driver
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
On iMX.RT devices, the number of GPIO pins exceeds the maximum of
64 that the PINT interrupt controller can support. Therefore, two
interrupt lines are now shared between the GPIO modules.
This patch allows the user to set the interrupt source for a GPIO
peripheral. For most LPC devices, this will always be the PINT. For some
RT devices, the PINT cannot use pins on GPIO modules other than 0 and 1
as input, and thus the INTA and INTB sources should be used.
Since Zephyr does not support sharing these interrupt between all GPIO
controllers, the user must configure a subset of all GPIO controllers to
use the shared module interrupts. An example of how to do so is provided
for the RT595 EVK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce PINT driver, for NXP pin interrupt and pattern match engine.
The driver currently supports only the pin interrupt feature of the
PINT.
Add DTS entires for the PINT on LPC and RT devices that support this
peripheral, and remove the interrupt defintions that are PINT specific
from the GPIO module on these devices.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
PR https://github.com/zephyrproject-rtos/zephyr/pull/55129 deleted the
"port-sel" property. Delete this property from remaining Microchip SoC
variants and boards.
Test: west build -b mec172xevb_assy6906 samples/drivers/espi/
Signed-off-by: Keith Short <keithshort@google.com>
The nRF9161 is technically a SiP (System-in-Package) that consists of
the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
so for nrfx/MDK the nRF9120 SoC is to be selected as the build target,
but since the nRF9161 is what a user can actually see on a board, using
only nRF9120 in the Zephyr build infrastructure might be confusing.
That's why in the top level of SoC definitions (for user-configurable
options in Kconfig, for example) the nRF9161 term is used and nRF9120
underneath.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds USB-HS support for LPC55S16, much in the same way that
LPC55S28 support was added previously.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Rename the nxp,kinetis-flexcan devicetree compatible to nxp,flexcan as it
is not specific to the NXP Kinetis series.
This is preparation for adding a nxp,flexcan-fd binding.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
No fmc node for the stm32u5 is implemented. This commit
adds a stm32-fmc compatible node to the device tree.
Signed-off-by: Christian Spinnler <christian.spinnler@fau.de>
Without adding a RAM entry for the USB RAM in the MPU,
USB RAM is mapped in the Peripheral Memory region
where unaligned memory accesses will cause a fault error.
Unaligned access errors were uncovered when we switch
to a different Zephyr C library where the memcpy function
implementation has unaligned accesses to the USB RAM.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Zephyr SPI driver model for full-duplex operation assumes
data will be transmitted and received during each clock period.
The QMSPI driver for the XEC family also supported dual and
quad I/O use cases which are inherently half-duplex. To
support dual/quad the driver incorrectly processed spi buffers
as all transmit buffers first then all receive buffers. This
worked if only the SPI driver was used. It did not work with
the Zephyr flash SPI NOR driver which assumes SPI drivers
follow the SPI driver model. This commit implements a QMSPI
driver that follows the Zephyr SPI driver model resulting in
a slightly smaller driver. Dual/quad SPI transactions are
supported if the experimental SPI extended mode Zephyr
configuration flag is enabled. We also remove the QMSPI full duplex
driver added previously to support the flash SPI NOR driver.
Added board to spi loop-back test and spi_flash sample.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add the FDCAN peripheral to the stm32H5 serie.
Two CAN1 & 2 instances for the stm32H56x/H57x devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the i2c driver for the Renesas SmartBond(tm) MCU family.
It supports blocking transfers and callback transfers.
Currently only supports controller mode.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Removed extra #includes at top of files. Missed closing } of
mec172xnlj.dtsi. Lower-cased 'reg' field of PWMs.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Adds the nodes for the GPDMA 1 & 2 peripherals
to the stm32h5 serie.
Each instance has 8 channels and 140 DMA requests.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The sdmmc clock source is either pll1_q or pll2_r according to the
refMan of the stm32h7 devices. HSI48 is not a vaild clock source.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes warnings produced by dtc 1.6 due to missing address-cell
in all arm st exti definition.
Signed-off-by: Christian Spinnler <christian.spinnler@fau.de>
Adds the nodes for the window and independent watchdog peripherals
plus the rng to the stm32h5 serie
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The number of available EasyDMA MAXCNT bits is now defined per-instance
in Devicetree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Deleted adc_mchp_xec.c and microchip,xec-adc.yaml file.
DTSI, yaml, CMakeLists.txt and Kconfig.xec files are
updated for compatible.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Updated the "adc_mchp_xec_v2.c" adc driver to support both MEC172x and
MEC15xx SOC.
ADC smapling clock configuration updated using DTS.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
This update devicetree entries and Kconfig definition to allow use of
reset cause on all SAM series.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Product URL: https://www.ti.com/product/CC1352P7
Datasheet : https://www.ti.com/lit/ds/symlink/cc1352p7.pdf
Features:
Powerful 48-MHz Arm® Cortex®-M4F processor
* 704KB flash program memory
* 256KB of ROM for protocols and library functions
* 8KB of cache SRAM
* 144KB of ultra-low leakage SRAM with parity for
high-reliability operation
* Dual-band Sub-1 GHz and 2.4 GHz operation
Updates:
* Remove CC1352P7_LaunchXL due to compliance checks
* Add CC1352P7 updates
* Update hal_ti for CC1352P7 support
* Remove blank line at end of modules/Kconfig.simplelink
* Split struct and typedef for pinctrl_soc_pin/pinctrl_soc_pin_t
* Reference cc13x2_cc26x2/pinctrl_soc.h
* Reference cc13x2_cc26x2/soc.h
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Modifying counter drivers (rtc and timer) to rely completely on
device tree and not on Kconfig of MDK flags.
Adapting dtsi for all SoCs and adapting test configuration.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Adds a driver for the Nordic nRF GPREGRET registers and adds
entries to the SoCs for this peripheral.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit removes the deletion of the `sram0` node, which resulted in
the compat string `mmio-sram` missing from the final devicetree when
building stm32l4r5-based platforms in Zephyr.
This bug was introduced in
306dea6ff3.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Remove SPI2 from F070 (not present on F070x6) and add it to F070xB.
Add it to F051 and remove it from F091 (since it is already defined).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Flash erase-block-size is 2048 for F030xC, F070xB, and F071 and higher.
For all others, it is 1024, default value in base dtsi.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove calibrated temperature measure from base dtsi since it does not
exist for STM32F0x0, and add it only for the other STM32F0.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fix DMA1 interrupt channels. There are 7 for STM32F071 and higher, and 5
for all others, default value for the series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove TIM6, 7 & 15 from base dtsi, and add TIM6 & 15 to F030x8, TIM7 for
F030xC, TIM15 for F070, TIM6 & 7 for F070xC, TIM6 & 15 to F051, and TIM7
for F071.
Remove TIM2 from F072 and F091 dtsi since it is already included in F031.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Modify the successive dtsi include to better reflect the underlying
structure of the F0 family.
There are two main subfamilies: STM32F0x0 on one side, and STM32F0x1, x2
and x8 on the other
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32L432 SDMMC issue
RM0394 :SDMMC
Not available on STM32L42xxx, STM32L432xx and STM32L442xx devices.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This patch adds watchdog driver for Renesas Smartbond SOCs.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds driver for SmartBond TRNG peripheral that with separate
ISR an thread data pools.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Microchip XEC devices specify GPIO pin using octal numbering and
organize pins in banks of 32. Chip documentation does not use
bank naming rather naming each pin by its octal number. This has
led to the developer having to calculate the bit position of a pin
in its 32-bit bank when a specifying the pin for GPIO usage. We
created a set of defines for all possible GPIO pins that specify
the DT GPIO bank name used in the chip level DTSI files and the
bit position in that bank.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The dma-requests specified for dmamux is changed to
the correct number of 107. This can be found in the
Reference Manual RM0455 Section 17.1.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Extends dmamux driver to support DMAMUX 2,
which supports the BDMA on STM32H7 devices.
Co-authored-by: Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
update MEC172x adc driver to support device PM.
Implement pm resume and suspend actions to put adc
pins in proper state for suspend and resume.
Notify kernel of busy when adc sampling is in progress.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add initial version of Infineon CAT1 clock control driver.
- supports clock initialization based on board DT configuration.
Added initial version of system_clocks.dtsi for Infineon PSoC 6 SOC.
Includes: clk_imo, path_mux0..4, fll0, pll0, clk_hf0..4, clk_fast,
clk_slow and clk_peri.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Devicetree for Infineon PSoC 6 SOC with following
structure:
1. MPN devicetree files
|--> psoc6
|--> mpns
|--> CY8C6016BZI_F04.dtsi
|--> CY8C6036BZI_F04.dtsi
|--> CY****.dtsi
Those file describes cpus, flash-controller, sram memory, nvic option. It
includes the package dtsi (e.g. psoc6_02.124-bga.dtsi) with information
about gpio (based on package e.g. 68-qfn, 128-tqfp, 124-bga, etc.) and
peripherals for (based on PSoC 6 series, psoc6_01, psoc6_02, etc).
MPN devicetree file is main platform dtsi file, which should be included
from board dts (e.g cy8cproto_062_4343w.dts), example:
#include <infineon/psoc6/mpns/CY8C624ABZI_S2D44.dtsi>
2. Devicetree files for PSoC 6 series 02 (2M).
Includes: psoc6_02.dtsi - peripherals dtsi psoc6_01.xxxxx.dtsi - package
dtsi. User does not directly include those files.
It automatically includes via MPN dtsi.
|--> psoc6_02
|--> psoc6_02.dtsi
|--> psoc6_02.100-wlcsp.dtsi
|--> psoc6_02.124-bga.dtsi
|--> psoc6_02.128-tqfp.dtsi
|--> psoc6_02.68-qfn.dtsi
In future PR/commits will be added Devicetree for support all
PSoC 6 series:
- for PSoC 6 series 01 (1M)
- for PSoC 6 series 03 (512)
- for PSoC 6 series 04 (256)
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Polarity support added to XEC PWM driver. This allows (for example) PWM
controlled LEDs that are active low to actually be turned off when set
to off.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change the dtsi order for the stm32L4plus serie,
starting with stm32l4p5-stm32l4q5 and stm32l4r5-stm32l4s5
Significant changes are on the SRAM size, the sdmmc2
and separated RTC-bbram registers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The SRAM1(total 192 KBytes) plus SRAM2: (total 64 KBytes)
plus SRAM3(total 512 KBytes) is available from 0x20000000 to
0x200BFFFF.
The SRAM size is only 768KB at address 0x20000000
The 16KB SRAM4 is located at address 0x28000000 so that no ram
is present from 0x200c0000 to 0x28000000.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
STM32L4plus mcu has SDMMC internal DMA which works without any
configuration and it's handled by SDMMC HAL driver. This commit adds
option to enable it and use it.
Signed-off-by: Petr Hlineny <development@hlineny.cz>
For STM32L47x and STM32L48x, the high calibration value for temperature is
110. For all other STM32L4xx, it is 130. So we set 130 by default and set
it to 110 for L471.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
ADC3 is already defined for STM32L471 which is included in STM32L476 and in
STM32L496 so no need to define it a second time.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Move LPTIM2 from stm32l431 dtsi to the general stm32l4 dtsi since all
STM32L4xx have two LPTIMs.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
All STM32H7 variants seems to have two fd-can interfaces available. Add
a can2 definition in stm32h7.dtsi, drop the current one in
stm32h723.dtsi. Also drop the override of address/size cells, this node
is not supposed to have any child node so they are not needed.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
rt1064 already includes dtsi file for rt1060, including values for ARM and
IPG PODFs. Drop explicit assignment of those PODF values in order to reduce
duplicated code.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
update the endpint in dts to 6 to alignd with RM
enable usb-device for LPC55S28
all USB supported tests/samples PASS
samples:
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T samples/subsys/usb/
...
INFO - 7 of 25 test configurations passed (100.00%),\
0 failed, 18 skipped with 0 warnings in 73.49 seconds
...
tests
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T tests/subsys/usb/
...
INFO - 3 of 4 test configurations passed (100.00%),\
0 failed, 1 skipped with 0 warnings in 36.39 seconds
...
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
The Microchip XEC family of microcontrollers includes a
simple DMA block implementing multiple channels. DMA supports
memory to memory, memory to peripheral, and peripheral to
memory transfers. Peripheral support is limited by each
chip to I2C and SPI controllers. DMA hardware does not support
scatter-gather or linked transactions.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
* there is a subtle difference to the stm32h74x
* c.f. rm0468 (stm32h723/733 stm32h725/735 and stm32h730)
* verified on stm32h735
Signed-off-by: Roland Lezuo <roland.lezuo@embedded-solutions.at>
New Zephyr WDT driver for TI CC13xx/CC26xx family.
Supports interrupts & MCU soft reset on timeout.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
According to the reference manual, all STM32G4 variants except
STM32G431/STM32G441 have the UART5 peripheral.
Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
In all STM32 dts, remove all reference to the following properties:
- has-temp-channel
- has-vref-channel
- has-vbat-channel
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that we have a binding to define the channel number for temperature
and Vref measurement, update all dtsi to include the information.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Bugfix for the Cyclone V SoC DK ethernet driver need to add emac-index
in dts
- We remove the "local-mac-address" property from
dts/arm/intel_socfpga_std.dtsi to
boards/arm/cyclonev_socdk/cyclonev_socdk.dts, since this value is
dependant on the board / implementation and not universal to
the "intel_socfpga" package that it inherets from.
- The above is also true for the "status" property as the board
should enable the device.
Signed-off-by: Benjamin Kyd <benjamin.kyd@intel.com>
Add three xbar nodes and four qdec nodes in the rt10xx devicetree include.
Add xbara to rt1052 in Kconfig.soc
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
On STM32L4 that probvide HSI48 clock, use it as 48MHz domain clock.
This impacts following devices:
-SDMMC
-RNG
-USB
Otherwise, when HSI48 is not available MSI is used.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STMF412 and STM32F413 did not support CAN bus in Zephyr yet.
This adds the device tree entries to be able to use all 2, resp.
3 CAN controllers.
Signed-off-by: Tom Stirnkorb <tom@stirnkorb.me>
Remove the vref-mv = <3300>; property for all the ADC node of
the stm32 devices as it is set by default to 3300mV by the
dts/adc/st,stm32-adc.yaml
(Except for the stm32f303 vref is 3000mV)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure RNG domain clock and align it on USB (as this is the same clk).
This is not stricly required, as this configuration matches default
reset but its more consistent this way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove SDMMC from f410 soc variant since it's not actually available.
Do this in package variant as F410 is included by f412 who has a SDMMC.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide SDMMC domain clock, when required (because it is common)use
the same as the one selected by USB and RNG.
Otherwise, when available use HSI48, otherwise use the most handy (MSI,
sysclk ...).
PLLSAI is not used as not implemented for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Align RNG domain clock confguration on USB clock configuration.
For now we're not able to fully use CLK48 as a mux clock, so
this has to be done on both nodes rather than on a centralized
fashion.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This sets the RNG node that will be used by the Nordic
devices which support TF-M (nRF5340/nRF9160) to use the
defined scheme with psa_generate_random.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Describe USB default domain clock on all USB devices.
When available select HSI48.
On some series, a default clock my be set by default at start up.
On those series, in order to be able to compute USB clock at runtime,
clock_control driver needs to be aware of configuration and then this
default config has to be described explicitly too.
Default clocks are not enabled though. It is up to board configuration
to provide correct clock configuration (and we should not enabled by
default clocks that would not be required by board configuration).
Note: This change doesn't consider STM32F1/F3 devices, which
have a specific USB clock configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT500.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
In file stm32l412.dtsi, spi2 was missing fifo compatibility,
this way failing to initialise fifo threshold correctly
when spi data width is configured.
Signed-off-by: Mirko Bottarelli <mirko.bottarelli@gmail.com>
Add rng definition to f410.
Though, don't inherit directly in f412 as it's integrated
in a different way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to ease description of DCKCFG regsiters,
make f412 a variant of f410 as it supposed to be.
Only exception is missing DAC1.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Add the st,static-prescaler DTS property to the
stm32u5 family on the LPTIM1.
Also present on lptim3, 4 but not defined yet.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Purpose of this node is only to provide a way to configure RF
clock using device tree and clock_control driver.
Default configuration is reproducing existing hard-coded configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add missing interrupts property for second FlexSPI device on RT5xx.
This interrupt is shared between both FlexSPI devices, but the memc
driver does not use interrupts so no conflict should arise.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The addresses of the flash and flash controller of the RP2040
SoC were mixed up. There was no clear distinction between the
flash and the flash controller, which was unclear but also
caused a DTC warning.
This commit makes the distinction clearer: The SSI peripheral at
0x18000000 is the flash controller, and the flash itself starts
at 0x10000000. The flash driver and rpi_pico.dts were fixed
accordingly.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
The pinctrl node of the RP2040 had the same unit address as the GPIO
bank, causing a DTC warning. To fix this, the pinctrl's address was
removed, as it does not require any.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add initial support for gd32l23x series. gd32l23x used Cortex-M23, based
on ARMv8-M baseline, implement the System Timer.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Enable RTU.SWT (Real-Time Unit.Software Watchdog Timer) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to 48 Mhz.
Signed-off-by: Quang Bui Trong <quang.buitrong@nxp.com>
Add missing I2C clock sources for STM32F303 & F373.
Add a comment for all STM32F3 I2Cx and for STM32F0 I2C1 that the clock
source should always be defined.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add config cell property to gd,gd32-dma.
For supporting hardware variation, Splitting base definition
to gd,gd32-dma-base.yaml.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Define SYSCLK as the default I2C source clock for I2C1 on STM32F0x
and all I2Cx on STM32F3x.
On most series, the default I2C clock source (when it exists) is PCLK.
This clock does not exist as I2C clock source on FO & F3 and the default
one is HSI. Since HSI is not necessarily enabled we explicitly set it
to SYSCLK instead.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Include the new clock file dedicated for STM32F7 instead of the F4 one
previously used.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
peripheral-id property should be eventually removed.
For now set it as optional and allow skipping the usage
in UART driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
peripheral-id property should be eventually removed entirely.
For now set it as optional and allow skipping the usage
in GPIO driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
HAL update affects also EFR32MG21 SoC. Because of that we need to
update the reg addresses in DTS.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
This commit adds support for Silicon Labs EFR32BG22 SoC.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The stm32G0 device has a one APB peripheral clock bus
but splitted on two RCC registers: RCC_ABPENR1 and RCC_ABPENR2
Peripherals are on one or the other.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
We are about to add UART reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
STM32L4 devices, except STM32L412 STM32L422 STM32L4P5 STM32L4Q5, have
32 4-byte battery-backed RTC backup registers. Other STM32L4 devices
have backup registers in tamper module, not used in Zephyr.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All STM32L1 devices have 4-byte battery-backed RTC registers, but
they have different number of registers:
STM32L151Xb-a has 5 registers.
STM32L151Xb has 20 registers.
STM32L151Xc, STM32L152Xc, STM32L152Xe have 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add BBRAM entry for all STM32H7 microcontrollers except STM32H7A3 and
STM32H7B3 which have backup registers in tamper module.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All supported STM32F3 devices have 4-byte battery-backed RTC registers,
but they have different number of registers:
STM32F303x8 and STM32F334 have 5 registers.
STM32F303xc and STM32F303xe have 16 registers.
STM32F302x8 has 20 registers.
STM32F373 has 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Among supported devices only STM32F031, STM32F051, STM32F072 and
STM32f09x have 5 4-byte battery-backed RTC registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add the HSI48 clock to the stm32 devices that have this
clock signal.
Within a stm32 family, only few might have the
RCC_HSI48_SUPPORT.
STM32WB has a CLK48 mux.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1170 and RT1160 CM7 and CM4 cores have the same set of differences.
Merge the DTS files for both CM4 and CM7 cores, to create generic
rt11xx_cm4 and rt11xx_cm7 files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add system reset control device (sysrst), so that the drivers can
assert/deassert its reset line through the public reset controller
driver API.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Re-enable the CAAM for entropy
now that the HAL driver has been fixed
Job descriptors must be accessed coherently
between CAAM DMA and core.
The M4 Cores still do not work
because of mpu/cache/kconfig arch complications,
disable caam for M4 cores in DTS
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable RTU System Timer Module (STM) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to
133.333333 MHz.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Define the octospi node for the stm32l4plus MCUs from
STMicroelectronics.
It is controlled by a OSPIMgr in front of each peripheral.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
FlexSPI memory map indicates that the FlexSPI register space is 128MB, not
64MB. Update this value to be correct.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds an ieee802154 node to the list of nRF5340 application
core's peripherals. While it does not translate directly into a physical
RADIO peripheral, it represents the capability to use the ieee802154
radio (indirectly, through the network core).
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Ensure that PECI block is enabled in the EC Subsystem by clearing
the PECI_DIS (peci disable) register
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
For all STM32 featuring octospi, clock-names are added to use them
instead of indexing for configuring the clock.
For U5 series, a third clock is added for the OSPI manager.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Set the status of the DMA controller, xdmac, to disabled. In effect
changing the default status from okay to disabled for all sam e70
based board.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add support input interrupts for GPIO pins on NXP S32Z27
SoC. The driver will convert GPIO pin to respective
interrupt line that will be processed by External
Interrupt Controller.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add initial support for the NXP S32Z27 SIUL2 External
Interrupt Controller. Each SIUL2 node has a child node
will act as an interrupt-controller that processes external
interrupt signals.
This driver is required to manage GPIO interrupts.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
New ADC driver for the TI CC13xx/CC26xx family.
ADC channel configurations are translated from Zephyr constants to
simplelink driverlib ones (e.g., sample times use a lookup table).
Async mode was also implemented & tested.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Define the DMA and DMAMUX peripheral for the stm32MP1
DMA1 and 2 are of type V1 of 8 streams (channels) each
with a DMAMUX peripheral. See the RefManual for details.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Set default interrupt priority to 3 for all Microchip MEC172x eSPI
host child devices except the UART's which are set to 1.
The espi peripherals don't require the maximum priority hence they
are being made uniform and a lower priority 3.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
USB interface that may be used to send messages from a USB host to
the M4 processor in the S3B, and vice-versa.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
Add MEC172x full duplex qmspi driver version to support full
duplex transfers as expected by the Zephyr spi driver model.
On every spi clock we transmit one bit and receive one bit.
This driver will work with Zephyr SPI NOR driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
updated dts variables naming (hyphen instead of underscore).
moved all properties in microchip ldma yaml to a separate include file,
these properties will be common with the (to be added)
full duplex spi driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Enable GPIO driver on s32z270dc2_r52 boards. S32Z27 pads are grouped
into GPIO ports A to N.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 LINFlexD peripheral operating
in UART mode. Polling and interrupt-based serial API's are supported.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce support for Pinctrl driver on NXP S32Z/E SoC's.
The NXP S32 pin controller is a singleton node responsible for
controlling the pin function selection and pin properties, based on the
pin node group approach. The pinmux configuration is encoded in a
32-bit value.
Each S32 SoC implementing Pinctrl must create a `pinctrl_soc.h` header
which define SoC-specific macros to initialize the pinctrl structure.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 devices, specifically for
S32Z27 from S32Z/E family.
NXP S32Z27 processors are composed of two Real-Time Units (RTU)
containing each four ARM Cortex-R52 cores with flexible split/lock
configuration, and dedicated internal SRAM.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Ethernet MAC dts definition for STM32F107, similar to STM32F207 but with
different clocks, especially no PTP clock.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>