This patch add i.MX 943 soc support.
The i.MX 943 applications processors integrate up to four Arm Cortex-A55
cores and supports functional safety with built-in 2x Arm Cortex -M33 and
-M7 cores which can be configured as a safety island. Optimizing
performance and power efficiency for Industrial, IoT and automotive
devices, i.MX 943 processors are built with NXP’s innovative Energy Flex
architecture.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Avoid the individual `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` for each
board instead to referencing the dt value.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Commit `2844850` inadvertently omitted
`SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_160MHZ`. This commit restores
the missing flag to ensure proper SOC clock setup.
Additionally, `SL_SI91X_CUSTOM_FEAT_LIMIT_PACKETS_PER_STA` is now enabled
as the default setting, aligning with the driver Kconfig.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
When building with clang and CONFIG_LTO, clang warns:
soc/nuvoton/npcx/common/pinctrl_soc.h:141:4: error: field flags within
'struct npcx_pinctrl' is less aligned than 'struct (unnamed struct at
soc/nuvoton/npcx/common/./pinctrl_soc.h:128:2)' and is usually due to
'struct npcx_pinctrl' being packed, which can lead to unaligned accesses
[-Werror,-Wunaligned-access]
} flags;
^
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
This commit reflects a difference between FE310-G000 and FE310-G002 SoCs,
since only the latter supports PMP. The result of that is the split of the
HiFive1 board into two separate targets, since the HWMv2 right now assumes
that board revisions share the same SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Use flash_k4 driver for internal flash instead of ROM API driver. One
benefit is the flash program phrase size decreases from 128 Bytes to 16
Bytes. 16 Byte phrases enables this SOC to leverage the Zephyr NVS
subsystem, and the MCUboot swap mode.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Conflicts:
west.yml
This fixes a regression introduced in c31640239c where all regions
except Flash and RAM where left unmapped. Before introducing region
0 that prevents speculative access to the entire memory space, we
were relying on the architectural background map to access them.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This is a fix for issue #90426 .
Marking __kinetis_flash_config with __used attribute prevents
unwanted deletion when compiling with LTO.
Signed-off-by: Matthieu Speder <mspeder@users.sourceforge.net>
- Adds a flash runner configuration for mimxrt1052 and mimxrt1062,
used for sysbuild multi-image projects, mainly for MCU-boot.
- Avoid unwanted multiple erases and resets.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
On RW, normal configuration has all clock generators gated in PM2.
Only the LPOSC is available for main clock source since it is a low
power clock.
Many of the peripherals on the chip are still "on" and do need a
main clock source in order to be effective as wakeup sources
to the chip as intended. So we should make this switch for PM2
specifically in order to achieve desired wakeup capabilities.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
PMU related functions need to be located in IRAM when sleep
process is triggered, as cache is disabled past a certain point
in the execution of the sleep process.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
add uhc related items to dts.
add clock initialization
add BM4 if CONFIG_USB_UHC_NXP_KHCI is enabled
add pin mux
update board related CMakeLists.txt
update sdk-ng CMake to include NXP controller drivers
update west.yml to contain the hal_nxp pr
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
espi: add espi peripheral channel HOST_CMD driver for rts5912
Unlike other chips using IO port 0x800-0x8ff, we utilize shared memory to
transfer host command parameters. The AP firmware must have corresponding
settings for this configuration.
Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
Due to erratum ERR011573, speculative accesses might be performed
to normal memory unmapped in the MPU. This can be avoided by using
MPU region 0 to cover all unmapped memory and make this region
execute-never and inaccessible.
Fixes#89852
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
1. Add it51526bw SoC variant to it51xxx SoC series.
2. Create the .dtsi file with adjusted flash size for 512Kb (default = 1M).
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The ROM bootloader has the option to boot from external QSPI flash on
the FlexSPI instead of internal flash. Adds
CONFIG_NXP_FLEXSPI_BOOT_HEADER to include the FlexSPI boot ROM header
in the image.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Add Set_WP function to set SPI flash WP line to low
Add Get_WP function to obtain status of the SPI flash WP line
Signed-off-by: Benson Huang <benson7633769@gmail.com>
Add code for sama7g5 Generic Clock, Main Clock, Main System Bus Clock,
Peripheral Clock, Programmable Clock and PLL Clock.
Signed-off-by: Tony Han <tony.han@microchip.com>
To simplify usage add dependecy to MAX32_ON_ENTER_CPU_IDLE_HOOK
If CONFIG_PM not defined set to to y as current,
If CONFIG_PM defined not set it
If user set CONFIG_PM not need to disable
MAX32_ON_ENTER_CPU_IDLE_HOOK anymore
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
- AM6232 is a dual core variant of AM6234 with everything being same.
- Used in the first batch of PocketBeagle 2
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Added custom mcuboot cmake for sign/encrypt by using cysecuretools
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Enable support of SECURE LCS stage. In this stage, the protection
state is set to “secure”. A secured device will boot only when the
authentication of its flash boot and application code succeeds
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Instead of using app_header.c generate the app header using python
script and merge with final binary post build
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Siwx91x support a specific mode slightly better than the old legacy PS
mode.
This mode has to be set on the NWP boot, so it is not easy to configure
it during the runtime. Hence, this patch only provide a compile time
option to enable it.
Co-authored-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
sys_heap alloc and free are not thread safe so lock is needed to
prevent data corruption.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Sets the SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig from devicetree
entries. Also fixes invalid configuration on nrf54h20 whereby it
attempts to take the clock frequency from a peripheral that does
not exist
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Port SYS_INIT to use soc_early_init_hook as SYS_INITs are legacy.
Due to moving dmm_init() from PRE_KERNEL_1 SYS_INIT to
soc_early_init_hook(), the DMM test is also updated to ensure that
its setup function runs before dmm_init().
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Enabling CCDEV_SEL_EN may interfere with the expected behavior of
VCC1_RST#.
To prevent potential issues, this commit sets CCDEV_SEL_EN
to be disabled by default, ensuring reliable VCC1_RST# behavior.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
