soc: xtensa: Add mimxrt685s/hifi4
Add definitions, linker file and init code for mimxrt685s/hifi4 (i.MX RT685's HiFi 4 DSP). Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
This commit is contained in:
parent
44ae59e589
commit
e253c3b57f
14 changed files with 1275 additions and 6 deletions
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@ -7,3 +7,7 @@
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if(CONFIG_SOC_MIMXRT685S_CM33)
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add_subdirectory(cm33)
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endif()
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if(CONFIG_SOC_MIMXRT685S_HIFI4)
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add_subdirectory(hifi4)
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endif()
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@ -32,10 +32,23 @@ config SOC_MIMXRT685S_CM33
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select HAS_MCUX_CTIMER
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select SOC_EARLY_INIT_HOOK
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config SOC_MIMXRT685S_HIFI4
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select XTENSA
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select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
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select XTENSA_RESET_VECTOR
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select XTENSA_USE_CORE_CRT1
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select CLOCK_CONTROL
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select HAS_MCUX
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select HAS_MCUX_SYSCON
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select SOC_EARLY_INIT_HOOK
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if SOC_SERIES_IMXRT6XX
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config MCUX_CORE_SUFFIX
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default "_cm33" if SOC_MIMXRT685S_CM33
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default "_dsp" if SOC_MIMXRT685S_HIFI4
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if SOC_MIMXRT685S_CM33
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config INIT_SYS_PLL
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bool "Initialize SYS PLL"
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@ -62,4 +75,45 @@ config IMXRT6XX_CODE_CACHE
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Enable code cache for FlexSPI region at boot. If this Kconfig is
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cleared, the CACHE64 controller will be disabled during SOC init
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endif
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endif # SOC_MIMXRT685S_CM33
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if SOC_MIMXRT685S_HIFI4
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DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset)
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DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data)
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DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text)
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config RT685_ADSP_STACK_SIZE
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hex "Boot time stack size"
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default 0x1000
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help
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Stack space is reserved at the end of the RT685_ADSP_DATA_MEM
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region, starting at RT685_ADSP_DATA_MEM_ADDR - RT685_ADSP_STACK_SIZE
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config RT685_ADSP_RESET_MEM_ADDR
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hex
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default $(dt_node_reg_addr_hex,$(DT_ADSP_RESET_MEM))
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config RT685_ADSP_RESET_MEM_SIZE
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hex
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default $(dt_node_reg_size_hex,$(DT_ADSP_RESET_MEM))
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config RT685_ADSP_DATA_MEM_ADDR
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hex
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default $(dt_node_reg_addr_hex,$(DT_ADSP_DATA_MEM))
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config RT685_ADSP_DATA_MEM_SIZE
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hex
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default $(dt_node_reg_size_hex,$(DT_ADSP_DATA_MEM))
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config RT685_ADSP_TEXT_MEM_ADDR
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hex
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default $(dt_node_reg_addr_hex,$(DT_ADSP_TEXT_MEM))
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config RT685_ADSP_TEXT_MEM_SIZE
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hex
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default $(dt_node_reg_size_hex,$(DT_ADSP_TEXT_MEM))
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endif # SOC_MIMXRT685S_HIFI4
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endif # SOC_SERIES_IMXRT6XX
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@ -65,3 +65,13 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
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endif # CORTEX_M_SYSTICK
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endif # SOC_MIMXRT685S_CM33
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if SOC_MIMXRT685S_HIFI4
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 198000000
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config MCUX_CORE_SUFFIX
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default "_dsp"
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endif # SOC_MIMXRT685S_HIFI4
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@ -12,26 +12,34 @@ config SOC_MIMXRT685S
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bool
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select SOC_SERIES_IMXRT6XX
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config SOC
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default "mimxrt685s" if SOC_MIMXRT685S
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config SOC_MIMXRT685S_CM33
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bool
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select SOC_MIMXRT685S
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config SOC
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default "mimxrt685s" if SOC_MIMXRT685S_CM33
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config SOC_MIMXRT685S_HIFI4
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bool
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select SOC_MIMXRT685S
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config SOC_PART_NUMBER_MIMXRT685SFVKB
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select SOC_MIMXRT685S
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bool
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select SOC_MIMXRT685S_CM33
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config SOC_PART_NUMBER_MIMXRT685SFFOB
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select SOC_MIMXRT685S
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bool
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select SOC_MIMXRT685S_CM33
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config SOC_PART_NUMBER_MIMXRT685SFAWBR
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select SOC_MIMXRT685S
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bool
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select SOC_MIMXRT685S_CM33
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config SOC_PART_NUMBER
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default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB
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default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB
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default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR
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config SOC_TOOLCHAIN_NAME
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string
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default "nxp_rt600_adsp" if SOC_MIMXRT685S_HIFI4
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16
soc/nxp/imxrt/imxrt6xx/hifi4/CMakeLists.txt
Normal file
16
soc/nxp/imxrt/imxrt6xx/hifi4/CMakeLists.txt
Normal file
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@ -0,0 +1,16 @@
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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_include_directories(.)
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zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
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zephyr_sources(soc.c)
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zephyr_library_include_directories(
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${ZEPHYR_BASE}/kernel/include
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${ZEPHYR_BASE}/arch/${ARCH}/include
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)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
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353
soc/nxp/imxrt/imxrt6xx/hifi4/include/_soc_inthandlers.h
Normal file
353
soc/nxp/imxrt/imxrt6xx/hifi4/include/_soc_inthandlers.h
Normal file
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@ -0,0 +1,353 @@
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/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* Functions here are designed to produce efficient code to
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* search an Xtensa bitmask of interrupts, inspecting only those bits
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* declared to be associated with a given interrupt level. Each
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* dispatcher will handle exactly one flagged interrupt, in numerical
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* order (low bits first) and will return a mask of that bit that can
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* then be cleared by the calling code. Unrecognized bits for the
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* level will invoke an error handler.
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*/
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#include <xtensa/config/core-isa.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/sw_isr_table.h>
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#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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static inline int _xtensa_handle_one_int5(unsigned int mask)
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{
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int irq;
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if (mask & BIT(0)) {
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mask = BIT(0);
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irq = 0;
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goto handle_irq;
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}
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return 0;
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handle_irq:
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_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
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return mask;
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}
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static inline int _xtensa_handle_one_int2(unsigned int mask)
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{
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int irq;
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if (mask & 0x70006) {
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if (mask & 0x6) {
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if (mask & BIT(1)) {
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mask = BIT(1);
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irq = 1;
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goto handle_irq;
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}
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if (mask & BIT(2)) {
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mask = BIT(2);
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irq = 2;
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goto handle_irq;
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}
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} else {
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if (mask & BIT(16)) {
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mask = BIT(16);
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irq = 16;
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goto handle_irq;
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}
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if (mask & BIT(17)) {
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mask = BIT(17);
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irq = 17;
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goto handle_irq;
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}
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if (mask & BIT(18)) {
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mask = BIT(18);
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irq = 18;
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goto handle_irq;
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}
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}
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} else {
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if (mask & 0x180000) {
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if (mask & BIT(19)) {
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mask = BIT(19);
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irq = 19;
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goto handle_irq;
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}
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if (mask & BIT(20)) {
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mask = BIT(20);
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irq = 20;
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goto handle_irq;
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}
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} else {
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if (mask & BIT(21)) {
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mask = BIT(21);
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irq = 21;
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goto handle_irq;
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}
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if (mask & BIT(22)) {
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mask = BIT(22);
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irq = 22;
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goto handle_irq;
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}
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if (mask & BIT(23)) {
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mask = BIT(23);
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irq = 23;
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goto handle_irq;
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}
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}
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}
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return 0;
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handle_irq:
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_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
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return mask;
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}
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static inline int _xtensa_handle_one_int3(unsigned int mask)
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{
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int irq;
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if (mask & 0x7000018) {
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if (mask & 0x18) {
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if (mask & BIT(3)) {
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mask = BIT(3);
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irq = 3;
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goto handle_irq;
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}
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if (mask & BIT(4)) {
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mask = BIT(4);
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irq = 4;
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goto handle_irq;
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}
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} else {
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if (mask & BIT(24)) {
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mask = BIT(24);
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irq = 24;
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goto handle_irq;
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}
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if (mask & BIT(25)) {
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mask = BIT(25);
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irq = 25;
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goto handle_irq;
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}
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if (mask & BIT(26)) {
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mask = BIT(26);
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irq = 26;
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goto handle_irq;
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}
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}
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} else {
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if (mask & 0x18000000) {
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if (mask & BIT(27)) {
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mask = BIT(27);
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irq = 27;
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goto handle_irq;
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}
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if (mask & BIT(28)) {
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mask = BIT(28);
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irq = 28;
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goto handle_irq;
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}
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} else {
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if (mask & BIT(29)) {
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mask = BIT(29);
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irq = 29;
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goto handle_irq;
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}
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if (mask & BIT(30)) {
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mask = BIT(30);
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irq = 30;
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goto handle_irq;
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}
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if (mask & BIT(31)) {
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mask = BIT(31);
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irq = 31;
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goto handle_irq;
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}
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}
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}
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return 0;
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handle_irq:
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_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
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return mask;
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}
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static inline int _xtensa_handle_one_int1(unsigned int mask)
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{
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int irq;
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if (mask & 0x3e0) {
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if (mask & 0x60) {
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if (mask & BIT(5)) {
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mask = BIT(5);
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irq = 5;
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goto handle_irq;
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}
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if (mask & BIT(6)) {
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mask = BIT(6);
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irq = 6;
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goto handle_irq;
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}
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} else {
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if (mask & BIT(7)) {
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mask = BIT(7);
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irq = 7;
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goto handle_irq;
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}
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if (mask & BIT(8)) {
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mask = BIT(8);
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irq = 8;
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goto handle_irq;
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}
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if (mask & BIT(9)) {
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mask = BIT(9);
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irq = 9;
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goto handle_irq;
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}
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}
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} else {
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if (mask & 0x1c00) {
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if (mask & BIT(10)) {
|
||||
mask = BIT(10);
|
||||
irq = 10;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(11)) {
|
||||
mask = BIT(11);
|
||||
irq = 11;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(12)) {
|
||||
mask = BIT(12);
|
||||
irq = 12;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(13)) {
|
||||
mask = BIT(13);
|
||||
irq = 13;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(14)) {
|
||||
mask = BIT(14);
|
||||
irq = 14;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(15)) {
|
||||
mask = BIT(15);
|
||||
irq = 15;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
12
soc/nxp/imxrt/imxrt6xx/hifi4/include/adsp/cache.h
Normal file
12
soc/nxp/imxrt/imxrt6xx/hifi4/include/adsp/cache.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_ADSP_CACHE_H__
|
||||
#define __COMMON_ADSP_CACHE_H__
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
|
||||
#endif
|
41
soc/nxp/imxrt/imxrt6xx/hifi4/include/adsp/io.h
Normal file
41
soc/nxp/imxrt/imxrt6xx/hifi4/include/adsp/io.h
Normal file
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2025 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_IO__
|
||||
#define __INCLUDE_IO__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc/memory.h>
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
#include <zephyr/arch/common/sys_io.h>
|
||||
|
||||
static inline uint32_t io_reg_read(uint32_t reg)
|
||||
{
|
||||
return sys_read32(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write(uint32_t reg, uint32_t val)
|
||||
{
|
||||
sys_write32(val, reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_update_bits(uint32_t reg, uint32_t mask,
|
||||
uint32_t value)
|
||||
{
|
||||
io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
|
||||
}
|
||||
|
||||
static inline uint16_t io_reg_read16(uint32_t reg)
|
||||
{
|
||||
return sys_read16(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write16(uint32_t reg, uint16_t val)
|
||||
{
|
||||
sys_write16(val, reg);
|
||||
}
|
||||
|
||||
#endif
|
103
soc/nxp/imxrt/imxrt6xx/hifi4/include/pinctrl_soc.h
Normal file
103
soc/nxp/imxrt/imxrt6xx/hifi4/include/pinctrl_soc.h
Normal file
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT6XX_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NXP_IMX_RT6XX_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
typedef uint32_t pinctrl_soc_pin_t;
|
||||
|
||||
|
||||
#define Z_PINCTRL_IOPCTL_PINCFG(node_id) \
|
||||
(IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
|
||||
(IOPCTL_PIO_PUPDENA_MASK |)) /* pull down */ \
|
||||
IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
|
||||
(IOPCTL_PIO_PUPDENA_MASK | IOPCTL_PIO_PUPDSEL_MASK |)) /* pull up */ \
|
||||
IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \
|
||||
IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \
|
||||
IOPCTL_PIO_SLEWRATE(DT_ENUM_IDX(node_id, slew_rate)) | /* slew rate */ \
|
||||
IOPCTL_PIO_FULLDRIVE(DT_ENUM_IDX(node_id, drive_strength)) | /* drive strength */ \
|
||||
IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \
|
||||
IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */
|
||||
|
||||
/* MCUX RT parts only have one pin type */
|
||||
#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF)
|
||||
#define Z_PINCTRL_IOCON_A_PIN_MASK (0)
|
||||
#define Z_PINCTRL_IOCON_I_PIN_MASK (0)
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
|
||||
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group),
|
||||
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
|
||||
/*!<@brief Analog mux is disabled */
|
||||
#define IOPCTL_PIO_ANAMUX_DI 0x00u
|
||||
/*!<@brief Analog mux is enabled */
|
||||
#define IOPCTL_PIO_ANAMUX_EN 0x0200u
|
||||
/*!<@brief Normal drive */
|
||||
#define IOPCTL_PIO_FULLDRIVE_DI 0x00u
|
||||
/*!<@brief Full drive */
|
||||
#define IOPCTL_PIO_FULLDRIVE_EN 0x0100u
|
||||
/*!<@brief Selects pin function 0 */
|
||||
#define IOPCTL_PIO_FUNC0 0x00u
|
||||
/*!<@brief Selects pin function 1 */
|
||||
#define IOPCTL_PIO_FUNC1 0x01u
|
||||
/*!<@brief Selects pin function 2 */
|
||||
#define IOPCTL_PIO_FUNC2 0x02u
|
||||
/*!<@brief Selects pin function 3 */
|
||||
#define IOPCTL_PIO_FUNC3 0x03u
|
||||
/*!<@brief Selects pin function 4 */
|
||||
#define IOPCTL_PIO_FUNC4 0x04u
|
||||
/*!<@brief Selects pin function 5 */
|
||||
#define IOPCTL_PIO_FUNC5 0x05u
|
||||
/*!<@brief Selects pin function 6 */
|
||||
#define IOPCTL_PIO_FUNC6 0x06u
|
||||
/*!<@brief Selects pin function 7 */
|
||||
#define IOPCTL_PIO_FUNC7 0x07u
|
||||
/*!<@brief Selects pin function 8 */
|
||||
#define IOPCTL_PIO_FUNC8 0x08u
|
||||
/*!<@brief Disable input buffer function */
|
||||
#define IOPCTL_PIO_INBUF_DI 0x00u
|
||||
/*!<@brief Enables input buffer function */
|
||||
#define IOPCTL_PIO_INBUF_EN 0x40u
|
||||
/*!<@brief Input function is not inverted */
|
||||
#define IOPCTL_PIO_INV_DI 0x00u
|
||||
/*!<@brief Input function is inverted */
|
||||
#define IOPCTL_PIO_INV_EN 0x0800u
|
||||
/*!<@brief Pseudo Output Drain is disabled */
|
||||
#define IOPCTL_PIO_PSEDRAIN_DI 0x00u
|
||||
/*!<@brief Pseudo Output Drain is enabled */
|
||||
#define IOPCTL_PIO_PSEDRAIN_EN 0x0400u
|
||||
/*!<@brief Enable pull-down function */
|
||||
#define IOPCTL_PIO_PULLDOWN_EN 0x00u
|
||||
/*!<@brief Enable pull-up function */
|
||||
#define IOPCTL_PIO_PULLUP_EN 0x20u
|
||||
/*!<@brief Disable pull-up / pull-down function */
|
||||
#define IOPCTL_PIO_PUPD_DI 0x00u
|
||||
/*!<@brief Enable pull-up / pull-down function */
|
||||
#define IOPCTL_PIO_PUPD_EN 0x10u
|
||||
/*!<@brief Normal mode */
|
||||
#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u
|
||||
/*!<@brief Slow mode */
|
||||
#define IOPCTL_PIO_SLEW_RATE_SLOW 0x80u
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT6XX_PINCTRL_SOC_H_ */
|
39
soc/nxp/imxrt/imxrt6xx/hifi4/include/soc.h
Normal file
39
soc/nxp/imxrt/imxrt6xx/hifi4/include/soc.h
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
|
||||
#include <adsp/cache.h>
|
||||
#include <pinctrl_soc.h>
|
||||
|
||||
#ifndef __INC_IMX_SOC_H
|
||||
#define __INC_IMX_SOC_H
|
||||
|
||||
/* Macros related to interrupt handling */
|
||||
#define XTENSA_IRQ_NUM_SHIFT 0
|
||||
#define XTENSA_IRQ_NUM_MASK 0xff
|
||||
|
||||
/*
|
||||
* IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
|
||||
*
|
||||
* 1. Peripheral Register bit offset.
|
||||
*/
|
||||
#define XTENSA_IRQ_NUMBER(_irq) \
|
||||
((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
|
||||
|
||||
extern void z_soc_irq_enable(uint32_t irq);
|
||||
extern void z_soc_irq_disable(uint32_t irq);
|
||||
extern int z_soc_irq_is_enabled(unsigned int irq);
|
||||
|
||||
/* Workaround to handle macro variation in the SDK */
|
||||
#ifndef INPUTMUX_PINTSEL_COUNT
|
||||
#define INPUTMUX_PINTSEL_COUNT INPUTMUX_PINT_SEL_COUNT
|
||||
#endif
|
||||
|
||||
#endif /* __INC_IMX_SOC_H */
|
51
soc/nxp/imxrt/imxrt6xx/hifi4/include/soc/memory.h
Normal file
51
soc/nxp/imxrt/imxrt6xx/hifi4/include/soc/memory.h
Normal file
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Google LLC.
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __XTENSA_MEMORY_H__
|
||||
#define __XTENSA_MEMORY_H__
|
||||
|
||||
#include <autoconf.h>
|
||||
|
||||
#define TEXT_BASE (CONFIG_RT685_ADSP_TEXT_MEM_ADDR)
|
||||
#define TEXT_SIZE (CONFIG_RT685_ADSP_TEXT_MEM_SIZE)
|
||||
|
||||
#define DATA_BASE (CONFIG_RT685_ADSP_DATA_MEM_ADDR)
|
||||
#define DATA_SIZE (CONFIG_RT685_ADSP_DATA_MEM_SIZE - CONFIG_RT685_ADSP_STACK_SIZE)
|
||||
|
||||
/* The reset vector address in SRAM and its size. */
|
||||
#define XCHAL_RESET_VECTOR0_PADDR_IRAM (CONFIG_RT685_ADSP_RESET_MEM_ADDR)
|
||||
#define MEM_RESET_TEXT_SIZE (0x2e0)
|
||||
#define MEM_RESET_LIT_SIZE (0x120)
|
||||
|
||||
/* Base address of all interrupt vectors in IRAM. */
|
||||
#define XCHAL_VECBASE_RESET_PADDR_IRAM (TEXT_BASE)
|
||||
#define MEM_VECBASE_LIT_SIZE (0x178)
|
||||
|
||||
/* Vector and literal sizes. */
|
||||
#define MEM_VECT_LIT_SIZE (0x4)
|
||||
#define MEM_VECT_TEXT_SIZE (0x1C)
|
||||
|
||||
/* Addresses of the interrupt vectors. */
|
||||
#define XCHAL_INT_VECTOR_ADDR(x) (XCHAL_VECBASE_RESET_PADDR_IRAM + (x))
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x17C))
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x19C))
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1BC))
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1DC))
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1FC))
|
||||
#define XCHAL_USER_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x21C))
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x23C))
|
||||
|
||||
|
||||
/* Size and location of the intList section. Later used to construct the
|
||||
* Interrupt Descriptor Table (IDT). This is a bogus address as this
|
||||
* section will be stripped off in the final image. Situated before the DSP's
|
||||
* ITCM - prevents memory region inflation in zephyr_pre0.elf.
|
||||
*/
|
||||
#define IDT_SIZE (0x2000)
|
||||
#define IDT_BASE (CONFIG_RT685_ADSP_RESET_MEM_ADDR - IDT_SIZE)
|
||||
|
||||
#endif
|
466
soc/nxp/imxrt/imxrt6xx/hifi4/linker.ld
Normal file
466
soc/nxp/imxrt/imxrt6xx/hifi4/linker.ld
Normal file
|
@ -0,0 +1,466 @@
|
|||
/*
|
||||
* Copyright 2025 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(xtensa)
|
||||
|
||||
#include <soc/memory.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
|
||||
#define RAMABLE_REGION adsp_data :adsp_data_phdr
|
||||
#define ROMABLE_REGION adsp_data :adsp_data_phdr
|
||||
|
||||
MEMORY
|
||||
{
|
||||
vector_reset_text :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM,
|
||||
len = MEM_RESET_TEXT_SIZE
|
||||
vector_reset_lit :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
|
||||
len = MEM_RESET_LIT_SIZE
|
||||
vector_base_text :
|
||||
org = XCHAL_VECBASE_RESET_PADDR_IRAM,
|
||||
len = MEM_VECBASE_LIT_SIZE
|
||||
vector_int2_lit :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int2_text :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int3_lit :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int3_text :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int4_lit :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int4_text :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int5_lit :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int5_text :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_kernel_lit :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_kernel_text :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_user_lit :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_user_text :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_double_lit :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_double_text :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
adsp_text :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
|
||||
len = TEXT_SIZE - MEM_VECT_TEXT_SIZE
|
||||
adsp_data :
|
||||
org = DATA_BASE,
|
||||
len = DATA_SIZE
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST :
|
||||
org = IDT_BASE,
|
||||
len = IDT_SIZE
|
||||
#endif
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
vector_reset_text_phdr PT_LOAD;
|
||||
vector_reset_lit_phdr PT_LOAD;
|
||||
vector_base_text_phdr PT_LOAD;
|
||||
vector_base_lit_phdr PT_LOAD;
|
||||
vector_int2_text_phdr PT_LOAD;
|
||||
vector_int2_lit_phdr PT_LOAD;
|
||||
vector_int3_text_phdr PT_LOAD;
|
||||
vector_int3_lit_phdr PT_LOAD;
|
||||
vector_int4_text_phdr PT_LOAD;
|
||||
vector_int4_lit_phdr PT_LOAD;
|
||||
vector_int5_text_phdr PT_LOAD;
|
||||
vector_int5_lit_phdr PT_LOAD;
|
||||
vector_kernel_text_phdr PT_LOAD;
|
||||
vector_kernel_lit_phdr PT_LOAD;
|
||||
vector_user_text_phdr PT_LOAD;
|
||||
vector_user_lit_phdr PT_LOAD;
|
||||
vector_double_text_phdr PT_LOAD;
|
||||
vector_double_lit_phdr PT_LOAD;
|
||||
adsp_text_phdr PT_LOAD;
|
||||
adsp_data_phdr PT_LOAD;
|
||||
}
|
||||
|
||||
PROVIDE(_memmap_reset_vector = XCHAL_RESET_VECTOR0_PADDR_IRAM);
|
||||
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_IRAM);
|
||||
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
/* Various memory-map dependent cache attribute settings: */
|
||||
_memmap_cacheattr_wb_base = 0x00000012;
|
||||
_memmap_cacheattr_wt_base = 0x00000012;
|
||||
_memmap_cacheattr_bp_base = 0x00000022;
|
||||
_memmap_cacheattr_unused_mask = 0xFFFFFF00;
|
||||
_memmap_cacheattr_wb_trapnull = 0x22222212;
|
||||
_memmap_cacheattr_wba_trapnull = 0x22222212;
|
||||
_memmap_cacheattr_wbna_trapnull = 0x22222212;
|
||||
_memmap_cacheattr_wt_trapnull = 0x22222212;
|
||||
_memmap_cacheattr_bp_trapnull = 0x22222222;
|
||||
_memmap_cacheattr_wb_strict = 0xFFFFFF12;
|
||||
_memmap_cacheattr_wt_strict = 0xFFFFFF12;
|
||||
_memmap_cacheattr_bp_strict = 0xFFFFFF22;
|
||||
_memmap_cacheattr_wb_allvalid = 0x22222212;
|
||||
_memmap_cacheattr_wt_allvalid = 0x22222212;
|
||||
_memmap_cacheattr_bp_allvalid = 0x22222222;
|
||||
_memmap_region_map = 0x00000003;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
.ResetVector.text : ALIGN(4)
|
||||
{
|
||||
_ResetVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
_ResetVector_text_end = ABSOLUTE(.);
|
||||
} >vector_reset_text :vector_reset_text_phdr
|
||||
|
||||
.ResetVector.literal : ALIGN(4)
|
||||
{
|
||||
_ResetVector_literal_start = ABSOLUTE(.);
|
||||
*(.ResetVector.literal)
|
||||
_ResetVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_reset_lit :vector_reset_lit_phdr
|
||||
|
||||
.WindowVectors.text : ALIGN(4)
|
||||
{
|
||||
_WindowVectors_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.WindowVectors.text))
|
||||
_WindowVectors_text_end = ABSOLUTE(.);
|
||||
} >vector_base_text :vector_base_text_phdr
|
||||
|
||||
.Level2InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level2InterruptVector.literal)
|
||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int2_lit :vector_int2_lit_phdr
|
||||
|
||||
.Level2InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level2InterruptVector.text))
|
||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int2_text :vector_int2_text_phdr
|
||||
|
||||
.Level3InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level3InterruptVector.literal)
|
||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int3_lit :vector_int3_lit_phdr
|
||||
|
||||
.Level3InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level3InterruptVector.text))
|
||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int3_text :vector_int3_text_phdr
|
||||
|
||||
.DebugExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DebugExceptionVector.literal)
|
||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int4_lit :vector_int4_lit_phdr
|
||||
|
||||
.DebugExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DebugExceptionVector.text))
|
||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int4_text :vector_int4_text_phdr
|
||||
|
||||
.NMIExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.NMIExceptionVector.literal)
|
||||
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int5_lit :vector_int5_lit_phdr
|
||||
|
||||
.NMIExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.NMIExceptionVector.text))
|
||||
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int5_text :vector_int5_text_phdr
|
||||
|
||||
.KernelExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.KernelExceptionVector.literal)
|
||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_kernel_lit :vector_kernel_lit_phdr
|
||||
|
||||
.KernelExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.KernelExceptionVector.text))
|
||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_kernel_text :vector_kernel_text_phdr
|
||||
|
||||
.UserExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.UserExceptionVector.literal)
|
||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_user_lit :vector_user_lit_phdr
|
||||
|
||||
.UserExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.UserExceptionVector.text))
|
||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_user_text :vector_user_text_phdr
|
||||
|
||||
.DoubleExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DoubleExceptionVector.literal)
|
||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_double_lit :vector_double_lit_phdr
|
||||
|
||||
.DoubleExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DoubleExceptionVector.text))
|
||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_double_text :vector_double_text_phdr
|
||||
|
||||
.iram.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} >adsp_text :adsp_text_phdr
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
KEEP (*(.xt_except_table))
|
||||
KEEP (*(.gcc_except_table .gcc_except_table.*))
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
KEEP (*(.eh_frame))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
} >adsp_data :adsp_data_phdr
|
||||
|
||||
.module_init : ALIGN(4)
|
||||
{
|
||||
_module_init_start = ABSOLUTE(.);
|
||||
*(*.initcall)
|
||||
_module_init_end = ABSOLUTE(.);
|
||||
} >adsp_data :adsp_data_phdr
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
*(.ResetVector.literal)
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >adsp_text :adsp_text_phdr
|
||||
|
||||
#include <zephyr/linker/common-rom.ld>
|
||||
|
||||
.fw_ready : ALIGN(4)
|
||||
{
|
||||
KEEP(*(".fw_ready"));
|
||||
KEEP (*(.fw_ready_metadata))
|
||||
} >adsp_data :adsp_data_phdr
|
||||
|
||||
.noinit : ALIGN(4)
|
||||
{
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
} >adsp_data :adsp_data_phdr
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_trace_ctx_start = ABSOLUTE(.);
|
||||
*(.trace_ctx)
|
||||
_trace_ctx_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.gna_model)
|
||||
*(NonCacheable)
|
||||
__data_end = ABSOLUTE(.);
|
||||
. = ALIGN(4096);
|
||||
} >adsp_data :adsp_data_phdr
|
||||
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >adsp_data :adsp_data_phdr
|
||||
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >adsp_data :adsp_data_phdr
|
||||
|
||||
.heap_mem (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_heap_mem_start = ABSOLUTE(.);
|
||||
*(*.heap_mem)
|
||||
_heap_mem_end = ABSOLUTE(.);
|
||||
|
||||
} >adsp_data :adsp_data_phdr
|
||||
|
||||
/* stack */
|
||||
_end = ALIGN (8);
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
_heap_sentry = DATA_BASE + DATA_SIZE;
|
||||
__stack = DATA_BASE + DATA_SIZE;
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
}
|
111
soc/nxp/imxrt/imxrt6xx/hifi4/soc.c
Normal file
111
soc/nxp/imxrt/imxrt6xx/hifi4/soc.c
Normal file
|
@ -0,0 +1,111 @@
|
|||
/**
|
||||
* Copyright 2025 NXP
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/platform/hooks.h>
|
||||
#include <fsl_common.h>
|
||||
#include <fsl_clock.h>
|
||||
#include <fsl_inputmux.h>
|
||||
|
||||
#define BOARD_XTAL_SYS_CLK_HZ 24000000U
|
||||
|
||||
__weak void mimxrt685s_hifi4_irq_init(void)
|
||||
{
|
||||
/**
|
||||
* IRQ assignments
|
||||
*
|
||||
* L1: (lowest priority)
|
||||
* - IRQ 5 (SEL 0): Flexcomm 0 (UART)
|
||||
* - IRQ 6 (SEL 1): I3C
|
||||
* - IRQ 7 (SEL 2): GPIO_INT0_IRQ0
|
||||
* - IRQ 8 (SEL 3): GPIO_INT0_IRQ1
|
||||
* - IRQ 9 (SEL 4): GPIO_INT0_IRQ2
|
||||
* - IRQ 10 (SEL 5): GPIO_INT0_IRQ3
|
||||
* - IRQ 11 (SEL 6): GPIO_INT0_IRQ4
|
||||
* - IRQ 12 (SEL 7): GPIO_INT0_IRQ5
|
||||
* - IRQ 13 (SEL 8): GPIO_INT0_IRQ6
|
||||
* - IRQ 14 (SEL 9): GPIO_INT0_IRQ7
|
||||
* - IRQ 15 (SEL 10): HSGPIO_INT0
|
||||
*
|
||||
* L2:
|
||||
* - IRQ 16 (SEL 11): MRT0
|
||||
* - IRQ 17 (SEL 12): WDT1
|
||||
* - IRQ 18 (SEL 13): RTC
|
||||
* - IRQ 19 (SEL 14): CT32BIT0
|
||||
* - IRQ 20 (SEL 15): CT32BIT1
|
||||
* - IRQ 21 (SEL 16): CT32BIT2
|
||||
* - IRQ 22 (SEL 17): CT32BIT3
|
||||
* - IRQ 23 (SEL 18): CT32BIT4
|
||||
*
|
||||
* L3: (highest priority)
|
||||
* - IRQ 24 (SEL 19): UTICK0
|
||||
* - IRQ 25 (SEL 20): HWVAD0
|
||||
* - IRQ 26 (SEL 21): Flexcomm 5 (SPI)
|
||||
* - IRQ 27 (SEL 22): MU
|
||||
* - IRQ 28 (SEL 23): DMIC
|
||||
* - IRQ 29 (SEL 24): DMA1
|
||||
* - IRQ 30 (SEL 25): Flexcomm 3 (I2S TX)
|
||||
* - IRQ 31 (SEL 26): Flexcomm 1 (I2S RX)
|
||||
*/
|
||||
|
||||
INPUTMUX_Init(INPUTMUX);
|
||||
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 0, kINPUTMUX_Flexcomm0ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 1, kINPUTMUX_I3c0ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioInt0ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 3, kINPUTMUX_GpioInt1ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 4, kINPUTMUX_GpioInt2ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 5, kINPUTMUX_GpioInt3ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 6, kINPUTMUX_GpioInt4ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 7, kINPUTMUX_GpioInt5ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 8, kINPUTMUX_GpioInt6ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 9, kINPUTMUX_GpioInt7ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 10, kINPUTMUX_NsHsGpioInt0ToDspInterrupt);
|
||||
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 11, kINPUTMUX_Mrt0ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 12, kINPUTMUX_Wdt1ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 13, kINPUTMUX_RtcToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 14, kINPUTMUX_Ctimer0ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 15, kINPUTMUX_Ctimer1ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 16, kINPUTMUX_Ctimer2ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 17, kINPUTMUX_Ctimer3ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 18, kINPUTMUX_Ctimer4ToDspInterrupt);
|
||||
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 19, kINPUTMUX_Utick0ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 20, kINPUTMUX_Hwvad0ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 21, kINPUTMUX_Flexcomm5ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 22, kINPUTMUX_MuBToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 23, kINPUTMUX_Dmic0ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 24, kINPUTMUX_Dmac1ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 25, kINPUTMUX_Flexcomm3ToDspInterrupt);
|
||||
INPUTMUX_AttachSignal(INPUTMUX, 26, kINPUTMUX_Flexcomm1ToDspInterrupt);
|
||||
|
||||
INPUTMUX_Deinit(INPUTMUX);
|
||||
}
|
||||
|
||||
void soc_early_init_hook(void)
|
||||
{
|
||||
CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ);
|
||||
CLOCK_EnableClock(kCLOCK_Dmac1);
|
||||
|
||||
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay) && CONFIG_I2S)
|
||||
/* attach AUDIO PLL clock to FLEXCOMM1 (I2S_PDM) */
|
||||
CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1);
|
||||
#endif
|
||||
|
||||
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay) && CONFIG_I2S)
|
||||
/* attach AUDIO PLL clock to FLEXCOMM1 (I2S_PDM) */
|
||||
CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3);
|
||||
#endif
|
||||
|
||||
#if CONFIG_AUDIO_CODEC_WM8904
|
||||
/* attach AUDIO PLL clock to MCLK */
|
||||
CLOCK_AttachClk(kAUDIO_PLL_to_MCLK_CLK);
|
||||
CLOCK_SetClkDiv(kCLOCK_DivMclkClk, 1);
|
||||
SYSCTL1->MCLKPINDIR = SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK;
|
||||
#endif
|
||||
|
||||
mimxrt685s_hifi4_irq_init();
|
||||
}
|
|
@ -38,6 +38,7 @@ family:
|
|||
- name: mimxrt685s
|
||||
cpuclusters:
|
||||
- name: cm33
|
||||
- name: hifi4
|
||||
- name: imxrt7xx
|
||||
socs:
|
||||
- name: mimxrt798s
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue