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soc: cyw20829: Use python script to generate app header

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Instead of using app_header.c generate the app header using python
script and merge with final binary post build

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This commit is contained in:
Sreeram Tatapudi 2025-05-20 16:37:31 -07:00 • committed by Benjamin Cabé
commit 7ef83fca97
8 changed files with 344 additions and 146 deletions
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2
boards/infineon/cyw920829m2evk_02/board.cmake
View file

@ -18,3 +18,5 @@ endif()
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
board_runner_args(jlink "--device=CYW20829_tm")
include (${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
set_property(TARGET runners_yaml_props_target PROPERTY hex_file zephyr_merged.hex)

39
dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi
View file

@ -7,6 +7,9 @@
#include <mem.h>
#define BOOTSTRAP_SIZE DT_SIZE_K(12)
#define SRAM0_SIZE (DT_SIZE_K(256) - BOOTSTRAP_SIZE)
/ {
cpus {
#address-cells = <1>;
@ -35,14 +38,46 @@
};
sram0: memory@20000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(244)>;
reg = <0x20000000 SRAM0_SIZE>;
/* SRAM aliased address path */
sram_sahb: sram_bus_alias@20000000 {
reg = <0x20000000 SRAM0_SIZE>; /* SAHB address */
};
sram_cbus: sram_bus_alias@4000000 {
reg = <0x04000000 SRAM0_SIZE>; /* CBUS address */
};
};
/* sram_bootstrap address calculation:
* sram_sahb + sram_size (256k) - bootstrap size
* (e.g. 0x20000000 + 0x40000 - 12K (0x3000) = 0x2003D000)
*/
sram_bootstrap: memory@2003D000 {
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "BOOTSTRAP_RAM";
reg = <0x2003D000 DT_SIZE_K(12)>;
reg = <0x2003D000 BOOTSTRAP_SIZE>;
};
qspi_flash: qspi_flash@40890000 {
compatible = "infineon,cat1-qspi-flash";
reg = <0x40890000 0x30000>;
#address-cells = <1>;
#size-cells = <1>;
};
/* Flash aliased address path */
flash_sahb: flash_bus_alias@60000000 {
reg = <0x60000000 0x80000>; /* SAHB address */
};
flash_cbus: flash_bus_alias@8000000 {
reg = <0x08000000 0x80000>; /* CBUS address */
};
soc {

34
soc/infineon/cat1b/cyw20829/CMakeLists.txt
View file

@ -1,8 +1,7 @@
# Copyright (c) 2023 Cypress Semiconductor Corporation.
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(soc.c)
zephyr_sources(app_header.c)
zephyr_sources(mpu_regions.c)
zephyr_include_directories(.)
@ -19,3 +18,34 @@ zephyr_compile_definitions(CY_PDL_FLASH_BOOT)
# Use custome linker script
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/soc/infineon/cat1b/cyw20829/linker.ld CACHE INTERNAL "")
# Get sram_bootstrap address and size
dt_nodelabel(sram_bootstrap NODELABEL "sram_bootstrap")
dt_reg_addr(bootstrap_dst_addr PATH ${sram_bootstrap})
dt_reg_size(bootstrap_size PATH ${sram_bootstrap})
# Calculate the place in flash
math(EXPR flash_addr_offset
"${CONFIG_CYW20829_FLASH_SAHB_ADDR} + ${CONFIG_FLASH_LOAD_OFFSET} + ${CONFIG_ROM_START_OFFSET}"
OUTPUT_FORMAT HEXADECIMAL
)
set(gen_app_header_args --flash_addr_offset ${flash_addr_offset})
# Generate platform specific header (TOC2, l1_desc, etc)
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND
${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/infineon/cat1b/cyw20829/gen_app_header.py
-p ${ZEPHYR_BINARY_DIR} -n ${KERNEL_NAME} ${gen_app_header_args}
--bootstrap-size ${bootstrap_size}
--bootstrap-dst-addr ${bootstrap_dst_addr}
)
set(MERGED_FILE ${CMAKE_BINARY_DIR}/zephyr/zephyr_merged.hex CACHE PATH "merged hex")
# Merge platform specific header and zephyr image to a single binary.
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py
-o ${MERGED_FILE}
${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.hex ${ZEPHYR_BINARY_DIR}/app_header.hex
)
set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts ${MERGED_FILE})

16
soc/infineon/cat1b/cyw20829/Kconfig
View file

@ -16,3 +16,19 @@ config SOC_SERIES_CYW20829
select BUILD_OUTPUT_HEX
select BUILD_OUTPUT_BIN
select SOC_EARLY_INIT_HOOK
config CYW20829_FLASH_SAHB_ADDR
hex
default $(dt_nodelabel_reg_addr_hex,flash_sahb)
config CYW20829_FLASH_CBUS_ADDR
hex
default $(dt_nodelabel_reg_addr_hex,flash_cbus)
config CYW20829_SRAM_SAHB_ADDR
hex
default $(dt_nodelabel_reg_addr_hex,sram_sahb)
config CYW20829_SRAM_CBUS_ADDR
hex
default $(dt_nodelabel_reg_addr_hex,sram_cbus)

45
soc/infineon/cat1b/cyw20829/app_header.c
View file

@ -1,45 +0,0 @@
/* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/toolchain.h>
#include <stdint.h>
struct toc2_data {
uint32_t toc2_size;
uint32_t l1_app_descr_addr;
uint32_t service_app_descr_addr;
uint32_t debug_cert_addr;
} __packed;
struct l1_desc {
uint32_t l1_app_descr_size;
uint32_t boot_strap_addr;
uint32_t boot_strap_dst_addr;
uint32_t boot_strap_size;
uint32_t reserved[3];
} __packed;
struct l1_usr_app_hdr {
uint8_t reserved[32];
} __packed;
struct app_header {
struct toc2_data toc2_data;
struct l1_desc l1_desc;
uint8_t padding[4];
struct l1_usr_app_hdr l1_usr_app_hdr;
} __packed;
const struct app_header app_header Z_GENERIC_SECTION(.app_header) = {
.toc2_data = {.toc2_size = sizeof(struct toc2_data),
.l1_app_descr_addr = offsetof(struct app_header, l1_desc)},
.l1_desc = {.l1_app_descr_size = sizeof(struct l1_desc),
.boot_strap_addr = DT_REG_ADDR(DT_NODELABEL(bootstrap_region)) -
DT_REG_ADDR(DT_NODELABEL(flash0)),
.boot_strap_dst_addr = DT_REG_ADDR(DT_NODELABEL(sram_bootstrap)),
.boot_strap_size = DT_REG_SIZE(DT_NODELABEL(sram_bootstrap))},
};

32
soc/infineon/cat1b/cyw20829/bootstrap.ld
View file

@ -1,18 +1,13 @@
/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
/* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
SECTIONS
{
.app_header :
{
KEEP(*(.app_header))
} > APP_HEADER_FLASH
/* Cortex-M33 bootstrap code area */
.bootstrapText :
/* Cortex-M33 bootstrap code area */
bootstrap.text_lma = BS_CODE_LMA_CBUS;
bootstrap.text_vma = BS_CODE_VMA_CBUS;
.bootstrapText (bootstrap.text_vma) : AT (bootstrap.text_lma)
{
. = ALIGN(4);
__bootstrapText_begin = .;
@ -49,9 +44,11 @@ SECTIONS
. = ALIGN(4);
__bootstrapText_end = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
}
.bootstrapzero.table :
bootstrap.zerotable.vma = (__bootstrapText_end);
bootstrap.zerotable.lma = (bootstrap.text_lma + (__bootstrapText_end - __bootstrapText_begin));
.bootstrapzero.table (bootstrap.zerotable.vma): AT (bootstrap.zerotable.lma)
{
. = ALIGN(4);
__bootstrapzero_table_start__ = .;
@ -59,9 +56,11 @@ SECTIONS
LONG ((__bootstrap_bss_end__ - __bootstrap_bss_start__)/4)
. = ALIGN(4);
__bootstrapzero_table_end__ = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
}
.bootstrapData :
bootstrap.data.vma = ((__bootstrapzero_table_end__ - RAM_START_ADDR_CBUS) + RAM_START_ADDR_SAHB); /* CBUS -> SAHB */
bootstrap.data.lma = (bootstrap.zerotable.lma + (__bootstrapzero_table_end__ - __bootstrapzero_table_start__));
.bootstrapData (bootstrap.data.vma): AT (bootstrap.data.lma)
{
__bootstrapData_start__ = .;
. = ALIGN(4);
@ -85,9 +84,9 @@ SECTIONS
. = ALIGN(4);
__bootstrapData_end__ = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
} > BOOTSTRAP_RAM
.bootstrapBss (NOLOAD):
.bootstrapBss (__bootstrapData_end__) (NOLOAD):
{
. = ALIGN(4);
__bootstrap_bss_start__ = .;
@ -111,4 +110,3 @@ SECTIONS
. = ALIGN(4);
__bootstrap_bss_end__ = .;
} > BOOTSTRAP_RAM
}

139
soc/infineon/cat1b/cyw20829/gen_app_header.py Normal file
View file

@ -0,0 +1,139 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
import argparse
import ctypes
import sys
from pathlib import Path
from intelhex import bin2hex
# Const
TOC2_SIZE = 16
L1_APP_DESCR_SIZE = 28
L1_APP_DESCR_ADDR = 0x10
DEBUG_CERT_ADDR = 0x0
SERV_APP_DESCR_ADDR = 0x0
DEBUG = False
# Define the structures
class TOC2Data(ctypes.Structure):
_fields_ = [
("toc2_size", ctypes.c_uint32),
("l1_app_descr_addr", ctypes.c_uint32),
("service_app_descr_addr", ctypes.c_uint32),
("debug_cert_addr", ctypes.c_uint32),
]
class L1Desc(ctypes.Structure):
_fields_ = [
("l1_app_descr_size", ctypes.c_uint32),
("boot_strap_addr", ctypes.c_uint32),
("boot_strap_dst_addr", ctypes.c_uint32),
("boot_strap_size", ctypes.c_uint32),
("smif_crypto_cfg", ctypes.c_uint8 * 12),
("reserve", ctypes.c_uint8 * 4),
]
class SignHeader(ctypes.Structure):
_fields_ = [
("reserved", ctypes.c_uint8 * 32), # 32b for sign header
]
def generate_platform_headers(
secure_lcs,
output_path,
project_name,
bootstrap_size,
bootstrap_dst_addr,
flash_addr_offset,
smif_config,
):
######################### Generate TOC2 #########################
toc2_data = TOC2Data(
toc2_size=TOC2_SIZE,
l1_app_descr_addr=L1_APP_DESCR_ADDR,
service_app_descr_addr=SERV_APP_DESCR_ADDR,
debug_cert_addr=DEBUG_CERT_ADDR,
)
###################### Generate L1_APP_DESCR ####################
if secure_lcs:
boot_strap_addr = 0x30 # Fix address for signed image
else:
boot_strap_addr = 0x50 # Fix address for un-signed image
l1_desc = L1Desc(
l1_app_descr_size=L1_APP_DESCR_SIZE,
boot_strap_addr=boot_strap_addr,
boot_strap_dst_addr=int(bootstrap_dst_addr, 16),
boot_strap_size=int(bootstrap_size, 16),
)
if smif_config:
with open(smif_config, 'rb') as binary_file:
l1_desc.smif_crypto_cfg[0:] = binary_file.read()
# Write the structure to a binary file
with open(Path(output_path) / 'app_header.bin', 'wb') as f:
f.write(bytearray(toc2_data))
f.write(bytearray(l1_desc))
if not secure_lcs:
f.write(bytearray(SignHeader()))
# Generate hex from bin
sys.exit(
bin2hex(
Path(output_path) / 'app_header.bin',
Path(output_path) / 'app_header.hex',
int(flash_addr_offset, 16),
)
)
def main():
parser = argparse.ArgumentParser(allow_abbrev=False)
parser.add_argument(
'-m',
'--secure_lcs',
required=False,
type=bool,
default=False,
help='Use SECURE Life Cycle stage: True/False',
)
parser.add_argument('-p', '--project-path', required=True, help='path to application artifacts')
parser.add_argument('-n', '--project-name', required=True, help='Application name')
parser.add_argument('-k', '--keys', required=False, help='Path to keys')
parser.add_argument('--bootstrap-size', required=False, help='Bootstrap size')
parser.add_argument(
'--bootstrap-dst-addr',
required=False,
help='Bootstrap destanation address. Should be in RAM (SAHB)',
)
parser.add_argument('--flash_addr_offset', required=False, help='Flash offset')
parser.add_argument('-s', '--smif-config', required=False, help='smif config file')
args = parser.parse_args()
generate_platform_headers(
args.secure_lcs,
args.project_path,
args.project_name,
args.bootstrap_size,
args.bootstrap_dst_addr,
args.flash_addr_offset,
args.smif_config,
)
if __name__ == '__main__':
main()

183
soc/infineon/cat1b/cyw20829/linker.ld
View file

@ -64,33 +64,56 @@ _region_min_align = 4;
#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
#define MPU_ALIGN(region_size) \
. = ALIGN(_region_min_align); \
. = ALIGN( 1 << LOG2CEIL(region_size))
. = ALIGN(_region_min_align); \
. = ALIGN( 1 << LOG2CEIL(region_size))
#else
#define MPU_ALIGN(region_size) \
. = ALIGN(_region_min_align)
. = ALIGN(_region_min_align)
#endif
#define BOOTSTRAP_REGION BOOTSTRAP_FLASH
/* Maximum bootstrap code + data size */
#define BOOTSTRAP_REGION_SIZE DT_REG_SIZE(DT_NODELABEL(bootstrap_region))
#define USER_APP_START_OFFSET (CONFIG_FLASH_LOAD_OFFSET + CONFIG_ROM_START_OFFSET)
#define FLASH_START_ADDR_CBUS (CONFIG_CYW20829_FLASH_CBUS_ADDR + USER_APP_START_OFFSET)
#define FLASH_START_ADDR_SAHB (CONFIG_CYW20829_FLASH_SAHB_ADDR + USER_APP_START_OFFSET)
#define RAM_START_ADDR_CBUS CONFIG_CYW20829_SRAM_CBUS_ADDR /* 0x04000000 */
#define RAM_START_ADDR_SAHB CONFIG_CYW20829_SRAM_SAHB_ADDR /* 0x20000000 */
#define BOOTSTRAP_OFFSET_FLASH 0x00000050 /* toc2=0x10, l1_desc=0x1C, sign_header=0x20 */
/* vma for bootstrap code region */
#define BS_CODE_VMA_CBUS RAM_START_ADDR_CBUS + (DT_REG_ADDR(DT_NODELABEL(sram_bootstrap)) - RAM_START_ADDR_SAHB)
#define BS_CODE_VMA_SAHB DT_REG_ADDR(DT_NODELABEL(sram_bootstrap))
/* lma for bootstrap code region */
#define BS_CODE_LMA_CBUS FLASH_START_ADDR_CBUS + BOOTSTRAP_OFFSET_FLASH
#define BS_CODE_LMA_SAHB FLASH_START_ADDR_SAHB + BOOTSTRAP_OFFSET_FLASH
#include <zephyr/linker/linker-devnull.h>
MEMORY
{
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
{
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
#if defined(CONFIG_LINKER_DEVNULL_MEMORY)
DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE
DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE
#endif
LINKER_DT_REGIONS()
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFF7FFF, LENGTH = 32K
}
LINKER_DT_REGIONS()
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFF7FFF, LENGTH = 32K
}
ENTRY(CONFIG_KERNEL_ENTRY)
#include <bootstrap.ld>
SECTIONS
{
{
#include <zephyr/linker/rel-sections.ld>
@ -98,27 +121,28 @@ SECTIONS
#include <zephyr/linker/llext-sections.ld>
#endif
/*
* .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
* before text section.
*/
/DISCARD/ :
/*
* .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
* before text section.
*/
/DISCARD/ :
{
*(.plt)
}
/DISCARD/ :
/DISCARD/ :
{
*(.iplt)
}
GROUP_START(ROMABLE_REGION)
GROUP_START(ROMABLE_REGION)
__rom_region_start = ROM_ADDR;
SECTION_PROLOGUE(rom_start,,)
#include <bootstrap.ld>
SECTION_PROLOGUE(rom_start,(ROM_ADDR + BOOTSTRAP_REGION_SIZE + BOOTSTRAP_OFFSET_FLASH),)
{
. = 0x4;
. = ALIGN(4);
} GROUP_LINK_IN(ROMABLE_REGION)
@ -128,10 +152,9 @@ SECTIONS
#endif /* CONFIG_CODE_DATA_RELOCATION */
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{
__text_region_start = .;
#include <zephyr/linker/kobject-text.ld>
*(.text)
@ -180,7 +203,7 @@ SECTIONS
#include <zephyr/linker/common-rom.ld>
#include <zephyr/linker/thread-local-storage.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
*(.rodata)
*(".rodata.*")
@ -209,12 +232,12 @@ SECTIONS
#include <zephyr/linker/cplusplus-rom.ld>
#if defined(CONFIG_BUILD_ALIGN_LMA)
/*
* Include a padding section here to make sure that the LMA address
* of the sections in the RAMABLE_REGION are aligned with those
* section's VMA alignment requirements.
*/
SECTION_PROLOGUE(padding_section,,)
/*
* Include a padding section here to make sure that the LMA address
* of the sections in the RAMABLE_REGION are aligned with those
* section's VMA alignment requirements.
*/
SECTION_PROLOGUE(padding_section,,)
{
__rodata_region_end = .;
MPU_ALIGN(__rodata_region_end - ADDR(rom_start));
@ -225,20 +248,20 @@ SECTIONS
#endif
__rom_region_end = __rom_region_start + . - ADDR(rom_start);
GROUP_END(ROMABLE_REGION)
GROUP_END(ROMABLE_REGION)
/*
* These are here according to 'arm-zephyr-elf-ld --verbose',
* before data section.
*/
/DISCARD/ : {
/*
* These are here according to 'arm-zephyr-elf-ld --verbose',
* before data section.
*/
/DISCARD/ : {
*(.got.plt)
*(.igot.plt)
*(.got)
*(.igot)
}
GROUP_START(RAMABLE_REGION)
GROUP_START(RAMABLE_REGION)
. = RAM_ADDR;
/* Align the start of image RAM with the
@ -261,13 +284,13 @@ SECTIONS
_app_smem_size = _app_smem_end - _app_smem_start;
_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
__kernel_ram_start = .;
@ -280,9 +303,9 @@ SECTIONS
#include <linker_sram_bss_relocate.ld>
#endif
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
__bss_end = ALIGN(4);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
@ -291,9 +314,9 @@ SECTIONS
#endif /* CONFIG_USERSPACE */
GROUP_START(DATA_REGION)
GROUP_START(DATA_REGION)
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
{
__data_region_start = .;
__data_start = .;
@ -312,10 +335,10 @@ SECTIONS
__data_end = .;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
__data_size = __data_end - __data_start;
__data_load_start = LOADADDR(_DATA_SECTION_NAME);
__data_size = __data_end - __data_start;
__data_load_start = LOADADDR(_DATA_SECTION_NAME);
__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
#include <zephyr/linker/common-ram.ld>
#include <zephyr/linker/kobject-data.ld>
@ -327,16 +350,16 @@ SECTIONS
*/
#include <snippets-data-sections.ld>
__data_region_end = .;
__data_region_end = .;
#ifndef CONFIG_USERSPACE
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
__kernel_ram_start = .;
@ -349,21 +372,21 @@ SECTIONS
#include <linker_sram_bss_relocate.ld>
#endif
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
__bss_end = ALIGN(4);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
{
/*
* This section is used for non-initialized objects that
* will not be cleared during the boot process.
*/
*(.noinit)
*(".noinit.*")
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
{
/*
* This section is used for non-initialized objects that
* will not be cleared during the boot process.
*/
*(.noinit)
*(".noinit.*")
*(".kernel_noinit.*")
/* Located in generated directory. This file is populated by the
@ -371,13 +394,13 @@ SECTIONS
*/
#include <snippets-noinit.ld>
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#endif /* CONFIG_USERSPACE */
/* Define linker symbols */
/* Define linker symbols */
__kernel_ram_end = RAM_ADDR + RAM_SIZE;
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
__kernel_ram_end = RAM_ADDR + RAM_SIZE;
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
GROUP_START(ITCM)
@ -448,20 +471,20 @@ GROUP_END(DTCM)
#include <zephyr/linker/ram-end.ld>
GROUP_END(RAMABLE_REGION)
GROUP_END(RAMABLE_REGION)
#include <zephyr/linker/debug-sections.ld>
/DISCARD/ : { *(.note.GNU-stack) }
/DISCARD/ : { *(.note.GNU-stack) }
SECTION_PROLOGUE(.ARM.attributes, 0,)
SECTION_PROLOGUE(.ARM.attributes, 0,)
{
KEEP(*(.ARM.attributes))
KEEP(*(.gnu.attributes))
}
/* Sections generated from 'zephyr,memory-region' nodes */
LINKER_DT_SECTIONS()
/* Sections generated from 'zephyr,memory-region' nodes */
LINKER_DT_SECTIONS()
/* Must be last in romable region */
SECTION_PROLOGUE(.last_section,,)
@ -475,4 +498,4 @@ SECTION_PROLOGUE(.last_section,,)
* calculate this value here. */
_flash_used = LOADADDR(.last_section) + SIZEOF(.last_section) - __rom_region_start;
}
}