soc: cyw20829: Use python script to generate app header
Instead of using app_header.c generate the app header using python script and merge with final binary post build Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This commit is contained in:
parent
3d26d4cc87
commit
7ef83fca97
8 changed files with 344 additions and 146 deletions
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@ -18,3 +18,5 @@ endif()
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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board_runner_args(jlink "--device=CYW20829_tm")
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include (${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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set_property(TARGET runners_yaml_props_target PROPERTY hex_file zephyr_merged.hex)
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@ -7,6 +7,9 @@
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#include <mem.h>
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#define BOOTSTRAP_SIZE DT_SIZE_K(12)
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#define SRAM0_SIZE (DT_SIZE_K(256) - BOOTSTRAP_SIZE)
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/ {
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cpus {
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#address-cells = <1>;
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@ -35,14 +38,46 @@
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};
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sram0: memory@20000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(244)>;
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reg = <0x20000000 SRAM0_SIZE>;
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/* SRAM aliased address path */
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sram_sahb: sram_bus_alias@20000000 {
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reg = <0x20000000 SRAM0_SIZE>; /* SAHB address */
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};
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sram_cbus: sram_bus_alias@4000000 {
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reg = <0x04000000 SRAM0_SIZE>; /* CBUS address */
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};
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};
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/* sram_bootstrap address calculation:
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* sram_sahb + sram_size (256k) - bootstrap size
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* (e.g. 0x20000000 + 0x40000 - 12K (0x3000) = 0x2003D000)
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*/
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sram_bootstrap: memory@2003D000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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zephyr,memory-region = "BOOTSTRAP_RAM";
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reg = <0x2003D000 DT_SIZE_K(12)>;
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reg = <0x2003D000 BOOTSTRAP_SIZE>;
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};
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qspi_flash: qspi_flash@40890000 {
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compatible = "infineon,cat1-qspi-flash";
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reg = <0x40890000 0x30000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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/* Flash aliased address path */
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flash_sahb: flash_bus_alias@60000000 {
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reg = <0x60000000 0x80000>; /* SAHB address */
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};
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flash_cbus: flash_bus_alias@8000000 {
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reg = <0x08000000 0x80000>; /* CBUS address */
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};
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soc {
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@ -1,8 +1,7 @@
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# Copyright (c) 2023 Cypress Semiconductor Corporation.
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# Copyright (c) 2024 Cypress Semiconductor Corporation.
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(soc.c)
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zephyr_sources(app_header.c)
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zephyr_sources(mpu_regions.c)
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zephyr_include_directories(.)
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@ -19,3 +18,34 @@ zephyr_compile_definitions(CY_PDL_FLASH_BOOT)
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# Use custome linker script
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/soc/infineon/cat1b/cyw20829/linker.ld CACHE INTERNAL "")
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# Get sram_bootstrap address and size
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dt_nodelabel(sram_bootstrap NODELABEL "sram_bootstrap")
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dt_reg_addr(bootstrap_dst_addr PATH ${sram_bootstrap})
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dt_reg_size(bootstrap_size PATH ${sram_bootstrap})
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# Calculate the place in flash
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math(EXPR flash_addr_offset
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"${CONFIG_CYW20829_FLASH_SAHB_ADDR} + ${CONFIG_FLASH_LOAD_OFFSET} + ${CONFIG_ROM_START_OFFSET}"
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OUTPUT_FORMAT HEXADECIMAL
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)
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set(gen_app_header_args --flash_addr_offset ${flash_addr_offset})
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# Generate platform specific header (TOC2, l1_desc, etc)
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND
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${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/infineon/cat1b/cyw20829/gen_app_header.py
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-p ${ZEPHYR_BINARY_DIR} -n ${KERNEL_NAME} ${gen_app_header_args}
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--bootstrap-size ${bootstrap_size}
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--bootstrap-dst-addr ${bootstrap_dst_addr}
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)
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set(MERGED_FILE ${CMAKE_BINARY_DIR}/zephyr/zephyr_merged.hex CACHE PATH "merged hex")
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# Merge platform specific header and zephyr image to a single binary.
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py
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-o ${MERGED_FILE}
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${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.hex ${ZEPHYR_BINARY_DIR}/app_header.hex
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)
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set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts ${MERGED_FILE})
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@ -16,3 +16,19 @@ config SOC_SERIES_CYW20829
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select BUILD_OUTPUT_HEX
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select BUILD_OUTPUT_BIN
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select SOC_EARLY_INIT_HOOK
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config CYW20829_FLASH_SAHB_ADDR
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hex
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default $(dt_nodelabel_reg_addr_hex,flash_sahb)
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config CYW20829_FLASH_CBUS_ADDR
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hex
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default $(dt_nodelabel_reg_addr_hex,flash_cbus)
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config CYW20829_SRAM_SAHB_ADDR
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hex
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default $(dt_nodelabel_reg_addr_hex,sram_sahb)
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config CYW20829_SRAM_CBUS_ADDR
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hex
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default $(dt_nodelabel_reg_addr_hex,sram_cbus)
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@ -1,45 +0,0 @@
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/* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/toolchain.h>
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#include <stdint.h>
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struct toc2_data {
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uint32_t toc2_size;
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uint32_t l1_app_descr_addr;
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uint32_t service_app_descr_addr;
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uint32_t debug_cert_addr;
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} __packed;
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struct l1_desc {
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uint32_t l1_app_descr_size;
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uint32_t boot_strap_addr;
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uint32_t boot_strap_dst_addr;
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uint32_t boot_strap_size;
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uint32_t reserved[3];
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} __packed;
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struct l1_usr_app_hdr {
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uint8_t reserved[32];
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} __packed;
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struct app_header {
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struct toc2_data toc2_data;
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struct l1_desc l1_desc;
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uint8_t padding[4];
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struct l1_usr_app_hdr l1_usr_app_hdr;
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} __packed;
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const struct app_header app_header Z_GENERIC_SECTION(.app_header) = {
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.toc2_data = {.toc2_size = sizeof(struct toc2_data),
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.l1_app_descr_addr = offsetof(struct app_header, l1_desc)},
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.l1_desc = {.l1_app_descr_size = sizeof(struct l1_desc),
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.boot_strap_addr = DT_REG_ADDR(DT_NODELABEL(bootstrap_region)) -
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DT_REG_ADDR(DT_NODELABEL(flash0)),
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.boot_strap_dst_addr = DT_REG_ADDR(DT_NODELABEL(sram_bootstrap)),
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.boot_strap_size = DT_REG_SIZE(DT_NODELABEL(sram_bootstrap))},
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};
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@ -1,18 +1,13 @@
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/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
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/* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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SECTIONS
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{
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.app_header :
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{
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KEEP(*(.app_header))
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} > APP_HEADER_FLASH
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/* Cortex-M33 bootstrap code area */
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.bootstrapText :
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/* Cortex-M33 bootstrap code area */
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bootstrap.text_lma = BS_CODE_LMA_CBUS;
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bootstrap.text_vma = BS_CODE_VMA_CBUS;
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.bootstrapText (bootstrap.text_vma) : AT (bootstrap.text_lma)
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{
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. = ALIGN(4);
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__bootstrapText_begin = .;
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@ -49,9 +44,11 @@ SECTIONS
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. = ALIGN(4);
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__bootstrapText_end = .;
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} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
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}
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.bootstrapzero.table :
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bootstrap.zerotable.vma = (__bootstrapText_end);
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bootstrap.zerotable.lma = (bootstrap.text_lma + (__bootstrapText_end - __bootstrapText_begin));
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.bootstrapzero.table (bootstrap.zerotable.vma): AT (bootstrap.zerotable.lma)
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{
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. = ALIGN(4);
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__bootstrapzero_table_start__ = .;
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@ -59,9 +56,11 @@ SECTIONS
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LONG ((__bootstrap_bss_end__ - __bootstrap_bss_start__)/4)
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. = ALIGN(4);
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__bootstrapzero_table_end__ = .;
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} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
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}
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.bootstrapData :
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bootstrap.data.vma = ((__bootstrapzero_table_end__ - RAM_START_ADDR_CBUS) + RAM_START_ADDR_SAHB); /* CBUS -> SAHB */
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bootstrap.data.lma = (bootstrap.zerotable.lma + (__bootstrapzero_table_end__ - __bootstrapzero_table_start__));
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.bootstrapData (bootstrap.data.vma): AT (bootstrap.data.lma)
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{
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__bootstrapData_start__ = .;
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. = ALIGN(4);
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@ -85,9 +84,9 @@ SECTIONS
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. = ALIGN(4);
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__bootstrapData_end__ = .;
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} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
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} > BOOTSTRAP_RAM
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.bootstrapBss (NOLOAD):
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.bootstrapBss (__bootstrapData_end__) (NOLOAD):
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{
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. = ALIGN(4);
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__bootstrap_bss_start__ = .;
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@ -111,4 +110,3 @@ SECTIONS
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. = ALIGN(4);
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__bootstrap_bss_end__ = .;
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} > BOOTSTRAP_RAM
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}
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139
soc/infineon/cat1b/cyw20829/gen_app_header.py
Normal file
139
soc/infineon/cat1b/cyw20829/gen_app_header.py
Normal file
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@ -0,0 +1,139 @@
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# Copyright (c) 2024 Cypress Semiconductor Corporation.
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# SPDX-License-Identifier: Apache-2.0
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import argparse
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import ctypes
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import sys
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from pathlib import Path
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from intelhex import bin2hex
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# Const
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TOC2_SIZE = 16
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L1_APP_DESCR_SIZE = 28
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L1_APP_DESCR_ADDR = 0x10
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DEBUG_CERT_ADDR = 0x0
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SERV_APP_DESCR_ADDR = 0x0
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DEBUG = False
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# Define the structures
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class TOC2Data(ctypes.Structure):
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_fields_ = [
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("toc2_size", ctypes.c_uint32),
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("l1_app_descr_addr", ctypes.c_uint32),
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("service_app_descr_addr", ctypes.c_uint32),
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("debug_cert_addr", ctypes.c_uint32),
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]
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class L1Desc(ctypes.Structure):
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_fields_ = [
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("l1_app_descr_size", ctypes.c_uint32),
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("boot_strap_addr", ctypes.c_uint32),
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("boot_strap_dst_addr", ctypes.c_uint32),
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("boot_strap_size", ctypes.c_uint32),
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("smif_crypto_cfg", ctypes.c_uint8 * 12),
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("reserve", ctypes.c_uint8 * 4),
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]
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class SignHeader(ctypes.Structure):
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_fields_ = [
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("reserved", ctypes.c_uint8 * 32), # 32b for sign header
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]
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def generate_platform_headers(
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secure_lcs,
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output_path,
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project_name,
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bootstrap_size,
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bootstrap_dst_addr,
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flash_addr_offset,
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smif_config,
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):
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######################### Generate TOC2 #########################
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toc2_data = TOC2Data(
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toc2_size=TOC2_SIZE,
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l1_app_descr_addr=L1_APP_DESCR_ADDR,
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service_app_descr_addr=SERV_APP_DESCR_ADDR,
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debug_cert_addr=DEBUG_CERT_ADDR,
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)
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###################### Generate L1_APP_DESCR ####################
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if secure_lcs:
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boot_strap_addr = 0x30 # Fix address for signed image
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else:
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boot_strap_addr = 0x50 # Fix address for un-signed image
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l1_desc = L1Desc(
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l1_app_descr_size=L1_APP_DESCR_SIZE,
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boot_strap_addr=boot_strap_addr,
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boot_strap_dst_addr=int(bootstrap_dst_addr, 16),
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boot_strap_size=int(bootstrap_size, 16),
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)
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if smif_config:
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with open(smif_config, 'rb') as binary_file:
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l1_desc.smif_crypto_cfg[0:] = binary_file.read()
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# Write the structure to a binary file
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with open(Path(output_path) / 'app_header.bin', 'wb') as f:
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f.write(bytearray(toc2_data))
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f.write(bytearray(l1_desc))
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if not secure_lcs:
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f.write(bytearray(SignHeader()))
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# Generate hex from bin
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sys.exit(
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bin2hex(
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Path(output_path) / 'app_header.bin',
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Path(output_path) / 'app_header.hex',
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int(flash_addr_offset, 16),
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)
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)
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def main():
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parser = argparse.ArgumentParser(allow_abbrev=False)
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parser.add_argument(
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'-m',
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'--secure_lcs',
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required=False,
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type=bool,
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default=False,
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help='Use SECURE Life Cycle stage: True/False',
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)
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parser.add_argument('-p', '--project-path', required=True, help='path to application artifacts')
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parser.add_argument('-n', '--project-name', required=True, help='Application name')
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parser.add_argument('-k', '--keys', required=False, help='Path to keys')
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parser.add_argument('--bootstrap-size', required=False, help='Bootstrap size')
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parser.add_argument(
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'--bootstrap-dst-addr',
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required=False,
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help='Bootstrap destanation address. Should be in RAM (SAHB)',
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)
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parser.add_argument('--flash_addr_offset', required=False, help='Flash offset')
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parser.add_argument('-s', '--smif-config', required=False, help='smif config file')
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args = parser.parse_args()
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generate_platform_headers(
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args.secure_lcs,
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args.project_path,
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args.project_name,
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args.bootstrap_size,
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args.bootstrap_dst_addr,
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args.flash_addr_offset,
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args.smif_config,
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)
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if __name__ == '__main__':
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main()
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@ -64,33 +64,56 @@ _region_min_align = 4;
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#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align); \
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. = ALIGN( 1 << LOG2CEIL(region_size))
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. = ALIGN(_region_min_align); \
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. = ALIGN( 1 << LOG2CEIL(region_size))
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#else
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align)
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. = ALIGN(_region_min_align)
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#endif
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#define BOOTSTRAP_REGION BOOTSTRAP_FLASH
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/* Maximum bootstrap code + data size */
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#define BOOTSTRAP_REGION_SIZE DT_REG_SIZE(DT_NODELABEL(bootstrap_region))
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#define USER_APP_START_OFFSET (CONFIG_FLASH_LOAD_OFFSET + CONFIG_ROM_START_OFFSET)
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#define FLASH_START_ADDR_CBUS (CONFIG_CYW20829_FLASH_CBUS_ADDR + USER_APP_START_OFFSET)
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#define FLASH_START_ADDR_SAHB (CONFIG_CYW20829_FLASH_SAHB_ADDR + USER_APP_START_OFFSET)
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#define RAM_START_ADDR_CBUS CONFIG_CYW20829_SRAM_CBUS_ADDR /* 0x04000000 */
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#define RAM_START_ADDR_SAHB CONFIG_CYW20829_SRAM_SAHB_ADDR /* 0x20000000 */
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#define BOOTSTRAP_OFFSET_FLASH 0x00000050 /* toc2=0x10, l1_desc=0x1C, sign_header=0x20 */
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/* vma for bootstrap code region */
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#define BS_CODE_VMA_CBUS RAM_START_ADDR_CBUS + (DT_REG_ADDR(DT_NODELABEL(sram_bootstrap)) - RAM_START_ADDR_SAHB)
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#define BS_CODE_VMA_SAHB DT_REG_ADDR(DT_NODELABEL(sram_bootstrap))
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/* lma for bootstrap code region */
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#define BS_CODE_LMA_CBUS FLASH_START_ADDR_CBUS + BOOTSTRAP_OFFSET_FLASH
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#define BS_CODE_LMA_SAHB FLASH_START_ADDR_SAHB + BOOTSTRAP_OFFSET_FLASH
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#include <zephyr/linker/linker-devnull.h>
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MEMORY
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{
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FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
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RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
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{
|
||||
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
|
||||
RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
|
||||
|
||||
#if defined(CONFIG_LINKER_DEVNULL_MEMORY)
|
||||
DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE
|
||||
DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE
|
||||
#endif
|
||||
LINKER_DT_REGIONS()
|
||||
/* Used by and documented in include/linker/intlist.ld */
|
||||
IDT_LIST (wx) : ORIGIN = 0xFFFF7FFF, LENGTH = 32K
|
||||
}
|
||||
LINKER_DT_REGIONS()
|
||||
/* Used by and documented in include/linker/intlist.ld */
|
||||
IDT_LIST (wx) : ORIGIN = 0xFFFF7FFF, LENGTH = 32K
|
||||
}
|
||||
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
#include <bootstrap.ld>
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
{
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
|
||||
|
@ -98,27 +121,28 @@ SECTIONS
|
|||
#include <zephyr/linker/llext-sections.ld>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
|
||||
* before text section.
|
||||
*/
|
||||
/DISCARD/ :
|
||||
/*
|
||||
* .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
|
||||
* before text section.
|
||||
*/
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.plt)
|
||||
}
|
||||
|
||||
/DISCARD/ :
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.iplt)
|
||||
}
|
||||
|
||||
GROUP_START(ROMABLE_REGION)
|
||||
GROUP_START(ROMABLE_REGION)
|
||||
|
||||
__rom_region_start = ROM_ADDR;
|
||||
|
||||
SECTION_PROLOGUE(rom_start,,)
|
||||
#include <bootstrap.ld>
|
||||
SECTION_PROLOGUE(rom_start,(ROM_ADDR + BOOTSTRAP_REGION_SIZE + BOOTSTRAP_OFFSET_FLASH),)
|
||||
{
|
||||
|
||||
. = 0x4;
|
||||
. = ALIGN(4);
|
||||
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
|
||||
|
@ -128,10 +152,9 @@ SECTIONS
|
|||
|
||||
#endif /* CONFIG_CODE_DATA_RELOCATION */
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
|
||||
{
|
||||
__text_region_start = .;
|
||||
|
||||
#include <zephyr/linker/kobject-text.ld>
|
||||
|
||||
*(.text)
|
||||
|
@ -180,7 +203,7 @@ SECTIONS
|
|||
#include <zephyr/linker/common-rom.ld>
|
||||
#include <zephyr/linker/thread-local-storage.ld>
|
||||
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
*(.rodata)
|
||||
*(".rodata.*")
|
||||
|
@ -209,12 +232,12 @@ SECTIONS
|
|||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
|
||||
#if defined(CONFIG_BUILD_ALIGN_LMA)
|
||||
/*
|
||||
* Include a padding section here to make sure that the LMA address
|
||||
* of the sections in the RAMABLE_REGION are aligned with those
|
||||
* section's VMA alignment requirements.
|
||||
*/
|
||||
SECTION_PROLOGUE(padding_section,,)
|
||||
/*
|
||||
* Include a padding section here to make sure that the LMA address
|
||||
* of the sections in the RAMABLE_REGION are aligned with those
|
||||
* section's VMA alignment requirements.
|
||||
*/
|
||||
SECTION_PROLOGUE(padding_section,,)
|
||||
{
|
||||
__rodata_region_end = .;
|
||||
MPU_ALIGN(__rodata_region_end - ADDR(rom_start));
|
||||
|
@ -225,20 +248,20 @@ SECTIONS
|
|||
#endif
|
||||
__rom_region_end = __rom_region_start + . - ADDR(rom_start);
|
||||
|
||||
GROUP_END(ROMABLE_REGION)
|
||||
GROUP_END(ROMABLE_REGION)
|
||||
|
||||
/*
|
||||
* These are here according to 'arm-zephyr-elf-ld --verbose',
|
||||
* before data section.
|
||||
*/
|
||||
/DISCARD/ : {
|
||||
/*
|
||||
* These are here according to 'arm-zephyr-elf-ld --verbose',
|
||||
* before data section.
|
||||
*/
|
||||
/DISCARD/ : {
|
||||
*(.got.plt)
|
||||
*(.igot.plt)
|
||||
*(.got)
|
||||
*(.igot)
|
||||
}
|
||||
|
||||
GROUP_START(RAMABLE_REGION)
|
||||
GROUP_START(RAMABLE_REGION)
|
||||
|
||||
. = RAM_ADDR;
|
||||
/* Align the start of image RAM with the
|
||||
|
@ -261,13 +284,13 @@ SECTIONS
|
|||
_app_smem_size = _app_smem_end - _app_smem_start;
|
||||
_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
|
||||
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* For performance, BSS section is assumed to be 4 byte aligned and
|
||||
* a multiple of 4 bytes
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
/*
|
||||
* For performance, BSS section is assumed to be 4 byte aligned and
|
||||
* a multiple of 4 bytes
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
__kernel_ram_start = .;
|
||||
|
||||
|
@ -280,9 +303,9 @@ SECTIONS
|
|||
#include <linker_sram_bss_relocate.ld>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* As memory is cleared in words only, it is simpler to ensure the BSS
|
||||
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
|
||||
/*
|
||||
* As memory is cleared in words only, it is simpler to ensure the BSS
|
||||
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
|
||||
*/
|
||||
__bss_end = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
|
||||
|
@ -291,9 +314,9 @@ SECTIONS
|
|||
|
||||
#endif /* CONFIG_USERSPACE */
|
||||
|
||||
GROUP_START(DATA_REGION)
|
||||
GROUP_START(DATA_REGION)
|
||||
|
||||
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
|
||||
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
|
||||
{
|
||||
__data_region_start = .;
|
||||
__data_start = .;
|
||||
|
@ -312,10 +335,10 @@ SECTIONS
|
|||
__data_end = .;
|
||||
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
__data_size = __data_end - __data_start;
|
||||
__data_load_start = LOADADDR(_DATA_SECTION_NAME);
|
||||
__data_size = __data_end - __data_start;
|
||||
__data_load_start = LOADADDR(_DATA_SECTION_NAME);
|
||||
|
||||
__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
|
||||
__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
|
||||
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <zephyr/linker/kobject-data.ld>
|
||||
|
@ -327,16 +350,16 @@ SECTIONS
|
|||
*/
|
||||
#include <snippets-data-sections.ld>
|
||||
|
||||
__data_region_end = .;
|
||||
__data_region_end = .;
|
||||
|
||||
#ifndef CONFIG_USERSPACE
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* For performance, BSS section is assumed to be 4 byte aligned and
|
||||
* a multiple of 4 bytes
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
/*
|
||||
* For performance, BSS section is assumed to be 4 byte aligned and
|
||||
* a multiple of 4 bytes
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
__kernel_ram_start = .;
|
||||
|
||||
|
@ -349,21 +372,21 @@ SECTIONS
|
|||
#include <linker_sram_bss_relocate.ld>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* As memory is cleared in words only, it is simpler to ensure the BSS
|
||||
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
|
||||
/*
|
||||
* As memory is cleared in words only, it is simpler to ensure the BSS
|
||||
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
|
||||
*/
|
||||
__bss_end = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
|
||||
|
||||
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* This section is used for non-initialized objects that
|
||||
* will not be cleared during the boot process.
|
||||
*/
|
||||
*(.noinit)
|
||||
*(".noinit.*")
|
||||
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* This section is used for non-initialized objects that
|
||||
* will not be cleared during the boot process.
|
||||
*/
|
||||
*(.noinit)
|
||||
*(".noinit.*")
|
||||
*(".kernel_noinit.*")
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
|
@ -371,13 +394,13 @@ SECTIONS
|
|||
*/
|
||||
#include <snippets-noinit.ld>
|
||||
|
||||
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
|
||||
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
|
||||
#endif /* CONFIG_USERSPACE */
|
||||
|
||||
/* Define linker symbols */
|
||||
/* Define linker symbols */
|
||||
|
||||
__kernel_ram_end = RAM_ADDR + RAM_SIZE;
|
||||
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
|
||||
__kernel_ram_end = RAM_ADDR + RAM_SIZE;
|
||||
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
|
||||
GROUP_START(ITCM)
|
||||
|
@ -448,20 +471,20 @@ GROUP_END(DTCM)
|
|||
|
||||
#include <zephyr/linker/ram-end.ld>
|
||||
|
||||
GROUP_END(RAMABLE_REGION)
|
||||
GROUP_END(RAMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
|
||||
SECTION_PROLOGUE(.ARM.attributes, 0,)
|
||||
SECTION_PROLOGUE(.ARM.attributes, 0,)
|
||||
{
|
||||
KEEP(*(.ARM.attributes))
|
||||
KEEP(*(.gnu.attributes))
|
||||
}
|
||||
|
||||
/* Sections generated from 'zephyr,memory-region' nodes */
|
||||
LINKER_DT_SECTIONS()
|
||||
/* Sections generated from 'zephyr,memory-region' nodes */
|
||||
LINKER_DT_SECTIONS()
|
||||
|
||||
/* Must be last in romable region */
|
||||
SECTION_PROLOGUE(.last_section,,)
|
||||
|
@ -475,4 +498,4 @@ SECTION_PROLOGUE(.last_section,,)
|
|||
* calculate this value here. */
|
||||
_flash_used = LOADADDR(.last_section) + SIZEOF(.last_section) - __rom_region_start;
|
||||
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue