soc: modifications for cyw920829m2evk_02 power configuration

Added possibility to configure buck regulators according to
power profile.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This commit is contained in:
Nazar Palamar 2025-02-12 19:25:37 +02:00 committed by Benjamin Cabé
commit 4c822b7e03
3 changed files with 174 additions and 0 deletions

View file

@ -7,6 +7,13 @@
#include "clock_source_def.h"
/ {
srss_power: srss_power {
#clock-cells = <0>;
compatible = "infineon,cat1b-power";
power-profile = "POWER_PROFILE_0";
status = "okay";
};
clocks {
/* iho */
clk_iho: clk_iho {

View file

@ -0,0 +1,46 @@
# Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
#
# SPDX-License-Identifier: Apache-2.0
description: Infineon CAT1B power control
compatible: "infineon,cat1b-power"
include: base.yaml
properties:
power-profile:
type: string
description: |
Selects the System Active power profile:
- POWER_PROFILE_0 (LP MCU + Radio ON): All peripheral and CPU power modes are
available with a maximum configurable CPU clock at 96 MHz with a regulated
voltage of 1.1 V. Bluetooth® functionality is available because the radio
module is powered ON.
- POWER_PROFILE_1 (ULP MCU + Radio ON): All CPU peripherals and power modes are
available with the maximum frequency of 48 MHz and operating at 1.0 V voltage
regulation (see Regulator operations). Bluetooth® functionality is available because
the radio module is powered ON.
- POWER_PROFILE_2A (LP MCU Only): All peripheral and CPU power modes are available at
full speed (96 MHz) with a regulated voltage of 1.1 V, but Bluetooth® functionality is not
available because the radio module is in OFF state. The core buck voltage and mode are set
to high power 1.16 V and SDR0 is set to regulated 1.1 V.
- POWER_PROFILE_2B (LP MCU Only): All peripheral and CPU power modes are available at
full speed (96 MHz) with a regulated voltage of 1.1 V, but the Bluetooth® functionality is
not available because the radio module is in OFF state. The core buck voltage and mode are
set to low-power 1.1 V and SDR0 is set to bypassed 1.1 V.
- POWER_PROFILE_3 (ULP MCU Only): All CPU peripherals and power modes are available
with the maximum frequency of 48 MHz and operating with a regulated voltage of 1.0 V.
Bluetooth® radio module is turned OFF.
enum:
- "POWER_PROFILE_0"
- "POWER_PROFILE_1"
- "POWER_PROFILE_2A"
- "POWER_PROFILE_2B"
- "POWER_PROFILE_3"

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@ -16,6 +16,59 @@
#include <system_cat1b.h>
#include "cy_pdl.h"
/* Power profiles definition */
#define CY_CFG_PWR_MODE_POWER_PROFILE_0 0 /* LP MCU + Radio ON */
#define CY_CFG_PWR_MODE_POWER_PROFILE_1 1 /* ULP MCU + Radio ON */
#define CY_CFG_PWR_MODE_POWER_PROFILE_2A 2 /* LP MCU Only */
#define CY_CFG_PWR_MODE_POWER_PROFILE_2B 3 /* LP MCU Only */
#define CY_CFG_PWR_MODE_POWER_PROFILE_3 4 /* ULP MCU Only */
#define CY_CFG_PWR_SYS_ACTIVE_PROFILE \
UTIL_CAT(CY_CFG_PWR_MODE, DT_STRING_UPPER_TOKEN_OR(DT_NODELABEL(srss_power), \
power_profile, POWER_PROFILE_0))
#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
#define CY_CFG_PWR_REGULATOR_MODE_MIN 0
#define CY_CFG_PWR_SYS_LP_PROFILE_MODE 0
#define CY_CFG_PWR_SDR0_MODE_BYPASS true
#if (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_0)
#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP
#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V
#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
#define CY_CFG_PWR_SDR1_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
#define CY_CFG_PWR_SDR1_ENABLE true
#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_1)
#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP
#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V
#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_000V
#define CY_CFG_PWR_SDR1_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
#define CY_CFG_PWR_SDR1_ENABLE true
#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_2A)
#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP
#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V
#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
#define CY_CFG_PWR_SDR1_VOLT 0
#define CY_CFG_PWR_SDR1_ENABLE false
#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_2B)
#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_LP
#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_10V
#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
#define CY_CFG_PWR_SDR1_VOLT 0
#define CY_CFG_PWR_SDR1_ENABLE false
#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_3)
#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_LP
#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_00V
#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_000V
#define CY_CFG_PWR_SDR1_VOLT 0
#define CY_CFG_PWR_SDR1_ENABLE false
#else
#error CY_CFG_PWR_SYS_ACTIVE_PROFILE configured incorrectly
#endif
extern int ifx_pm_init(void);
cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddress userIsr)
@ -85,6 +138,73 @@ void disable_mpu_rasr_xn(void)
}
#endif /* CONFIG_ARM_MPU */
static cy_stc_syspm_core_buck_params_t coreBuckConfigParam = {
.voltageSel = CY_CFG_PWR_CBUCK_VOLT,
.mode = CY_CFG_PWR_CBUCK_MODE,
.override = false,
.copySettings = false,
.useSettings = false,
.inRushLimitSel = 0,
};
static cy_stc_syspm_sdr_params_t sdr0ConfigParam = {
.coreBuckVoltSel = CY_CFG_PWR_CBUCK_VOLT,
.coreBuckMode = CY_CFG_PWR_CBUCK_MODE,
.coreBuckDpSlpVoltSel = CY_SYSPM_CORE_BUCK_VOLTAGE_0_90V,
.coreBuckDpSlpMode = CY_SYSPM_CORE_BUCK_MODE_LP,
.sdr0DpSlpVoltSel = CY_SYSPM_SDR_VOLTAGE_0_900V,
.sdrVoltSel = CY_CFG_PWR_SDR0_VOLT,
.sdr0Allowbypass = CY_CFG_PWR_SDR0_MODE_BYPASS,
};
static cy_stc_syspm_sdr_params_t sdr1ConfigParam = {
.coreBuckVoltSel = CY_CFG_PWR_CBUCK_VOLT,
.coreBuckMode = CY_CFG_PWR_CBUCK_MODE,
.sdrVoltSel = CY_CFG_PWR_SDR1_VOLT,
.sdr1HwControl = true,
.sdr1Enable = true,
};
static inline void init_power(void)
{
CY_UNUSED_PARAMETER(
sdr1ConfigParam); /* Suppress a compiler warning about unused variables */
Cy_SysPm_Init();
/* **Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD** */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) {
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* **System Active Power Mode Profile Configuration** */
/* Core Buck Regulator Configuration */
Cy_SysPm_CoreBuckConfig(&coreBuckConfigParam);
/* SDR0 Regulator Configuration */
Cy_SysPm_SdrConfigure(CY_SYSPM_SDR_0, &sdr0ConfigParam);
/* SDR1 Regulator Configuration */
#if (CY_CFG_PWR_SDR1_ENABLE)
Cy_SysPm_SdrConfigure(CY_SYSPM_SDR_1, &sdr1ConfigParam);
#endif /* CY_CFG_PWR_SDR1_VOLT */
/* **System Active Low Power Profile(LPACTIVE/LPSLEEP) Configuration** */
#if (CY_CFG_PWR_SYS_LP_PROFILE_MODE)
Cy_SysPm_SystemLpActiveEnter();
#endif /* CY_CFG_PWR_SYS_LP_PROFILE_MODE */
/* **System Regulators Low Current Configuration** */
#if (CY_CFG_PWR_REGULATOR_MODE_MIN)
Cy_SysPm_SystemSetMinRegulatorCurrent();
#endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
}
void soc_early_init_hook(void)
{
#ifdef CONFIG_ARM_MPU
@ -94,6 +214,7 @@ void soc_early_init_hook(void)
/* Initializes the system */
SystemInit();
init_power();
#ifdef CONFIG_PM
ifx_pm_init();
#endif