soc: modifications for cyw920829m2evk_02 power configuration
Added possibility to configure buck regulators according to power profile. Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This commit is contained in:
Nazar Palamar
Benjamin Cabé
parent
8b5fe624e2
commit
4c822b7e03
3 changed files with 174 additions and 0 deletions
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@ -7,6 +7,13 @@
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#include "clock_source_def.h"
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/ {
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srss_power: srss_power {
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#clock-cells = <0>;
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compatible = "infineon,cat1b-power";
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power-profile = "POWER_PROFILE_0";
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status = "okay";
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};
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clocks {
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/* iho */
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clk_iho: clk_iho {
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46
dts/bindings/power/infineon,cat1b-power.yaml
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46
dts/bindings/power/infineon,cat1b-power.yaml
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@ -0,0 +1,46 @@
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# Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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description: Infineon CAT1B power control
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compatible: "infineon,cat1b-power"
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include: base.yaml
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properties:
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power-profile:
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type: string
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description: |
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Selects the System Active power profile:
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- POWER_PROFILE_0 (LP MCU + Radio ON): All peripheral and CPU power modes are
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available with a maximum configurable CPU clock at 96 MHz with a regulated
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voltage of 1.1 V. Bluetooth® functionality is available because the radio
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module is powered ON.
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- POWER_PROFILE_1 (ULP MCU + Radio ON): All CPU peripherals and power modes are
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available with the maximum frequency of 48 MHz and operating at 1.0 V voltage
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regulation (see Regulator operations). Bluetooth® functionality is available because
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the radio module is powered ON.
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- POWER_PROFILE_2A (LP MCU Only): All peripheral and CPU power modes are available at
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full speed (96 MHz) with a regulated voltage of 1.1 V, but Bluetooth® functionality is not
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available because the radio module is in OFF state. The core buck voltage and mode are set
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to high power 1.16 V and SDR0 is set to regulated 1.1 V.
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- POWER_PROFILE_2B (LP MCU Only): All peripheral and CPU power modes are available at
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full speed (96 MHz) with a regulated voltage of 1.1 V, but the Bluetooth® functionality is
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not available because the radio module is in OFF state. The core buck voltage and mode are
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set to low-power 1.1 V and SDR0 is set to bypassed 1.1 V.
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- POWER_PROFILE_3 (ULP MCU Only): All CPU peripherals and power modes are available
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with the maximum frequency of 48 MHz and operating with a regulated voltage of 1.0 V.
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Bluetooth® radio module is turned OFF.
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enum:
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- "POWER_PROFILE_0"
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- "POWER_PROFILE_1"
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- "POWER_PROFILE_2A"
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- "POWER_PROFILE_2B"
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- "POWER_PROFILE_3"
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@ -16,6 +16,59 @@
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#include <system_cat1b.h>
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#include "cy_pdl.h"
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/* Power profiles definition */
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#define CY_CFG_PWR_MODE_POWER_PROFILE_0 0 /* LP MCU + Radio ON */
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#define CY_CFG_PWR_MODE_POWER_PROFILE_1 1 /* ULP MCU + Radio ON */
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#define CY_CFG_PWR_MODE_POWER_PROFILE_2A 2 /* LP MCU Only */
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#define CY_CFG_PWR_MODE_POWER_PROFILE_2B 3 /* LP MCU Only */
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#define CY_CFG_PWR_MODE_POWER_PROFILE_3 4 /* ULP MCU Only */
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#define CY_CFG_PWR_SYS_ACTIVE_PROFILE \
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UTIL_CAT(CY_CFG_PWR_MODE, DT_STRING_UPPER_TOKEN_OR(DT_NODELABEL(srss_power), \
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power_profile, POWER_PROFILE_0))
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#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
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#define CY_CFG_PWR_REGULATOR_MODE_MIN 0
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#define CY_CFG_PWR_SYS_LP_PROFILE_MODE 0
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#define CY_CFG_PWR_SDR0_MODE_BYPASS true
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#if (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_0)
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#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP
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#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V
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#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
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#define CY_CFG_PWR_SDR1_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
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#define CY_CFG_PWR_SDR1_ENABLE true
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#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_1)
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#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP
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#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V
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#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_000V
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#define CY_CFG_PWR_SDR1_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
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#define CY_CFG_PWR_SDR1_ENABLE true
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#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_2A)
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#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP
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#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V
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#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
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#define CY_CFG_PWR_SDR1_VOLT 0
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#define CY_CFG_PWR_SDR1_ENABLE false
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#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_2B)
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#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_LP
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#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_10V
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#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
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#define CY_CFG_PWR_SDR1_VOLT 0
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#define CY_CFG_PWR_SDR1_ENABLE false
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#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_POWER_PROFILE_3)
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#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_LP
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#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_00V
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#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_000V
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#define CY_CFG_PWR_SDR1_VOLT 0
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#define CY_CFG_PWR_SDR1_ENABLE false
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#else
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#error CY_CFG_PWR_SYS_ACTIVE_PROFILE configured incorrectly
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#endif
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extern int ifx_pm_init(void);
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cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddress userIsr)
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@ -85,6 +138,73 @@ void disable_mpu_rasr_xn(void)
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}
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#endif /* CONFIG_ARM_MPU */
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static cy_stc_syspm_core_buck_params_t coreBuckConfigParam = {
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.voltageSel = CY_CFG_PWR_CBUCK_VOLT,
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.mode = CY_CFG_PWR_CBUCK_MODE,
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.override = false,
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.copySettings = false,
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.useSettings = false,
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.inRushLimitSel = 0,
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};
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static cy_stc_syspm_sdr_params_t sdr0ConfigParam = {
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.coreBuckVoltSel = CY_CFG_PWR_CBUCK_VOLT,
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.coreBuckMode = CY_CFG_PWR_CBUCK_MODE,
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.coreBuckDpSlpVoltSel = CY_SYSPM_CORE_BUCK_VOLTAGE_0_90V,
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.coreBuckDpSlpMode = CY_SYSPM_CORE_BUCK_MODE_LP,
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.sdr0DpSlpVoltSel = CY_SYSPM_SDR_VOLTAGE_0_900V,
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.sdrVoltSel = CY_CFG_PWR_SDR0_VOLT,
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.sdr0Allowbypass = CY_CFG_PWR_SDR0_MODE_BYPASS,
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};
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static cy_stc_syspm_sdr_params_t sdr1ConfigParam = {
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.coreBuckVoltSel = CY_CFG_PWR_CBUCK_VOLT,
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.coreBuckMode = CY_CFG_PWR_CBUCK_MODE,
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.sdrVoltSel = CY_CFG_PWR_SDR1_VOLT,
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.sdr1HwControl = true,
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.sdr1Enable = true,
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};
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static inline void init_power(void)
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{
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CY_UNUSED_PARAMETER(
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sdr1ConfigParam); /* Suppress a compiler warning about unused variables */
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Cy_SysPm_Init();
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/* **Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD** */
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#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
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#ifdef CY_CFG_SYSCLK_ILO_ENABLED
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if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) {
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Cy_SysLib_ResetBackupDomain();
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Cy_SysClk_IloDisable();
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Cy_SysClk_IloInit();
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}
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#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
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#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
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/* **System Active Power Mode Profile Configuration** */
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/* Core Buck Regulator Configuration */
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Cy_SysPm_CoreBuckConfig(&coreBuckConfigParam);
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/* SDR0 Regulator Configuration */
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Cy_SysPm_SdrConfigure(CY_SYSPM_SDR_0, &sdr0ConfigParam);
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/* SDR1 Regulator Configuration */
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#if (CY_CFG_PWR_SDR1_ENABLE)
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Cy_SysPm_SdrConfigure(CY_SYSPM_SDR_1, &sdr1ConfigParam);
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#endif /* CY_CFG_PWR_SDR1_VOLT */
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/* **System Active Low Power Profile(LPACTIVE/LPSLEEP) Configuration** */
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#if (CY_CFG_PWR_SYS_LP_PROFILE_MODE)
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Cy_SysPm_SystemLpActiveEnter();
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#endif /* CY_CFG_PWR_SYS_LP_PROFILE_MODE */
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/* **System Regulators Low Current Configuration** */
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#if (CY_CFG_PWR_REGULATOR_MODE_MIN)
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Cy_SysPm_SystemSetMinRegulatorCurrent();
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#endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
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}
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void soc_early_init_hook(void)
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{
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#ifdef CONFIG_ARM_MPU
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@ -94,6 +214,7 @@ void soc_early_init_hook(void)
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/* Initializes the system */
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SystemInit();
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init_power();
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#ifdef CONFIG_PM
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ifx_pm_init();
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#endif
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