esp32-mp.c calls z_sched_ipi() so it needs to include ksched.h,
as it is no longer included via kernel.h after removal of
kernel/internal/smp.h.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Port the nordicsemi_nrf53_init to use soc_early_init_hook instead of
SYS_INIT as SYS_INIT is legacy.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Intial support of pinctrl driver for Renesas RX MCU
family.
This support base on using Renesas RX driver package in
hal_renesas layer
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
for high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
Initial support of clock control driver for RX MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
The qemu-system-rx is based on RX62N, this commit added
support for the RX62N SOC layer. MCU is using RXv1 core and
system timer running at 6MHz
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
For npck3m8k:
1. Update code ram from 320KB to 416KB (0x1005_8000~0x100B_FFFF).
2. Update data ram from 32KB to 64KB.
3. Move fiudiv from hfcbcd1 to hfcbcd2 register
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace incorrect call to memc_flexram_dt_partition() with
flexram_dt_partition() to resolve build error on
IMXRT10xx and IMXRT11xx.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Configures AHBSC MASTER_SEC_LEVEL register for the cpu1 before cpu1 is
enabled. By default, this gives CPU1 secure and privileged access to
the rest of the SOC, same as CPU0.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Use `defaut y if` instead of `depends on` as the related Kconfig
should be user configurable even when standby mode is not used.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
0~12.
supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
interface 0~8.
supports 16 bytes dedicated FIFO mode that only supports write or
read mode and the maximum buffer size is 256 bytes.
support non-FIFO write to shared FIFO read mode. The maximum
shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
i2c_burst_write(), i2c_write_read()
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The buf_in_nocache function is to be used by various device drivers
to check if buffer is in noncacheable region.
The cacheable DMA buffer shall be put into section .ambiq_dma_buff
due to certain restrictions of the SoC.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
There is no need for kernel/internal/smp.h as SOF does not call
z_sched_ipi(). Actually... git log over there has no mention of
z_sched_ipi() anywhere, just arch_sched_ipi().
And include <ksched.h> for source using z_sched_ipi() since
they are using scheduling functions, and would be the correct
file to include.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This platform was previously using a default sys_arch_reboot
implementation which did nothing. Add an implementation which uses the
CRL_APB_RESET_CTRL register to initiate a soft reset (SRST) of the
device.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
MAX32657 is Cortex-M33 based Analog Devices MCU.
It supports ARM TrustZone security model.
There will be two boards of this MCU Secure and Non-Secure
This commit defines Secure version of peripherals.
Basic feature of MAX32657 device:
- Core is Cortex-M33
- 50MHz IPO clock
- There are 54 interrupt vectors
- 1MB flash & 256 SRAM
- MAX32657 has:
- 1 x UART
- 1 x I2C/I3C
- 1 x SPI
- 6 x TIMER
- 1 x RTC
- 1 x WDT
- 1 x TRNG
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
For simplicity/consistency with many other soc families, rename the
bouffalolab_bflb soc family to the simpler bflb.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Moved to: include/zephyr/drivers/misc/flexram/memc_nxp_flexram.h
This change makes it so that the .h file does not need to be pulled in
using the CMakeLists.txt file, and can be included like other public
includes.
Removes drivers/memc/memc_nxp_flexram.h
Add memc_nxp_flexram.h to include/zephyr/drivers/misc/flexram
Modify drivers/memc/memc_nxp_flexram.c to use the new include path.
Modifies the mimxrt1170 magic_addr sample to include the driver using
the new include path.
Modify the soc file: soc/nxp/imxrt/imxrt11xx/soc.c to use the new path.
Add relevant information to migration-guide-4.2.rst.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Co-authored-by: Declan Snyder <declan.snyder@nxp.com>
Disable GPD for MCUBoot build, as it cannot be
reinitialized later in application (SDFW does not
support reinitialization).
Also, remove the GPD disabling from the mcumgr sample
for nRF54H20 iron board app - it was the reinitialization
that caused problems.
Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
The symbol SRAM_VECTOR_TABLE is not used in the adi/max32 soc. Removed
it in order to clean up the Kconfig file and avoid confusion with the
upcoming new definition of SRAM_VECTOR_TABLE symbol. (PR #87468)
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Use the Zephyr cache API in soc initialization code instead of calling the
HAL directly. The change does not modify the pre-existing cache settings,
just changes the path they are enabled.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Remove the sanity check between Cube HAL SMPS symbol and Kconfig SMPS
configuration.
SMPS is available on all STM32H7R/S SoC, so misalignment isn't possible.
Additionally, point to the hal commit which revert the fix which was done
on hal_stm32 to add this symbol.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Introduces config file entries for STM32F401XD variants. The
STM32F401XD family is related to the STM32F401XE family but with a
reduced flash memory.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
