Commit graph

2589 commits

Author SHA1 Message Date
Pieter De Gendt
5bba8dd101 soc: arm: atmel_sam: sam4e: Rework clock_init
Update clock_init for the Atmel SAM4E SoC using the new PMC API.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2024-01-22 09:47:21 +00:00
Pieter De Gendt
89f23f7947 soc: arm: atmel_sam: sam3x: Rework clock_init
Update clock_init for the Atmel SAM3X SoC using the new PMC API.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2024-01-22 09:47:21 +00:00
Pieter De Gendt
a69d611de8 soc: arm: atmel_sam: sam4s: Rework clock_init
Update clock_init for the Atmel SAM4S SoC using the new PMC API.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2024-01-22 09:47:21 +00:00
Pieter De Gendt
20f1f44120 soc: arm: atmel_sam: common: Add PMC API for clock management
Add functions to Atmel SAM SoC PMC API. This is an effort to hide
most of the internal registers used in different SAM families.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2024-01-22 09:47:21 +00:00
Gerson Fernando Budke
e9b26b5eb6 soc: sam0: samd: Fix switching between clocks
The clock z_arm_platform_init hangs switching between clocks when using
MCUboot. This fixes the issue using the 8MHz internal clock as gclk_main
source when configuring PLL/DFLL.

Fixes: #67220

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2024-01-20 14:36:30 +01:00
Ryan McClelland
2ee2b6ac08 drivers: spi: dw: remove HAS_SPI_DW Kconfig
The HAS_SPI_DW Kconfig is rather unncessary. If the synopsys designware
spi is to be included. It should come from the devicetree.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2024-01-20 13:11:42 +01:00
Ben Wolsieffer
37352d3d29 soc: nrf53: fix building anomaly 168 workaround
With GCC 12.3 and binutils 2.40, the build fails with:

<...>/zephyr/arch/arm/core/cortex_m/cpu_idle.S: Assembler messages:
<...>/zephyr/arch/arm/core/cortex_m/cpu_idle.S:51: Error: junk at end of line, first unrecognized character is `n'
<...>/zephyr/arch/arm/core/cortex_m/cpu_idle.S:133:   Info: macro invoked from here

Because the SOC_ON_EXIT_CPU_IDLE macro puts all the statements on a
single line, there must be a semicolon after .rept

Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
2024-01-18 12:53:12 +01:00
Krzysztof Chruściński
a0382bd0f3 soc: arm: nordic_nrf: Disable UART runtime configuration
Since it takes 400 bytes of code and it is rarely used disable
by default this feature.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2024-01-18 11:12:55 +01:00
Mykola Kvach
72758f96d1 drivers: pinctrl: pfc_rcar: add support of voltage control to pfc driver
Add support of voltage control to Renesas PFC driver. Voltage register
mappings have been added to r8a77951 and r8a77961 SoCs.

Allow 'power-source' property for 'renesas,rcar-pfc' node. This property
will be used for configuring IO voltage on appropriate pin. For now it
is possible to have only two voltages: 1.8 and 3.3.

Note: it is possible to change voltage only for SD/MMC pins on r8a77951
      and r8a77961 SoCs.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2024-01-18 10:53:17 +01:00
Markus Swarowsky
11175c3ad3 tf-m: Change NS include path for TF-M 2.0.0
The place where TF-M places its non-secure api header files has changed
Therefore changing it for for all applications that use it.

Signed-off-by: Markus Swarowsky <markus.swarowsky@nordicsemi.no>
2024-01-17 16:52:52 +01:00
Daniel DeGrasse
6d562f1750 soc: arm: nxp_imx: rt5xx: clock DMIC0
Clock DMIC0 from the audio PLL when DMIC driver class is enabled.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
2024-01-17 14:43:52 +01:00
Erwan Gouriou
7a2e74604f soc: stm32: common: Define STM32_LPTIM_CLOCK from device tree inputs
Now that:
1 - LS Clocks sources values are identical accross series
2 - We're able to extract this value from device tree

define STM32_LPTIM_CLOCK choice symbol from device tree

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2024-01-16 10:07:02 +00:00
Manuel Argüelles
6d53c2aed2 soc: arm: nxp_s32: s32k3: select CONFIG_CACHE_MANAGEMENT
Commit 447a492 switched to `sys_cache*` to enable caches at SoC init. To
preserve the old behavior of enabling caches at init, is missing to
select `CONFIG_CACHE_MANAGEMENT`.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-01-12 09:21:58 -06:00
Derek Snell
11d52f71e5 soc: arm: nxp: increase NUM_IRQS for RT5xx series
This enables the PVT Sensor IRQ.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2024-01-12 10:00:00 +01:00
Daniel DeGrasse
55fe95a5f6 soc: arm: nxp_imx: enable CONFIG_CACHE_MANAGEMENT for RT1xxx M7 cores
Since d992683db5 (soc: arm: replace redundant config option for
caches for nxp_imx), RT1xxx series will not have cache enabled at boot
unless CONFIG_CACHE_MANAGEMENT=y. Since this will improve performance,
enable CONFIG_CACHE_MANAGEMENT by default.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-01-11 16:17:03 +00:00
Jun Lin
a897b8a09c drivers: spi: npcx: add driver for the SPI peripheral
This commit adds the driver support for the NPCX SPI peripheral.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2024-01-11 10:04:21 +01:00
Gerard Marull-Paretas
b3d8fc5e82 soc: arm: gigadevice: s/gigadevice/gd_gd32
Gigadevice was inconsistent with the convention established by other SoC
families, that is, use <vnd_prefix>_<family>. For example, ST STM32 uses
st_stm32. Note that GD32VF103, under soc/riscv, has already been
adjusted.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-10 20:59:21 -05:00
Benedikt Schmidt
10c0b86f83 soc: arm: use sys_cache* to enable caches for stm32f7 and stm32h7
Use sys_cache* functions to enable the caches for stm32f7 and
stm32h7. This ensures that CONFIG_CACHE_MANAGEMENT is
considered correctly.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2024-01-10 09:59:58 +01:00
Benedikt Schmidt
8b4516226b soc: arm: use sys_cache* for enabling the caches on same70 and samv71
Use the sys_cache* functions to enable the caches on same70 and
samv71. This will ensure that CONFIG_CACHE_MANAGEMENT is
considered correctly.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2024-01-10 09:59:58 +01:00
Benedikt Schmidt
1f1b430d88 soc: arm: remove redundant cache config options for kv5x
Remove the redundant cache config options for kv5x and use
the sys_cache* functions to enable the caches. This will automatically
consider CONFIG_CACHE_MANAGEMENT.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2024-01-10 09:59:58 +01:00
Benedikt Schmidt
d992683db5 soc: arm: replace redundant config option for caches for nxp_imx
Replace the redundant cache config options for the nxp_imx and
use sys_cache* functions to enable the caches. These will automatically
consider CONFIG_CACHE_MANAGEMENT.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2024-01-10 09:59:58 +01:00
Benedikt Schmidt
49d3244798 soc: arm: use sys_cache* for enabling the caches in nxp_s32
Use sys_cache* for enabling the caches in nxp_s32. This automatically
considers CONFIG_CACHE_MANAGEMENT and will activate the
cases only if this is active.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2024-01-10 09:59:58 +01:00
Andriy Gelman
d540407fc8 drivers: mdio: Add xmc4xxx mdio drivers
Add mdio drivers for xmc4xxx SoCs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2024-01-09 10:00:47 +01:00
Manuel Argüelles
58f5720eb4 dts: arm: nxp: add FlexCAN support for S32K1xx
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-01-08 08:30:49 -06:00
Bjarki Arge Andreasen
95c5f9b6f3 soc: arm: stm32f4 increase IDLE stack in case of PM
When Power Management is enabled (CONFIG_PM=y),
the CONFIG_IDLE_STACK_SIZE of 320 is not enough :
Increase its size to 512.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
2024-01-08 12:34:30 +01:00
Bjarki Arge Andreasen
01e94e0766 soc: arm: stm32: Fix invalid Kconfig PM entry in defconfig file
The defconfig.series file for the stm32f4 incorrectly redefines
the PM Kconfig in order to select two dependencies, COUNTER and
COUNTER_RTC_STM32_SUBSECONDS, instead of setting a default for
them if PM is included.

This commit fixes the error described above.

Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
2024-01-08 12:34:30 +01:00
Jakub Zymelka
dfbcc8911a dts: arm: add new gpiote instances definition
Added GPIOTE0, GPIOTE1 instances for legacy devices,
GPIOTE20, GPIOTE30 for Moonlight and GPIOTE130,
GPIOTE131 instances for Haltium.

Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
2024-01-08 11:19:37 +01:00
Jamie McCrae
6f226eb153 various: Remove BOOTLOADER_SRAM_SIZE overrides
Removes settings this Kconfig to 0, because the default already
is 0

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-01-08 10:06:24 +01:00
Manuel Argüelles
aeebe484f2 soc: arm: nxp_s32: s32k1: add FlexTimer support
Add support for FlexTimer (FTM) module on S32K1xx devices.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-01-05 09:03:00 +01:00
Derek Snell
44885cbca5 boards: mimxrt595: add CONFIG_MIPI_DPHY_CLK_SRC
Give option in soc.c to initialize the MIPI DPHY clock from the default
AUX1_PLL, or from the FRO using CONFIG_MIPI_DPHY_CLK_SRC_FRO.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2024-01-05 09:02:25 +01:00
Derek Snell
3f2ded3455 soc: arm: nxp_imx: r5xx: add Kconfig to clock FC0 from FRO
Flexcomm0 has option to clock from FRO.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2024-01-05 09:02:25 +01:00
Aaron Ye
c3e8b731ef soc: arm: ambiq: Remove the redundant configurations.
These non-cached SRAM size and base address configurations
are not needed now.

Signed-off-by: Aaron Ye <aye@ambiq.com>
2024-01-04 11:06:37 +00:00
Jaro Van Landschoot
be6cf5c268 soc: arm: atmel_sam: Sys_arch_reboot using RSTC
The previous implementation of the sys_arch_reboot function
for the Atmel SAM series was using NVIC_SystemReset.
This caused a reboot time of around 20 seconds on a SAM4SA16CA,
which is now reduced by directly writing to the
reset controller control register (RSTC_CR).

Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-12-28 12:05:53 +00:00
Daniel DeGrasse
beb43bdf20 soc: arm: nxp: add MK22F12 definition
Add SOC definition for MK22F12 series, larger LQFP-144 K22 series
parts that feature additional peripheral instances.

Additionally, these parts differ from the standard MK22 in the following
ways:
- SYSMPU peripheral is present, so an MPU definition is required
- No external oscillator divider is present

This commit also updates the NXP HAL to include pin control files for
these SOCs.

Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
2023-12-23 10:00:36 +00:00
Erwan Gouriou
79599a15d4 soc: stm32: stmw32wba: Get stop mode compatible with BLE
Supporting Stop1 mode while BLE RF is enabled requires some specific
adaptation and usage of STM32WBA Cube BLE controller scm API.

scm (Secure clock manager) is in charge of switching clock depending
on RF status and should be informed of PM stop modes scheduling.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-12-22 09:53:33 +01:00
Erwan Gouriou
2908458554 soc: stm32wba: hci_if: Implement HW_RNG_EnableClock API
STM32WBA controller uses a PKA driver to perform cyphering operations
on keys. Since PKA hardware block requires RNG clock to be enabled, a
synchronization with zephyr RNG driver is needed.

Use RNG enable status to check if RNG could be switched off or needs to
be switched on.
Similarly in entropy driver, don't cut RNG clock if PKA is enabled.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-12-21 09:18:53 +01:00
Andrei-Edward Popa
ea1cafbee7 drivers: clock_control: Added clock driver for Raspberry Pi Pico
Added clock driver for Raspberry Pi Pico platform

Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2023-12-20 11:14:24 +01:00
Johan Hedberg
95b1d586b9 soc: arm: Use HEAP_MEM_POOL_ADD_SIZE KConfig options
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2023-12-20 11:01:42 +01:00
Andrej Butok
abcfd0cbd8 soc: lpc55xxx: Fix TFM
TFM is using flash, so sys. clock must be decreased.
Fixes #65957

Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
2023-12-19 08:51:45 +01:00
Erwan Gouriou
6f6410061d soc: stm32wba: Implement BLE controller lib APIs over Zephyr
In order to enable BLE support on STM32WBA, following APIs are implemented:
- HostStack_: BLE Controller scheduling
- ll_sys_: Link layer API required for scheduling
- UTIL_TIMER_: BLE Controller timer utility
- LINKLAYER_PLAT_: BLE controller utilities

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-12-18 17:31:08 +00:00
Tom Chang
4dc7c89f40 drivers: espi: npcx: introduce espi taf driver
This CL implements espi taf read/write/erase function for NPCX.

Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
2023-12-18 09:30:01 +01:00
Zoltan Havas
e7039bc37f zephyr: Kconfig: SOC_GECKO_CUSTOM_RADIO_PHY option for RAIL for proprietary
Currently on zephyr, RAIL library is used only by Bluetooth applications,
with this update, it will be able to be used for sample applications
for custom radio phys.
All files were copied from Silicon Labs GSDK v4.2.4.

Signed-off-by: Zoltan Havas <zoltan.havas@silabs.com>
2023-12-14 14:21:21 +01:00
Marc Desvaux
4dc0bd1800 drivers: ethernet: remove sections.ld for SOC_SERIES_STM32H5X
remove section(".eth_stm32_desc") and
section(".eth_stm32_desc") for SOC_SERIES_STM32H5X


Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
2023-12-14 09:32:35 +01:00
Evan Perry Grove
a54a52b085 dts: arm: Add support for STM32F722 SoC
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.

Signed-off-by: Evan Perry Grove <evan@4grove.com>
2023-12-13 13:57:55 +01:00
Sebastian Schlupp
0462cc060d soc: same51 and same54: added DFLL48 frequency information
Specified the value 48000000 for the DFLL48 clock source

Signed-off-by: Sebastian Schlupp <sebastian.schlupp@gmail.com>
2023-12-12 16:25:46 +01:00
Flavio Ceolin
ebf50eee42 soc: stm32f4: Fix PM dependency
COUNTER_RTC_STM32_SUBSECONDS depends on DT_HAS_ST_STM32_RTC_ENABLED.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-12-12 10:57:34 +01:00
Andreas Sandberg
5767c8d78c dts: stm32g4: Add ITM support
The STM32 G4 series has a built-in Arm Instrumentation Trace
Macrocell. Set CONFIG_HAS_SWO to enable this.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2023-12-12 10:56:44 +01:00
Francois Ramu
5bacc2eaac soc: arm: stm32 SYS_CLOCK_TICKS_PER_SEC config with STM32_LPTIM_TIMER
Configure the SYS_CLOCK_TICKS_PER_SEC directly from the
DTS st-prescaler property of the lptim node
aka stm32_lp_tick_source

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-12-12 09:52:30 +00:00
Luca Burelli
11d4f8e5e5 soc: stm32: unify cache conditionals for F7 and H7 targets
The instruction cache in the STM32F7 and H7 was enabled regardless
of the value assigned via Kconfig to the CONFIG_ICACHE parameter.
This commit adds the missing conditional checks; note that this does
not affect the compiled behavior unless CONFIG_ICACHE is explicitly
disabled by the user.

Remove a redundant low-level check on DCache being already enabled,
since it is also performed inside the SCB_EnableDCache function.

Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
2023-12-12 09:51:11 +00:00
Anas Nashif
699880a430 arch: arm: cortex_m: rename expection header
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-11 18:22:40 -05:00