soc: arm: atmel_sam: sam4s: Rework clock_init
Update clock_init for the Atmel SAM4S SoC using the new PMC API. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
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1 changed files with 60 additions and 146 deletions
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@ -3,6 +3,7 @@
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* Copyright (c) 2016 Intel Corporation.
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* Copyright (c) 2017 Justin Watson
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* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
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* Copyright (c) 2023 Basalte bv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -15,9 +16,9 @@
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* for the Atmel SAM4S series processor.
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <soc_pmc.h>
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#include <soc_supc.h>
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/**
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* @brief Setup various clock on SoC at boot time.
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@ -29,158 +30,36 @@
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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uint32_t reg_val;
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/* Switch the main clock to the internal OSC with 12MHz */
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soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
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#ifdef CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK
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/* Switch slow clock to the external 32 KHz crystal oscillator. */
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SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL;
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/* Switch MCK (Master Clock) to the main clock */
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soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
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/* Wait for oscillator to be stabilized. */
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while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) {
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;
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}
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#endif /* CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK */
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#ifdef CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK
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/*
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* Setup main external crystal oscillator.
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*/
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/* Start the external crystal oscillator. */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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/* Fast RC oscillator frequency is at 4 MHz. */
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| CKGR_MOR_MOSCRCF_4_MHz
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/*
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* We select maximum setup time. While start up time
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* could be shortened this optimization is not deemed
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* critical right now.
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*/
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| CKGR_MOR_MOSCXTST(0xFFu)
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/* RC oscillator must stay on. */
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| CKGR_MOR_MOSCRCEN
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| CKGR_MOR_MOSCXTEN;
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/* Wait for oscillator to be stabilized. */
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
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;
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}
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/* Select the external crystal oscillator as the main clock source. */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCRCF_4_MHz
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| CKGR_MOR_MOSCRCEN
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| CKGR_MOR_MOSCXTEN
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| CKGR_MOR_MOSCXTST(0xFFu)
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| CKGR_MOR_MOSCSEL;
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/* Wait for external oscillator to be selected. */
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while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
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;
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}
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/* Turn off RC oscillator, not used any longer, to save power */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCSEL
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| CKGR_MOR_MOSCXTST(0xFFu)
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| CKGR_MOR_MOSCXTEN;
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/* Wait for the RC oscillator to be turned off. */
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while (PMC->PMC_SR & PMC_SR_MOSCRCS) {
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;
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}
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#ifdef CONFIG_SOC_ATMEL_SAM4S_WAIT_MODE
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/*
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* Instruct CPU to enter Wait mode instead of Sleep mode to
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* keep Processor Clock (HCLK) and thus be able to debug
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* CPU using JTAG.
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*/
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PMC->PMC_FSMR |= PMC_FSMR_LPM;
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EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
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#if defined(ID_EFC1)
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EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
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#endif
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#else
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/* Setup main fast RC oscillator. */
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/*
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* NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR
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* register, should normally be the case.
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*/
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
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;
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soc_pmc_enable_clock_failure_detector();
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK)) {
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soc_supc_slow_clock_select_crystal_osc();
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}
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/* Set main fast RC oscillator to 12 MHz. */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCRCF_12_MHz
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| CKGR_MOR_MOSCRCEN;
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) {
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/*
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* Setup main external crystal oscillator.
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*/
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/* Wait for RC oscillator to stabilize. */
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
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;
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}
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#endif /* CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK */
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/*
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* Setup PLLA
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*/
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/* Switch MCK (Master Clock) to the main clock first. */
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reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
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PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK;
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/* Wait for clock selection to complete. */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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;
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/* We select maximum setup time.
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* While start up time could be shortened
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* this optimization is not deemed
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* critical now.
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*/
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soc_pmc_switch_mainck_to_xtal(false, 0xff);
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}
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/* Setup PLLA. */
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
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| CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA)
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| CKGR_PLLAR_PLLACOUNT(0x3Fu)
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| CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA);
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/*
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* NOTE: Both MULA and DIVA must be set to a value greater than 0 or
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* otherwise PLL will be disabled. In this case we would get stuck in
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* the following loop.
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*/
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/* Wait for PLL lock. */
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while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
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;
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}
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/*
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* Final setup of the Master Clock
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*/
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/*
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* NOTE: PMC_MCKR must not be programmed in a single write operation.
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* If CSS or PRES are modified we must wait for MCKRDY bit to be
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* set again.
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*/
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/* Setup prescaler - PLLA Clock / Processor Clock (HCLK). */
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reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk;
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PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1;
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/* Wait for Master Clock setup to complete */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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;
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}
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/* Finally select PLL as Master Clock source. */
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reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
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PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK;
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/* Wait for Master Clock setup to complete. */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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;
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}
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}
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void z_arm_platform_init(void)
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{
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/*
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* Set FWS (Flash Wait State) value before increasing Master Clock
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* (MCK) frequency. Look at table 44.73 in the SAM4S datasheet.
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@ -188,9 +67,44 @@ void z_arm_platform_init(void)
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* hurt lower clock frequencies. However, a high frequency with too
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* few read cycles could cause flash read problems. FWS 5 (6 cycles)
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* is the safe setting for all of this SoCs usable frequencies.
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* TODO: Add code to handle SAM4SD devices that have 2 EFCs.
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*/
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EFC0->EEFC_FMR = EEFC_FMR_FWS(5);
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#if defined(ID_EFC1)
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EFC1->EEFC_FMR = EEFC_FMR_FWS(5);
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#endif
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/*
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* Setup PLLA
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*/
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soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA, 0x3Fu,
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CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA);
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/*
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* Final setup of the Master Clock
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*/
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/* prescaler has to be set before PLL lock */
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soc_pmc_mck_set_prescaler(1);
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/* Select PLL as Master Clock source. */
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soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
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/* Disable internal fast RC if we have an external crystal oscillator */
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) {
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soc_pmc_osc_disable_fastrc();
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}
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}
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void z_arm_platform_init(void)
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{
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_WAIT_MODE)) {
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/*
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* Instruct CPU to enter Wait mode instead of Sleep mode to
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* keep Processor Clock (HCLK) and thus be able to debug
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* CPU using JTAG.
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*/
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soc_pmc_enable_waitmode();
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}
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/* Setup system clocks. */
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clock_init();
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