Add support for mipi_dsi_detach API to dsi_mcux_2l driver, and
update RT5xx SOC interface to enable halting clocks for the MIPI DPHY.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Enable NXP FlexRAM in DTS and SOC code.
Do not configure flexram at runtime if the code is in the RAM.
Fix RT1060 DT to be more accurate.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Other drivers like the pinctrl_ti_k3 rely on a fully initialized system.
Move the am62x_init to an earlier stage than PRE_KERNEL_1 to keep both
PRE_KERNEL_{1,2} free for drivers.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
- Make caparray delta a Kconfig variable
- Set caparray delta for beagle_bcf at beagleconnect_freedom_defconfig
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we
introduce a new chip series. Most of them are relevant to register
layouts in different npcx soc series. It moves soc-specific register
definitions from `reg_def.h` to its own soc.h file.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Fix cmake depreciation warning on pre-defined linker.id
(soc/arm/renesas_ra/ra4m1/linker.ld) used for arduino_uno_r4_minima.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Allow user to disable CONFIG_ADJUST_DCDC for their board, rather than
selecting it at the SOC level. The symbol still defaults to enabled,
preserving existing behavior unless a user explicitly chooses to disable
it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.
Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit introduce 'USE_SWITCH' feature into cortex-A/R(aarch32)
architecture
For introducing USE_SWITCH, the exception entry and exit are unified via
`z_arm_cortex_ar_enter_exc` and `z_arm_cortex_ar_exit_exc`. All
exceptions including ISR are using this way to enter and exit exception
handler.
Differentiate exception depth and interrupt depth. Allow doing
context switch when exception depth greater than 1 but not allow doing
this when interrupt depth greater than 1.
Currently, USE_SWITCH doesn't support FPU_SHARING and USERSPACE.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Commit c6e3bac4f changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
For this SoC, an additional section is conditionally included on top of
the default linker script for Cortex-M. Set `SOC_LINKER_SCRIPT` to the
local `linker.ld`.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Remove CONFIG_IPM_IMX_REV2, as this Kconfig is no longer needed. The
driver can now be enabled with CONFIG_IPM_IMX.
Update NXP HAL to remove this Kconfig as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit updates all arm SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Locate common mpu code together with other arm / nxp mpu code in the
arch folder where it logically belongs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
PM should not be enabled by default at the soc level. This is an
application decision and not a platform decision whether to enable or
disable PM features.
Enabling PM by default will result in descripencies and test scope and
failures in tests that do not account for PM being enabled.
Fixes#60359
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Force STM32_ENABLE_DEBUG_SLEEP_STOP option when running tests.
This option enables Debug in Sleep/stop states and disables it when
disabled (default state).
When disabled, it may be impossible to flash the device with runner
such as openocd. It's generally working using cubeprogrammer, but it might
fail as well with fault configuration.
Instead of fixing each test or breaking CI each time a new test is created
with CONFIG_PM=y, force this option to be enabled when ZTEST=y (as it was
already the case when DEBUG=y).
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM
code for Armv-8 Aarch32 is written for Arm mode only. This Soc
has a general purpose register that can set the core TEINIT signal
to change the mode exceptions are taken before booting up the core.
The debugger startup scripts or firmware booting up the core may
configure this bit to Thumb mode, as is the case of the NXP S32 debug
probe startup scripts for S32ZE.
Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value
is ignored and exceptions are always taken into Arm mode, compatible
with current Zephyr ASM code. At least until taking execeptions in Thumb
mode is supported in Zephyr.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit adds an implementation of poweroff, which first
uses SUPC to enable all defined wakeup sources (except for
sam4l), followed by entering backup mode.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Now the API to manage GPREGRET register is unified for all devices
having one or more GPREGRET entries.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add generic SoC support for the supported nordic SoCs:
- nrf5340
- nrf9160
- nrf9120
Add generic SoC support by taking board specific configurations from
zephyr devicetree and kconfig.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Let's make the sync_rtc kconfig depend on the SOC_COMPATIBLE
options which are set both by the real and simulated targets,
so this code works in the same way for both.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The Kconfig option HAS_PM, which must be needed for SoCs providing PM
hooks, is missing in npcx4.
This commit adds it to soc/arm/nuvoton_npcx/npcx4/Kconfig.series.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
- if we have input enable use CY_GPIO_DM_xxxx else
CY_GPIO_DM_xxx_IN_OFF;
- added bias_high_impedance option
- Updated HIGHZ drive mode, now it sets if:
--- we have bias_high_impedance
--- or if input_enable and no addition bias mode
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
