Commit graph

2589 commits

Author SHA1 Message Date
Charles Dias
63ceeb3bba soc: arm: st_stm32: add support for stm32h7b0xx and stm32h7b0xxQ
Add Kconfig SoC configurations.

Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
2023-11-15 10:02:06 +01:00
Daniel DeGrasse
5854821b65 drivers: mipi_dsi: add support for mipi_dsi_detach to dsi_mcux_2l
Add support for mipi_dsi_detach API to dsi_mcux_2l driver, and
update RT5xx SOC interface to enable halting clocks for the MIPI DPHY.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-14 09:22:59 +01:00
Manuel Argüelles
434a40470c drivers: mbox: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-13 12:18:34 -05:00
Manuel Argüelles
b3f950c648 drivers: mdio: nxp_s32_netc: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-13 09:49:26 +01:00
Declan Snyder
2d1fdb5586 soc: nxp: rt1xxx: Enable NXP FlexRAM
Enable NXP FlexRAM in DTS and SOC code.

Do not configure flexram at runtime if the code is in the RAM.

Fix RT1060 DT to be more accurate.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-13 09:42:28 +01:00
Daniel Schultz
a2f971795f soc: arm: ti_k3: am62x_m4: Lower Initialization level for init
Other drivers like the pinctrl_ti_k3 rely on a fully initialized system.
Move the am62x_init to an earlier stage than PRE_KERNEL_1 to keep both
PRE_KERNEL_{1,2} free for drivers.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2023-11-13 09:42:11 +01:00
Jason Kridner
26f30db8ad soc: arm: ti_simplelink: cc13x2x7_cc26x2x7: add caparray delta config
- Make caparray delta a Kconfig variable
- Set caparray delta for beagle_bcf at beagleconnect_freedom_defconfig

Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
2023-11-11 18:49:25 -05:00
Declan Snyder
fef0018cca soc: lpc55xxx: Support, enable, test NXP MRT
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-10 10:40:54 +01:00
Declan Snyder
93c59793c2 soc: rt6xx: Add NXP MRT
Add NXP MRT to RT6xx DT definition and add peripheral reset to soc.c

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-10 10:40:54 +01:00
Declan Snyder
ff83745c9a soc: rt5xx: Enable NXP MRT
Enable NXP MRT on RT5xx soc and MIMXRT595_EVK board

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-10 10:40:54 +01:00
Manuel Argüelles
595a9c11c8 counter: nxp_s32_sys_timer: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-09 18:21:19 +01:00
Declan Snyder
345f079e49 dts: bindings: Fix NXP USB bindings
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-09 15:34:39 +01:00
Mulin Chao
f9a4a3597b soc: arm: npcx: move soc-specific register definitions to soc.h
This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we
introduce a new chip series. Most of them are relevant to register
layouts in different npcx soc series. It moves soc-specific register
definitions from `reg_def.h` to its own soc.h file.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-11-09 10:20:39 +00:00
Manuel Argüelles
6744d6084d watchdog: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-09 10:20:27 +00:00
Manuel Argüelles
bda3b101d3 serial: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-08 10:06:46 +01:00
Dmitrii Golovanov
82ec6394a1 soc: arm: Fix cmake linker.ld warning for arduino_uno_r4_minima
Fix cmake depreciation warning on pre-defined linker.id
(soc/arm/renesas_ra/ra4m1/linker.ld) used for arduino_uno_r4_minima.

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
2023-11-07 09:53:57 +01:00
Daniel DeGrasse
883f604f12 soc: arm: nxp_imx: rt11xx: allow user to disable CONFIG_ADJUST_DCDC
Allow user to disable CONFIG_ADJUST_DCDC for their board, rather than
selecting it at the SOC level. The symbol still defaults to enabled,
preserving existing behavior unless a user explicitly chooses to disable
it.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-07 09:48:35 +01:00
Manuel Argüelles
237ec65ad3 intc: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.

Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-06 19:02:56 -05:00
Huifeng Zhang
abde709b5e arch: arm: cortex_a_r: introduce USE_SWITCH
This commit introduce 'USE_SWITCH' feature into cortex-A/R(aarch32)
architecture

For introducing USE_SWITCH, the exception entry and exit are unified via
`z_arm_cortex_ar_enter_exc` and `z_arm_cortex_ar_exit_exc`. All
exceptions including ISR are using this way to enter and exit exception
handler.

Differentiate exception depth and interrupt depth. Allow doing
context switch when exception depth greater than 1 but not allow doing
this when interrupt depth greater than 1.

Currently, USE_SWITCH doesn't support FPU_SHARING and USERSPACE.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-11-06 15:32:01 -06:00
Gerson Fernando Budke
3ed1c990dc soc: st: l010xb: Fix the number of IRQs
Change the NUM_IRQS value from 32 to 30 following the rm0451.

Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2023-11-06 10:14:10 +01:00
Gerson Fernando Budke
6e3bae727b soc: st: Add all missing stm32l010 SoCs
Add minimal SoC entries to enable the whole stm32l010 family.

Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2023-11-06 10:14:10 +01:00
Caspar Friedrich
8242ef0a37 soc: arm: st_stm32: stm32l0: Add support for STM32L081
Add support for the STM32L081xx soc series.

Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
2023-11-06 10:11:40 +01:00
Declan Snyder
4d654250a5 soc: lpc55xxx: Fix system hw clock cycle rate
Commit c6e3bac4f changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-06 10:11:25 +01:00
Grzegorz Swiderski
e4448ed498 soc: mimx8mm6_m4: Restore linker script
For this SoC, an additional section is conditionally included on top of
the default linker script for Cortex-M. Set `SOC_LINKER_SCRIPT` to the
local `linker.ld`.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2023-11-06 10:10:55 +01:00
Daniel DeGrasse
29ab2b13f6 drivers: ipm: Remove CONFIG_IPM_IMX_REV2
Remove CONFIG_IPM_IMX_REV2, as this Kconfig is no longer needed. The
driver can now be enabled with CONFIG_IPM_IMX.

Update NXP HAL to remove this Kconfig as well.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-06 10:09:59 +01:00
Daniel DeGrasse
8d5322b8ff drivers: ipm: remove nxp,imx-mu-rev2 compatible
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible

Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-06 10:09:59 +01:00
Torsten Rasmussen
4812884f84 cmake: arm: update arm SoC to use SOC_LINKER_SCRIPT variable
This commit updates all arm SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-03 11:01:23 +01:00
Torsten Rasmussen
3e82eb976e soc: move arm cortex_m common mpu code to arch/arm/core/mpu
Locate common mpu code together with other arm / nxp mpu code in the
arch folder where it logically belongs.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-02 09:45:18 +01:00
TOKITA Hiroshi
a9e49918cf drivers: interrupt_controller: Add icu driver for Renesas RA series
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
04b723e900 drivers: pinctrl: Add pinctrl driver for Renesas RA series
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
1741b3a356 drivers: clock_control: Add clock driver for Renesas RA series
Add initial support for Renesas RA clock generation circuit.

It returns a fixed value to simplify the first commit to get the UART
working now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
5ccc0eb319 soc: arm: add support for Renesas RA4M1 series SoC
Add essential support for RA4M1 Series.
It only defines `r7fa4m1ab3cfm` currently.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
Andriy Gelman
d0961756a6 drivers: watchdog: Add xmc4xxx support
Adds watchdog support for Infineon xmc4xxx MCUs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-10-27 12:58:07 -05:00
Mike J. Chen
ca19b40733 soc: arm: nxp_imx: rt5xx: make some clock init functions weak
Allows a board to provide their own functions if
they wish to init clocks differently.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2023-10-27 10:51:28 +02:00
Anas Nashif
51f6c4269b soc: microchip_mec: do not enable PM in soc
PM should not be enabled by default at the soc level. This is an
application decision and not a platform decision whether to enable or
disable PM features.

Enabling PM by default will result in descripencies and test scope and
failures in tests that do not account for PM being enabled.

Fixes #60359

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-10-26 12:28:18 -05:00
Erwan Gouriou
54fa6f30b8 soc: stm32: Enable Debug in stop mode when ZTEST is used
Force STM32_ENABLE_DEBUG_SLEEP_STOP option when running tests.
This option enables Debug in Sleep/stop states and disables it when
disabled (default state).

When disabled, it may be impossible to flash the device with runner
such as openocd. It's generally working using cubeprogrammer, but it might
fail as well with fault configuration.

Instead of fixing each test or breaking CI each time a new test is created
with CONFIG_PM=y, force this option to be enabled when ZTEST=y (as it was
already the case when DEBUG=y).

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-10-26 09:49:42 +02:00
Manuel Argüelles
a7bda08960 nxp: s32ze: take exceptions in Arm mode
Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM
code for Armv-8 Aarch32 is written for Arm mode only. This Soc
has a general purpose register that can set the core TEINIT signal
to change the mode exceptions are taken before booting up the core.
The debugger startup scripts or firmware booting up the core may
configure this bit to Thumb mode, as is the case of the NXP S32 debug
probe startup scripts for S32ZE.

Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value
is ignored and exceptions are always taken into Arm mode, compatible
with current Zephyr ASM code. At least until taking execeptions in Thumb
mode is supported in Zephyr.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-10-25 18:14:51 -07:00
Bjarki Arge Andreasen
9b21d4d366 soc: sam: Add poweroff implementation
This commit adds an implementation of poweroff, which first
uses SUPC to enable all defined wakeup sources (except for
sam4l), followed by entering backup mode.

Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
2023-10-24 11:35:43 +02:00
Bjarki Arge Andreasen
312c8b1930 soc: sam: Add SUPC driver and dts model
This commit adds a driver and dts model for the ATMEL SAM
SUPC component.

Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
2023-10-24 11:35:43 +02:00
Nikodem Kastelik
a4cbe9e9c6 soc: arm: nordic_nrf: align nrf_power calls to new scheme
Now the API to manage GPREGRET register is unified for all devices
having one or more GPREGRET entries.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2023-10-24 11:13:53 +02:00
Nikodem Kastelik
f3f2c113d1 soc: arm: nordic_nrf: nrf53: align nrf_regulators calls to new scheme
Now more generic regulators API is available.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2023-10-24 11:13:53 +02:00
Joakim Andersson
17fd1f8fba boards: Enable TF-M by default for nordic SoC NS boards
Enable TF-M by default for nordic nRF5340 and nrf9160 SoC boards.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2023-10-24 09:40:16 +02:00
Joakim Andersson
33a44d0ed8 tfm: nordic_nrf: Add generic SoC support for nordic SoCs
Add generic SoC support for the supported nordic SoCs:
- nrf5340
- nrf9160
- nrf9120

Add generic SoC support by taking board specific configurations from
zephyr devicetree and kconfig.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2023-10-24 09:40:16 +02:00
Alberto Escolar Piedras
9834fabe2d nrf53: Correct sync_rtc kconfig dependencies for simulation
Let's make the sync_rtc kconfig depend on the SOC_COMPATIBLE
options which are set both by the real and simulated targets,
so this code works in the same way for both.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-10-20 15:20:09 +02:00
Alberto Escolar Piedras
32d0c8d8e5 nrf53: Refactor sync RTC options to their own file
So they can be reused by the simulated board

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-10-20 15:20:09 +02:00
Jun Lin
e5e599c100 soc: npcx: add HAS_PM to npcx4
The Kconfig option HAS_PM, which must be needed for SoCs providing PM
hooks, is missing in npcx4.
This commit adds it to soc/arm/nuvoton_npcx/npcx4/Kconfig.series.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-10-20 15:11:14 +02:00
Adam Wojasinski
5685af0923 modules: hal_nordic: Add support for new TWIM instances
Add Kconfig and symbols for twim: 20-22, 30, 121, 130-137 instances

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-10-20 15:04:10 +02:00
Adam Wojasinski
5c1daef5ab drivers: spi: nrfx: Add SPIM Kconfig symbols for new instances
Add support for upcomming SPIM instances.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-10-20 15:03:17 +02:00
Niek Ilmer
9e6b1d5ba6 SOC: Smartbond: Add DA14695
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.

Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
2023-10-20 14:51:49 +02:00
Nazar Palamar
4d76e26f17 drivers: pinctrl: Update Infineon CAT1 pinctrl driver
- if we have input enable use CY_GPIO_DM_xxxx else
CY_GPIO_DM_xxx_IN_OFF;

- added bias_high_impedance option

- Updated HIGHZ drive mode, now it sets if:
--- we have bias_high_impedance
--- or if input_enable and no addition bias mode

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2023-10-12 15:17:35 +03:00