Commit graph

2576 commits

Author SHA1 Message Date
Manuel Argüelles
6744d6084d watchdog: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-09 10:20:27 +00:00
Manuel Argüelles
bda3b101d3 serial: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-08 10:06:46 +01:00
Dmitrii Golovanov
82ec6394a1 soc: arm: Fix cmake linker.ld warning for arduino_uno_r4_minima
Fix cmake depreciation warning on pre-defined linker.id
(soc/arm/renesas_ra/ra4m1/linker.ld) used for arduino_uno_r4_minima.

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
2023-11-07 09:53:57 +01:00
Daniel DeGrasse
883f604f12 soc: arm: nxp_imx: rt11xx: allow user to disable CONFIG_ADJUST_DCDC
Allow user to disable CONFIG_ADJUST_DCDC for their board, rather than
selecting it at the SOC level. The symbol still defaults to enabled,
preserving existing behavior unless a user explicitly chooses to disable
it.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-07 09:48:35 +01:00
Manuel Argüelles
237ec65ad3 intc: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.

Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-06 19:02:56 -05:00
Huifeng Zhang
abde709b5e arch: arm: cortex_a_r: introduce USE_SWITCH
This commit introduce 'USE_SWITCH' feature into cortex-A/R(aarch32)
architecture

For introducing USE_SWITCH, the exception entry and exit are unified via
`z_arm_cortex_ar_enter_exc` and `z_arm_cortex_ar_exit_exc`. All
exceptions including ISR are using this way to enter and exit exception
handler.

Differentiate exception depth and interrupt depth. Allow doing
context switch when exception depth greater than 1 but not allow doing
this when interrupt depth greater than 1.

Currently, USE_SWITCH doesn't support FPU_SHARING and USERSPACE.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-11-06 15:32:01 -06:00
Gerson Fernando Budke
3ed1c990dc soc: st: l010xb: Fix the number of IRQs
Change the NUM_IRQS value from 32 to 30 following the rm0451.

Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2023-11-06 10:14:10 +01:00
Gerson Fernando Budke
6e3bae727b soc: st: Add all missing stm32l010 SoCs
Add minimal SoC entries to enable the whole stm32l010 family.

Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2023-11-06 10:14:10 +01:00
Caspar Friedrich
8242ef0a37 soc: arm: st_stm32: stm32l0: Add support for STM32L081
Add support for the STM32L081xx soc series.

Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
2023-11-06 10:11:40 +01:00
Declan Snyder
4d654250a5 soc: lpc55xxx: Fix system hw clock cycle rate
Commit c6e3bac4f changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-06 10:11:25 +01:00
Grzegorz Swiderski
e4448ed498 soc: mimx8mm6_m4: Restore linker script
For this SoC, an additional section is conditionally included on top of
the default linker script for Cortex-M. Set `SOC_LINKER_SCRIPT` to the
local `linker.ld`.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2023-11-06 10:10:55 +01:00
Daniel DeGrasse
29ab2b13f6 drivers: ipm: Remove CONFIG_IPM_IMX_REV2
Remove CONFIG_IPM_IMX_REV2, as this Kconfig is no longer needed. The
driver can now be enabled with CONFIG_IPM_IMX.

Update NXP HAL to remove this Kconfig as well.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-06 10:09:59 +01:00
Daniel DeGrasse
8d5322b8ff drivers: ipm: remove nxp,imx-mu-rev2 compatible
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible

Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-06 10:09:59 +01:00
Torsten Rasmussen
4812884f84 cmake: arm: update arm SoC to use SOC_LINKER_SCRIPT variable
This commit updates all arm SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-03 11:01:23 +01:00
Torsten Rasmussen
3e82eb976e soc: move arm cortex_m common mpu code to arch/arm/core/mpu
Locate common mpu code together with other arm / nxp mpu code in the
arch folder where it logically belongs.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-02 09:45:18 +01:00
TOKITA Hiroshi
a9e49918cf drivers: interrupt_controller: Add icu driver for Renesas RA series
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
04b723e900 drivers: pinctrl: Add pinctrl driver for Renesas RA series
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
1741b3a356 drivers: clock_control: Add clock driver for Renesas RA series
Add initial support for Renesas RA clock generation circuit.

It returns a fixed value to simplify the first commit to get the UART
working now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
5ccc0eb319 soc: arm: add support for Renesas RA4M1 series SoC
Add essential support for RA4M1 Series.
It only defines `r7fa4m1ab3cfm` currently.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
Andriy Gelman
d0961756a6 drivers: watchdog: Add xmc4xxx support
Adds watchdog support for Infineon xmc4xxx MCUs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-10-27 12:58:07 -05:00
Mike J. Chen
ca19b40733 soc: arm: nxp_imx: rt5xx: make some clock init functions weak
Allows a board to provide their own functions if
they wish to init clocks differently.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2023-10-27 10:51:28 +02:00
Anas Nashif
51f6c4269b soc: microchip_mec: do not enable PM in soc
PM should not be enabled by default at the soc level. This is an
application decision and not a platform decision whether to enable or
disable PM features.

Enabling PM by default will result in descripencies and test scope and
failures in tests that do not account for PM being enabled.

Fixes #60359

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-10-26 12:28:18 -05:00
Erwan Gouriou
54fa6f30b8 soc: stm32: Enable Debug in stop mode when ZTEST is used
Force STM32_ENABLE_DEBUG_SLEEP_STOP option when running tests.
This option enables Debug in Sleep/stop states and disables it when
disabled (default state).

When disabled, it may be impossible to flash the device with runner
such as openocd. It's generally working using cubeprogrammer, but it might
fail as well with fault configuration.

Instead of fixing each test or breaking CI each time a new test is created
with CONFIG_PM=y, force this option to be enabled when ZTEST=y (as it was
already the case when DEBUG=y).

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-10-26 09:49:42 +02:00
Manuel Argüelles
a7bda08960 nxp: s32ze: take exceptions in Arm mode
Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM
code for Armv-8 Aarch32 is written for Arm mode only. This Soc
has a general purpose register that can set the core TEINIT signal
to change the mode exceptions are taken before booting up the core.
The debugger startup scripts or firmware booting up the core may
configure this bit to Thumb mode, as is the case of the NXP S32 debug
probe startup scripts for S32ZE.

Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value
is ignored and exceptions are always taken into Arm mode, compatible
with current Zephyr ASM code. At least until taking execeptions in Thumb
mode is supported in Zephyr.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-10-25 18:14:51 -07:00
Bjarki Arge Andreasen
9b21d4d366 soc: sam: Add poweroff implementation
This commit adds an implementation of poweroff, which first
uses SUPC to enable all defined wakeup sources (except for
sam4l), followed by entering backup mode.

Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
2023-10-24 11:35:43 +02:00
Bjarki Arge Andreasen
312c8b1930 soc: sam: Add SUPC driver and dts model
This commit adds a driver and dts model for the ATMEL SAM
SUPC component.

Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
2023-10-24 11:35:43 +02:00
Nikodem Kastelik
a4cbe9e9c6 soc: arm: nordic_nrf: align nrf_power calls to new scheme
Now the API to manage GPREGRET register is unified for all devices
having one or more GPREGRET entries.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2023-10-24 11:13:53 +02:00
Nikodem Kastelik
f3f2c113d1 soc: arm: nordic_nrf: nrf53: align nrf_regulators calls to new scheme
Now more generic regulators API is available.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2023-10-24 11:13:53 +02:00
Joakim Andersson
17fd1f8fba boards: Enable TF-M by default for nordic SoC NS boards
Enable TF-M by default for nordic nRF5340 and nrf9160 SoC boards.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2023-10-24 09:40:16 +02:00
Joakim Andersson
33a44d0ed8 tfm: nordic_nrf: Add generic SoC support for nordic SoCs
Add generic SoC support for the supported nordic SoCs:
- nrf5340
- nrf9160
- nrf9120

Add generic SoC support by taking board specific configurations from
zephyr devicetree and kconfig.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2023-10-24 09:40:16 +02:00
Alberto Escolar Piedras
9834fabe2d nrf53: Correct sync_rtc kconfig dependencies for simulation
Let's make the sync_rtc kconfig depend on the SOC_COMPATIBLE
options which are set both by the real and simulated targets,
so this code works in the same way for both.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-10-20 15:20:09 +02:00
Alberto Escolar Piedras
32d0c8d8e5 nrf53: Refactor sync RTC options to their own file
So they can be reused by the simulated board

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-10-20 15:20:09 +02:00
Jun Lin
e5e599c100 soc: npcx: add HAS_PM to npcx4
The Kconfig option HAS_PM, which must be needed for SoCs providing PM
hooks, is missing in npcx4.
This commit adds it to soc/arm/nuvoton_npcx/npcx4/Kconfig.series.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-10-20 15:11:14 +02:00
Adam Wojasinski
5685af0923 modules: hal_nordic: Add support for new TWIM instances
Add Kconfig and symbols for twim: 20-22, 30, 121, 130-137 instances

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-10-20 15:04:10 +02:00
Adam Wojasinski
5c1daef5ab drivers: spi: nrfx: Add SPIM Kconfig symbols for new instances
Add support for upcomming SPIM instances.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-10-20 15:03:17 +02:00
Niek Ilmer
9e6b1d5ba6 SOC: Smartbond: Add DA14695
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.

Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
2023-10-20 14:51:49 +02:00
Nazar Palamar
4d76e26f17 drivers: pinctrl: Update Infineon CAT1 pinctrl driver
- if we have input enable use CY_GPIO_DM_xxxx else
CY_GPIO_DM_xxx_IN_OFF;

- added bias_high_impedance option

- Updated HIGHZ drive mode, now it sets if:
--- we have bias_high_impedance
--- or if input_enable and no addition bias mode

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2023-10-12 15:17:35 +03:00
Andrzej Kuros
adec56bcee nrf5340: pretick decoupled from workaround anomaly 160
Coupling in code between workarounds for anomaly 160 and anomaly 165
(pretick) is decreased.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-10-11 11:09:29 +02:00
Andrzej Kuros
3eef769209 nrf53: fix RTC pretick for RTC rescheduling by other interrupts
It might happen that while some interrupt handler other than for RTC0
or RTC1 (e.g. for RADIO) is executed, the scheduled pretick CC triggers.
This starts pretick pulses due to the loop through IPC. The change
in pretick schedule did not stop the pretick pulses going through IPC
loop, what caused heavy increase in power consumption.

This commit fixes this behavior.
Added also clarifications for Kconfig option `SOC_NRF53_RTC_PRETICK`.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-10-11 11:09:29 +02:00
Andrzej Kuros
c4e53dabf7 nrf53: fix RTC pretick power usage for events on RTC0
For RTC0 events the RTC1 pretick event was not cleared what caused the
WDT to be not stopped. This resulted in increased power usage.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-10-11 11:09:29 +02:00
Flavio Ceolin
e7bd10ae71 random: Rename random header
rand32.h does not make much sense, since the random subsystem
provides more APIs than just getting a random 32 bits value.

Rename it to random.h and get consistently with other
subsystems.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-10-10 14:23:50 +03:00
Daniel DeGrasse
faf5593272 soc: arm: nxp_lpc: Only clock core from PLL1 when CONFIG_FLASH=n
Do not clock the LPC55xxx cores from PLL1 when CONFIG_FLASH is set. This
is required due to the following limitation of the flash controller
(documented in the reference manual):

Flash operations (erase, blank check, program) and reading a single word
can only be performed for CPU frequencies of up to 100 MHz. These
operations cannot be performed for frequencies above 100 MHz.

The PLL1 clock source will result in a core clock of 150MHz, which
violates this requirement.

Fixes #62963

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-10-08 11:25:02 +01:00
Yonatan Schachter
c461441cc5 soc: silabs: Added Kconfig to indicate the existence of a radio PHY
Added SOC_GECKO_HAS_RADIO symbol, to indicate that a SoC has a radio
phy, so that radio related code would only apply to devices with radio.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2023-10-04 10:30:00 +03:00
Andrzej Kuros
d44e96e486 nrf53: pretick with NRF_802154_RADIO_DRIVER
The `SOC_NRF53_RTC_PRETICK` option is now allowed to be used with
`NRF_802154_RADIO_DRIVER`.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Andrzej Kuros
e03d5d4c6d nrf53: RTC pretick allows user channels and require just one CC
The nrf53 pretick can be used with non-zero
`NRF_RTC_TIMER_USER_CHAN_COUNT` Kconfig option.

The nrf53 pretick requires just one RTC1 CC channel.

The nrf53 pretick handles also RTC1 and RTC0 both CCs and OVERFLOW
events by examination of events scheduled on them. The pretick is set
based on number of ticks to the closest event scheduled that can trigger
an interrupt.

Because the operation in `z_arm_on_enter_cpu_idle` hook would
take too much time with interrupts disabled, the
`z_arm_on_enter_cpu_idle_prepare` hook enabled by Kconfig option
`ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK` is used. It performs RTC0 and RTC1
examination, and sets pretick without interrupts being blocked.

The LDREX/STREX are leveraged to detect if exception took place
between start of `z_arm_on_enter_cpu_idle_prepare` and
`z_arm_on_enter_cpu_idle`. If exception has not been taken, the pretick
calculation can be trusted because source data could not changed and
too much time could not pass. Otherwise the sleep attempt is disallowed,
the idle will loop again and try later.

Prompt for `SOC_NRF53_RTC_PRETICK` Kconfig option allows to control
this option by an user and turn the feature off if necessary.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Krzysztof Chruściński
31eaffdf05 nrf53: Add RTC pretick
Add RTC pretick option that triggers HW activity one tick before and
RTC event that leads to the interrupt. Option is active only on nrf53
network core.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Guillaume Gautier
6f76e0dcf8 soc: arm: st_stm32: stm32u5: add stm32u5a5 soc
Add STM32U5A5 SOC

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-09-29 10:34:33 +02:00
Manuel Argüelles
d212e50eaf soc: nxp_s32: enable RTU.PIT timers for S32ZE
Each RTU includes one PIT instance that can be used by any
of the cores.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-29 09:47:35 +02:00
Dat Nguyen Duy
8185faa0cb drivers: dma_mcux_edma: add support dma driver for s32k344
On S32K344, the offset in memory map between each channel
is 0x4000 for most channels, but there is specific case is
between channel 11 and 12 which is 0x1D4000 instead. As a
consequence, 32 channels are divided to two parts: one
starts from channel 0 -> 11. The other is from channel 128
to 145. The channel gap is from 12 -> 127.

For user and data structures in shim driver, the channel's
value comes from 0 --> 31. Above constraint will be counted
when interact with the mcux sdk

Beside that, the DMAMUX register in this platform is very
specific, not in identical with DMAMUX channel, so shim
driver is updated to cover this case

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2023-09-27 14:02:09 -05:00
Flavio Ceolin
646a06c9fe random: Fix kconfig symbol name
s/CSPRING_ENABLED/CSPRNG_ENABLED/g

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-09-27 11:55:10 -05:00
Jeff Daly
83de11d9f3 Microchip MEC172X: Rework GPIO definitions to separate package types.
MEC172X has 2 package sizes with additional pins on the -LJ package.
This commit separates the package-specific parts into different files.
In addition, this patch removes unnecessary package-specific enums in
favor of calculated offsets into the desired registers.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
2023-09-26 16:53:29 +02:00
Yong Cong Sin
3300b31de8 boards: ti_k3: prevent header dependencies
These headers are using things like `uint32_t` & devicetree
macros, so they should include the `devicetree.h` & `types.h`.

Otherwise they depend on the parent file to have those headers
included before they are included.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-26 12:03:54 +02:00
Yong Cong Sin
b49d0addc5 soc: ti_k3: guard the soc header
Add macro guard to the soc header to prevent multiple inclusion

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-26 12:03:54 +02:00
Alberto Escolar Piedras
c7c3c82aa0 soc nordic_nrf: Select new compatible kconfig options
Select the newly introduced nrf53 compatible kconfig options.
These are common both for real HW and for simulated HW,
allowing SW to behave appropriately for both.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-09-25 16:42:45 +02:00
Daniel DeGrasse
9e5188353e soc: arm: nxp_imx: add support for SMARTDMA for RT5xx
Add support for SMARTDMA to RT5xx SOCs. SMARTDMA ram banks will be
powered up, so code can be programmed into this region for the SMARTDMA
engine.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-09-25 09:46:55 +02:00
Roland Lezuo
f4c901b82d soc: arm: st_stm32: add config to allow debugger attach in sleep/stop modes
Adds CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP to allow debugger attaching in
sleep/stop mode of STM32 parts. Mainly useful for debugging. Move DBGMCU
from part-sepcific power.c to common soc_config.c. CONFIG_USE_SEGGER_RTT
depends on this as well.

Signed-off-by: Roland Lezuo <roland.lezuo@embedded-solutions.at>
2023-09-22 15:31:47 +02:00
Aaron Ye
09e7e2db51 soc: arm: Add support for Ambiq Apollo4 Blue Plus.
Added devicetree and Kconfig for Apollo4 Blue Plus SoC.
They are needed for the apollo4p_blue_kxr_evb board.

Signed-off-by: Aaron Ye <aye@ambiq.com>
2023-09-22 08:29:29 -05:00
Declan Snyder
15bc6a2389 soc: lpc55s3x: Enable VREF
Add node for VREF0 peripheral to LPC55S3X SOC DT

Clock VREF peripheral if status = okay in DT

Enable VREF on lpcxpresso55s36

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-09-21 09:26:57 +02:00
Manuel Argüelles
7fca0aa8a6 nxp_s32: enable clock control for S32ZE
Enable clock control driver for NXP S32ZE SoCs and add clock sources
definitions for devicetree.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-20 17:25:44 +01:00
Gerard Marull-Paretas
49df14c08a dts: arm: nordic: fix cryptocell description
The ARM Cryptocell 310/312 IP is wrapped by Nordic specific registers.
It is organized as follows:

- Base address: Nordic wrapper
- Base address + 0x1000: ARM Cryptocell IP registers

Following more standard devicetree conventions, use a single node for
what is exposed as a single peripheral. The node contains 2 register
entries, one for the wrapper and a second one for the 3rd party IP.
Compatibles are used from more specific (nordic,cryptocell) to more
generic (arm,cryptocell-3xx).

Other minor fixes: peripheral is disabled by default (as it should be in
SoC dts files).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-20 13:54:38 +01:00
Jonas Otto
2baac8e769 soc: Add support for STM32F072X8
Adds support for the STM32F072X8 SOC, which is a variant of the
existing STM32F072XB with less flash.

Signed-off-by: Jonas Otto <jonas@jonasotto.com>
2023-09-19 15:25:09 +01:00
Filip Kokosinski
8131a67d6f soc/arm/silabs_exx32: select missing CONFIG_SOC_GECKO_SERIESx
This commit:
* adds the `CONFIG_SOC_GECKO_SERIES0` Kconfig option for Gecko Series 0
  SoCs
* selects the proper `CONFIG_SOC_GECKO_SERIESx` option where it's currently
  missing

Fixes #62806.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-09-19 09:32:55 -04:00
Gerard Marull-Paretas
efb8408ba2 soc: arm: nordic_nrf: nrf52: deprecate GPIO_AS_PINRESET
In favor of devicetree property in the UICR node.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-18 13:14:08 +02:00
Yonatan Schachter
fb140de04a soc: silabs_exx32: Select SOC_GECKO_SERIES1 for 1x devices
Select SOC_GECKO_SERIES1 for all Silabs devices of the series 1x.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2023-09-18 12:55:40 +02:00
Daniel DeGrasse
23264c4b3a soc: arm: nxp_imx: introduce ROM ramloader feature
The iMX RT bootrom allows the user to load images into RAM regions from
flash by providing a correctly configured boot header. In particular, if
the boot header contains a load address within RAM, the bootroom will
automatically copy the image to the load address before executing it

Introduce CONFIG_NXP_IMX_RT_ROM_RAMLOADER to enable this feature. This
Kconfig will shift the LMA of a image built to run in a RAM region to
reside in the default FlexSPI boot region, which allows the image to be
loaded to the FlexSPI region using west. This is intended to simplify
development of applications executing from RAM on iMX RT based systems.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-09-15 14:37:07 -05:00
Gerard Marull-Paretas
0762008586 soc: arm: nordic_nrf: deprecate CONFIG_NFCT_PINS_AS_GPIOS
In favor of the new UICR nfct-pins-as-gpios devicetree property.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 16:05:28 +02:00
Carlo Caione
e4a125b6a4 dt: Make zephyr,memory-attr a capabilities bitmask
This is the final step in making the `zephyr,memory-attr` property
actually useful.

The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.

With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.

The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).

For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_VOLATILE |
			       DT_MEM_NON_CACHEABLE |
			       DT_MEM_OOO )>;
   };

The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-region = "NOCACHE_REGION";
       zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
   };

See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).

The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
			       DT_MEM_SW_ALLOCATABLE )>;
   };

Or maybe we can leverage the property to specify some alignment
requirements for the region:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_CACHEABLE |
			       DT_MEM_SW_ALIGN(32) )>;
   };

The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).

When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`

Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory  region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-09-15 12:46:54 +02:00
Gerard Marull-Paretas
aaeb0a672e toolchain: only include <zephyr/toolchain.h>
It is wrong to use toolchain-specific header files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 09:27:30 +02:00
Marcin Niestroj
f15e7c5909 soc: arm: st: set SWO reference frequency based on 'rcc'
Configure SWO reference frequency to be the same as
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. This should make all ST boards ready to
be used with SWO, without configuring any other devicetree property.

Tested with NUCLEO-L476RG and NUCLEO-H563ZI.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2023-09-13 16:29:56 +02:00
Jordan Yates
1e06ba2328 soc: arm: nordic: handle nRF52832 anomaly 109
Enable workaround for anomaly 109 by default when affected peripherals
are enabled.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-09-13 12:05:27 +02:00
Paulo Santos
395395b266 soc: arm: efr32bg22: add missing GPIO flag
Add the missing SOC_GECKO_GPIO selection to the EFR32BG22 SoC Series.

Signed-off-by: Paulo Santos <pauloroberto.santos@edge.ufal.br>
2023-09-13 11:49:27 +02:00
Huifeng Zhang
2c22e83dfb include: arch: arm: Remove aarch32 directory
This commit follows the parent commit work.

This commit introduces the following major changes.

  1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
    to the 'include/zephyr/arch/arm' directory.

  2. Change the path string which is influenced by the changement 1.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-09-13 10:08:05 +01:00
Huifeng Zhang
df41deac1c arch: arm: Remove aarch32 directory
It doesn't make sense to keep the aarch32 directory in the
'arch/arm/core' directory as the aarch64 has been moved out.

This commit introduces the following major changes.

  1. Move all directories and files in 'arch/arm/core/aarch32' to
    'arch/arm/core' and remove the 'arch/arm/core/aarch32' directory.
  2. Move all directories and files in 'arch/include/aarch32' to
    'arch/include' and remove the 'arch/include/aarch32' directory.
  3. Remove the nested including in the 'arch/include/kernel_arch_func.h'
    and 'arch/include/offsets_short_arch.h' header files.
  4. Change the path string which is influenced by the changement 1
    and 2.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-09-13 10:08:05 +01:00
Albort Xue
2073dc9cdd boards: arm: lpcxpresso55s36: Added dac support for LPC55S36
Added dac support for the LPC55S36 board, updated lpc55xxx/soc.c to
enable clock and power for dac0.

Signed-off-by: Albort Xue <yao.xue@nxp.com>
2023-09-11 19:55:26 +02:00
Mulin Chao
eacdadf270 driver: adc: npcx: remove threshold-reg-offset DT property
Remove `threshold-reg-offset` DT property and implement them with static
inline functions in `reg_def.h`

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-09-08 14:43:37 +02:00
Mulin Chao
72ee4f75ef driver: adc: npcx: add multi-device support in npcx adc driver
Add multi-device support in npcx adc driver since there is more than one
adc module in npcx4 series. And each adc's reference voltage might be
different, this CL introduces the `vref-mv` prop. to select its own
reference voltage.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Kate Yen <htyen@nuvoton.com>
2023-09-08 14:43:37 +02:00
Piotr Dymacz
98e104fe3d soc: cc13x2_cc26x2: disable CCFG when building MCUboot chain-loaded images
The 'CCFG' (Customer Configuration) occupies 88 bytes in topmost flash
sector (8 KiB) and is by default always included in the final image.

This disables including CCFG part when building images for chain-loading
by the MCUboot bootloader.

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
2023-09-07 08:51:21 -05:00
Richard Wheatley
a92008c17d soc: arm: ambiq: apollo4: add simobuck init to apollo4 init
Adds comments and simobuck init function for low power.

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2023-09-06 09:33:06 +02:00
Warren Buffer
09577b0a0e soc: Added support for EFR32MG12P433F1024GM68
Added devicetree and Kconfig for EFR32MG12P433F1024GM68, needed for
the BRD4170A radio board by Silicon Labs.

Signed-off-by: Warren Buffer <warren.buffer78@gmail.com>
2023-09-05 16:16:30 +02:00
Gerard Marull-Paretas
35479cccac soc: arm: atmel_sam0: common: bossa: add missing init.h
Because modules uses SYS_INIT, from init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-05 12:19:04 +02:00
Vinayak Kariappa Chettimada
9ede8cd87e dts: nRF: Add missing headermask binding for NRF_CCM
Add missing headermask binding for NRF_CCM peripheral and
define HAS_HW_NRF_CCM_HEADERMASK Kconfig.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2023-09-05 10:04:57 +02:00
Gerard Marull-Paretas
4747218837 soc: arm: ti_simplelink: cc13x2_cc26x2: compile power.c if PM_DEVICE=y
power.c contains some struct definitions required by the HAL when using
PM_DEVICE.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-04 12:22:55 +02:00
Sreeram Tatapudi
09a07e42c0 drivers: cat1: Updates to support latest version of HAL/PDL
- Refactoring to support latest versions of HAL/PDL

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2023-09-01 09:52:25 +02:00
Gerard Marull-Paretas
c315c9b97c soc: arm: ti_simplelink: cc13x2_cc26x2: add support for sys_poweroff
Implement sys_poweroff() hooks, based on previous SOFT_OFF
implementation.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 14:42:26 +02:00
Rahul Arasikere
da55c26593 soc: arm: Add Kconfig option for SOC_STM32F765XX
Adds a new Kconfig menuchoice for the STM32F765xx series.

Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
2023-08-31 10:21:25 +02:00
Gerard Marull-Paretas
b459064ec1 soc: arm: st_stm32: wl: add support for sys_poweroff
Implement the hook for sys_poweroff based on the SOFT_OFF code. Note
that standby mode was a substate of SOFT_OFF, however, it was not
supported judging from defined DT states. It can be added later using
the STANDBY state.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
574360cba0 soc: arm: st_stm32: wba: remove redundant entry in pm_exit_post_ops
SOFT_OFF is not supported for this SoC, also, SOFT_OFF will never reach
the PM post ops.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
d7a0b4fa93 soc: arm: st_stm32: u5: add support for sys_poweroff
Add support for the sys_poweroff hook, re-using code from the SOFT_OFF
state.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
b97b17a4f5 soc: arm: st_stm32: wb: add support for sys_poweroff
Implement the sys_poweroff() hook. The hsem locking is not part of the
implementation, it doesn't seem necessary after
https://github.com/zephyrproject-rtos/zephyr/pull/42409 but I may be
wrong. Needs verification.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
643383b060 soc: arm: st_stm32: l4: add support for sys_poweroff
Convert SOFT_OFF handler to sys_poweroff hook.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
11242691cd soc: arm: st_stm32: l0: remove unsupported state
SOFT_OFF state (which translates to standby) doesn't seem to be
supported according to the L0 DT files. Also, by definition soft off
implies context loss, ie boot from scratch, but the implementation
expected a call to the PM exit hook.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
00ff421129 soc: arm: nxp_imx: rt10xx: s/device.h/init.h
File was not using any device.h API, but init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:53:50 +02:00
Gerard Marull-Paretas
b3b8a19e02 soc: arm: nuvoton_npcx: common: s/device.h/init.h
File was not using any device.h API, but init.h (SYS_INIT).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:53:35 +02:00
Tristen Pierson
1f2180e8ff drivers: adc: adc_sam0: fix c20 and c21 reference not setting
drivers: adc: adc_sam0: fix c20 and c21 reference not setting

On c20 and c21 variants, the adc_sam0 driver is failing to honor the
enable-protected status of the REFCTRL register when writing the channel
config's reference into it. This causes the reference to never be set
when adc_sam0_channel_setup is called since the ADC is not disabled
prior to the write. Fix it by adding the
ADC_SAM0_REFERENCE_ENABLE_PROTECTED definition to the c20 and c21 soc.h
files. This effectively disables the ADC during writes to the REFCTRL
register, thus honoring the enable-protected behavior of this register.
I'm assuming ADC_SAM0_REFERENCE_ENABLE_PROTECTED exists for this type
of situation and therefore this was the approach taken. After making
the change, I was able to verify proper ADC readings by measuring
voltage on an ADC pin and observing correct values. Reverting back prior
to this change, running the same test yields reading 0's.

Fixes: #61975

Signed-off-by: Tristen Pierson <tpierson@bitconcepts.tech>
2023-08-30 10:21:15 +02:00
Francois Ramu
66caf58265 soc: arm: stm32h7x mapping system memory region
System memory declared by the MPU as 'Strongly Ordered'
with region attributes which will inhibit the speculative fetch,
preventing the Flash RDSERR.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-08-30 10:17:39 +02:00
Gerard Marull-Paretas
f88d21cdb9 soc: arm: nordic_nrf: nrf53: sync_rtc: add missing init.h
File was using SYS_INIT, from init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-29 14:35:45 +01:00
Mulin Chao
f942b44c56 soc: arm: npcx: move workaround methods for npcx series to its soc.c
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-08-28 08:22:10 +01:00
Maximilian Deubel
4cde3ea70f soc: arm: nordic_nrf: nrf91: rename nRF9161 SICA to LACA
This patch corrects the name of the nRF9161,
which is LACA, not SICA.

Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
2023-08-25 13:48:17 +02:00
Maximilian Deubel
dc954977b7 soc: arm: nordic_nrf: nrf91: add nRF9131 LACA
This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.

Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
2023-08-25 11:56:12 +02:00
Mateusz Sierszulski
be149593c9 drivers: pinctrl: Add more config options for Ambiq Apollo4
This commits add more configuration options
for Ambiq Apollo4 pinctrl driver.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2023-08-25 10:31:58 +02:00
Marcin Niestroj
19d7b26238 soc: arm: stm32h5: support SWO
In case of stm32h5 both LL_DBGMCU_EnableTraceClock() and
LL_DBGMCU_SetTracePinAssignment() need to be called in order to properly
configure SWO output.

Select HAS_SWO, so that logging over SWO can be enabled.

Tested with ST's fork of openocd [1].

[1] https://github.com/STMicroelectronics/OpenOCD

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2023-08-24 18:21:52 -05:00
Daniel DeGrasse
905512438e soc: arm: nxp_imx: update iMX RT boot header to handle CONFIG_XIP=n
Update iMX RT boot header to support CONFIG_XIP=n, when the image is not
linked into the flash space. Also, update the boot header to correctly
calculate the flash used size within the boot data header. This field is
used by the iMX boot ROM to determine how much data to copy when running
from RAM, so using the correct size fixes an issue where the ROM would
copy more data than needed.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-24 22:09:01 +01:00
Gerard Marull-Paretas
94a4d38ed9 cmsis: remove unnecessary includes
Some files included <cmsis_core.h> for nothing, delete it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-08-24 13:20:21 +02:00
Gerard Marull-Paretas
9c961571a2 modules: cmsis: move glue code to modules/cmsis
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).

To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.

All files including CMSIS have been updated.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-08-24 13:20:21 +02:00
Jun Lin
df0646ed6e driver: flash: npcx: add support for npcx4 series
This CL introduces new Flash Interface Unit (FIU) hardware in npcx4
series. The different operations of npcx9 and npcx4 FIU include:

1. 4-byte mode support for DRA mode move to SPI_DEV reg
2. To access the second flash in DRA mode, we need to configure
   SPI_DEV_SEL field in BURST_CFG additionally.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-08-24 10:42:33 +01:00
Mulin Chao
5c7ab5c2bf driver: clock_control: npcx: add support for npcx4 series
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.

For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-08-24 10:42:33 +01:00
Mulin Chao
8ae0bb8b70 soc: npcx: add soc drivers for npcx4 series
This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f
and npcx4m8f support, we also modified the register offset of
LV_GPIO_CTL and PUPD_EN for npcx4 series.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-08-24 10:42:33 +01:00
Jeff Daly
f868d391ec Samples: Fix XEC clock control sample code for MEC172x using new GPIOs.
The XEC clock control driver sample code uses enum indexes to offset to
the desired GPIO CTRL register of the package.  These enums are only
used in this example code and are being removed in favor of calculated
indexing into the specific GPIO register memory map.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
2023-08-23 10:06:13 +02:00
Moritz Fischer
9e8a8b4e85 soc: arm: common: cortex_m: Move arm_mpu_mem_cfg.h
Move arm_mpu_mem_cfg header to common include directory.

The benefits are two-fold:
- Allow for out of tree SoC definitions to use them to
  define mpu_regions.
- Remove odd relative include path

Signed-off-by: Moritz Fischer <moritzf@google.com>
2023-08-16 14:56:06 +02:00
Manuel Argüelles
298f028d20 soc: nxp_s32: rename family to SOC_FAMILY_NXP_S32
Rename NXP S32 device's family to SOC_FAMILY_NXP_S32 to avoid ambiguity.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-16 10:21:26 +02:00
Manuel Argüelles
acbdf1f53c modules: rename S32 to NXP_S32
Rename module from `S32` to `NXP_S32` to avoid ambiguity.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-16 10:21:26 +02:00
Henrik Brix Andersen
cafcf9a474 soc: arm: nxp: lpc55xxx: Change PLL1 frequency to 144 MHz
Reduce the main clock frequency from 150MHz to 144MHz which allows meeting
the full range of CAN bitrates.

Fixes: #60811

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-08-16 10:20:44 +02:00
Ederson de Souza
91450a4358 soc/arm/microchip_mec/mec17x: Initialise GPIO after ECIA
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the ECIA initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.

This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after ECIA.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2023-08-15 10:13:37 -07:00
Ederson de Souza
0295edf834 soc/arm/microchip_mec/mec1501: Initialise GPIO after interrupts
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the SOC initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.

This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after SOC.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2023-08-15 10:13:37 -07:00
Tanmay Shah
33a25371b6 soc: zynqmp: increase SRAMP_PRIV MPU region size
openamp shared memory regions can be anywhere in DDR memory
withing 2G range. Current SRAM_PRIV region is 64M which
prevents access of shared memory (vrings) by RPU (cortex-r5)
if it is out of 64M range. This patch allows vrings to be in DDR within
2G address space.

Developed-by: Dan Millea
Commited by: Tanmay Shah

Signed-off-by: Dan Milea <dan.milea@windriver.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
2023-08-15 11:23:04 +00:00
Benjamin Lemouzy
35849319e0 soc: arm: imx_rt10xx: support enet1 external clock
Configure ENET_REF_CLK direction as input when
CONFIG_ETH_MCUX_RMII_EXT_CLK is set to allow Ethernet external clock
usage.

Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
2023-08-14 08:21:26 -05:00
Markus Fuchs
4fd5a9cee1 boards: efr32_radio: Add PM support using BURTC timer
Add power management support running in EM1 and EM2 from BURTC timer.

Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
2023-08-09 08:24:52 +00:00
Markus Fuchs
536894bb31 boards: efr32_radio: Enable sleep timer
Enable sleep timer (stimer0) node for the efr32_radio_brd4187c board.

Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
2023-08-09 08:24:52 +00:00
Markus Fuchs
27af62603c drivers: counter: gecko: Add SYSRTC stimer support
SiLabs' sleeptimer driver supports several hardware peripherals, of
which the counter driver so far only supports the RTCC-based variant.

This patch adds support for the SYSRTC-based sleeptimer implementation,
which is required for Gecko SoCs that do not have an RTCC module.

Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
2023-08-09 08:24:52 +00:00
Gerard Marull-Paretas
b990082bef soc: arm: nordic_nrf: fix poweroff for nrf53/91
nRF53/91 require usage of nrf_regulators_system_off, so the API is not
common with nRF51/52. This was an oversight during the conversion.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-09 08:21:34 +00:00
Benjamin Perseghetti
109d91aaf8 board: Add NXP VMU RT1170 board support package
Adds support for the NXP VMU RT1170 board. This Vehicle
Management Unit based on the i.MX RT1176 brings a fantastic
combination of sensors and IO all on one board for development
of various systems. It is also the featured board for
CogniPilot's Cerebri - VMU autopilot software based on Zephyr.

Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
2023-08-08 12:09:10 -05:00
Daniel DeGrasse
c3dfc2220a soc: arm: nxp_imx: rt: Remove CONFIG_OCRAM_NOCACHE setting
Remove CONFIG_OCRAM_NOCACHE setting, as this is now possible to achieve
using devicetree linker regions, and there is no point in having a
specific Kconfig for one memory region on the RT series like this.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-04 16:11:37 -05:00
Daniel DeGrasse
7e646b56a1 soc: arm: nxp_imx: rt: enable SOC fixed MPU regions, add SDRAM0 region
Enable SOC fixed MPU regions by default for the RT10xx/RT11xx SOC lines.

Additionally, add code to handle defining the SDRAM0 region as
device type (non cacheable, non shareable). This behavior can
be disabled with CONFIG_NXP_IMX_EXTERNAL_SDRAM=y. Set this Kconfig
for all boards in tree using SDRAM.

This will resolve an issue present on the RT11xx series where
the core may execute speculative prefetches to the SDRAM region when
no SDRAM is present on the board, resulting in the system faulting.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-04 16:11:37 -05:00
Daniel DeGrasse
c85d3dd828 soc: arm: nxp_imx: don't default CONFIG_DEVICE_CONFIGURATION_DATA=y
Don't default CONFIG_DEVICE_CONFIGURATION_DATA to enabled for iMX RT
SOCs, as this configuration block is only used when the board needs
peripherals like the external memory controller setup from reset by the
bootrom.

Enable this feature on all in tree boards that will require it,
and document the change to the default value in release notes.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-04 16:11:37 -05:00
Gerard Marull-Paretas
2e3bc500a9 soc: arm: nxp_imx: rt5xx: drop SOFT_OFF
SOFT_OFF is now handled via sys_shutdown() API.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-04 16:59:36 +02:00
Gerard Marull-Paretas
b5d05e9670 soc: arm: nxp_imx: rt5xx: add support for power off
Implement support for sys_poweroff(). Code re-used from the PM SOFT_OFF
implementation.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-04 16:59:36 +02:00
Gerard Marull-Paretas
96b3827313 soc: arm: nordic_nrf: drop PM hooks
Nordic SoCs do all power management automagically when going to idle (ie
k_cpu_idle()). The only extra state, system off, is now handled via
sys_shutdown(), so there's no need to support the PM subsystem.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-04 16:59:36 +02:00
Gerard Marull-Paretas
526a7bb20d soc: arm: nordic_nrf: add support for poweroff
Implement the z_sys_poweroff() hook and select HAS_POWEROFF.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-04 16:59:36 +02:00
Manuel Argüelles
ab346c08b5 drivers: nxp_s32_netc: fix init priorities
So far the init priories were:
enetc_psi0=60 < enetc_vsin=61 < emdio=70 < ethernet-phy=80
because the Ethernet PSI driver was doing global initialization for the
whole NETC complex, including enabling MDIO function (due to the way
the HAL works).

Change to use the default init priorities:
mdio=60 < phy=70 < eth=enetc_psi0=80 < enetc_vsin=81
by executing at an early stage the NETC global initialization. This also
allows to match the DT hierarchy representation of NETC with the
effective priorities assigned.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-04 13:55:45 +00:00
Maciej Sobkowski
1d45065e8a soc: arm: ambiq: apollo4x: configure STIMER
Disable SysTick when STIMER is in use and configure
SYS_CLOCK_HW_CYCLES_PER_SEC setting for it.

Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-04 10:48:58 +02:00
Maciej Sobkowski
8a670d0713 drivers: pinctrl: Add pinctrl driver for Apollo4
This commit addst pinctrl support for Apollo4 SoCs.

Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-04 10:48:58 +02:00
Maciej Sobkowski
0118886624 soc: arm: ambiq: apollo4: Add support for Apollo4 Plus SoC
Add all required parts (new SoC family/series, device tree) for
the Ambiq Apollo4 Plus SoC.

Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-04 10:48:58 +02:00
Gerson Fernando Budke
ee15b1ff05 soc: atmel: same5x: Disable cache
The sam0 CMCC configure Cortex-M cache controller. However, it is not
clear how the cache management should be performed. It is nor clear if
instructions like SCB_EnableICache can be used. In this case, if cache
management should be made only by CMCC it may require a dedicated
implementation.

Besides above, the CPU_CORTEX_M4 do not define cache by default which
can signal a bad configuration in tree since the SOC_SERIES_SAME54 do
not define which caches should be available.

This force cache controller disable to avoid issues.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
Gerson Fernando Budke
ea24dd40eb soc: atmel: sam: Fix cache management
The current platform initialization do not take in consideration cache
management for historic reasons. This fixes any miss configuration and
allow users to enable/disable caches at board definition. The default
value is cache disabled and the below examples are for SAMV71 which
have both I/D Cache available:

I Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE=n

D Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ICACHE=n

I/D Cache disabled:
CONFIG_ICACHE=n
CONFIG_DCACHE=n

I/D Cache Enabled:
CONFIG_CACHE_MANAGEMENT=y

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
Gerson Fernando Budke
45ad244212 soc: atmel: Enable platform specific init
This replace pre kernel initialization by the platform specific
initialization call. The platform specific init will configure
at very beginning the clocks, flash wait states and cache.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
Gerson Fernando Budke
5457c2d74e soc: arm: sam: Reorder copyright by year ascending
Adjust copyright order by ascending year order.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
Gerson Fernando Budke
0847e85088 soc: arm: atmel: Normalize Kconfig.series files
This update Kconfig.series files to normalize copyright date order from
lower to higher and reorder select entries.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
David Ullmann
bcc7499684 drivers: rt6xx ctimer pwm driver
using ctimer to implement pwm api
Signed-off-by: David Ullmann <davidu@meta.com>
2023-08-03 12:39:06 -04:00
Nicolas Pitre
9a748371eb timer: allow for configuring it out
Some configurations have the system timer driver hardwired in.
Let's make them compatible with CONFIG_SYS_CLOCK_EXISTS=n.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-08-03 10:29:46 +02:00
Manuel Argüelles
12627d329e soc: nxp_s32: s32k344: add EMAC support
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-03 10:28:20 +02:00
Ioannis Karachalios
34ce476ce6 soc: smartbond: da1469x: Support Global Foundries silicon
Add support for the GF silicon variant.

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
2023-08-02 14:00:39 +02:00
Manuel Argüelles
c7200cac00 soc: nxp_s32: add LPSPI to S32K344
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-01 09:51:16 +02:00
Henrik Brix Andersen
de656c1169 drivers: can: sam: do not select cache management
Do not select CONFIG_CACHE_MANAGEMENT in the Microchip SAM CAN driver
Kconfig but rather leave it up to the SoC/platform Kconfig to enable it as
needed and enable CACHE_MANAGEMENT by default for the Atmel SAM E70/V71 SoC
series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2023-07-31 19:38:22 +00:00
Antoine Bout
dbea999347 soc/arm/silabs: Kconfig: add SOC_GECKO_USE_RAIL kconfig option
Currently on zephyr, RAIL is used only for bluetooth. RAIL library is
needed to use efr32 radio regardless of the protocol used. We add
SOC_GECKO_USE_RAIL kconfig option to indicate if we use radio.
FPU is needed when using RAIL, we configure it if SOC_GECKO_USE_RAIL
is set.

Signed-off-by: Antoine Bout <antoine.bout@silabs.com>
2023-07-31 09:05:17 +00:00
Gerard Marull-Paretas
0b49b86f06 soc: arm: st_stm32: remove redundant PM_STATE_ACTIVE case
pm_state_exit_post_ops() will never be called with PM_STATE_ACTIVE.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-28 09:09:01 +00:00
David Ullmann
724a5cd54f board: add cy8ckit 062 pioneer
Tested with hello_world and blinky projects
Signed-off-by: David Ullmann <davidl.ullmann@gmail.com>
2023-07-27 15:26:40 -04:00
Cong Nguyen Huu
3d1285bc40 drivers: i2c_mcux: update to compatible with S32K344
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
2023-07-27 12:32:07 -05:00
Cong Nguyen Huu
36d63e132d boards: arm: mr_canhubk3: enable support for FlexCAN
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
2023-07-27 11:06:45 -05:00
Carles Cufi
acb8f6bf0b soc: nordic_nrf: Add nRF52833 QDAA variant
This variant has fewer pins.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2023-07-27 08:47:35 +00:00
Carles Cufi
b140963557 soc: nordic_nrf: Add nRF52840 QFAA variant
This variant has fewer pins.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2023-07-27 08:47:35 +00:00
Andriy Gelman
d8f955e375 drivers: pwm: Add driver for xmc4xxx using ccu8 module
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.

Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-07-26 15:09:41 +02:00
Andriy Gelman
23b6e4f507 drivers: pwm: Add driver for xmc4xxx using ccu4 module
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.

The CCU4 module also has a capture mode. Capture support will be added
in the future.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-07-26 15:09:41 +02:00
Wojciech Sipak
69d0f03ebd soc: quicklogic_eos_s3: remove unneeded code
Pinmuxing is now done by a pinctrl driver, not by board.c,
so the code used previously for pinmuxing can be removed.

Fixes #59186.

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-26 14:59:59 +02:00
Wojciech Sipak
bff69f5384 drivers: pinctrl: add driver for EOS S3
This adds a new pinctrl driver for Quicklogic EOS S3 SoC

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-26 14:59:59 +02:00
Wojciech Sipak
40fa96506b drivers: pinctrl: Add pinctrl driver for Gecko Series 1
This adds a new pinctrl driver for EFM32.

Co-authored-by: Todd Dust <Todd.Dust@silabs.com>
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-26 14:33:03 +02:00
Florian Grandel
d34709121f drivers: cc13xx_cc26xx: pinctrl: support edge detection
Introduces support for SoC-specific input-edge-detect configuration to
the CC13/26xx pinctrl driver.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-26 14:32:53 +02:00
Florian Grandel
0dcbb22265 drivers: cc13xx_cc26xx: pinctrl: support drive strength
Introduces support for drive-strength configuration to the CC13/26xx
pinctrl driver.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-26 14:32:53 +02:00
Florian Grandel
31fb5f53d2 drivers: cc13xx_cc26xx: pinctrl: fix header conflict
CC13/26xx's pinctrl_cc13xx_cc26xx.c driver included ioc.h and
(indirectly) pinctrl_soc.h which contained duplicate defines.

This change removes the header conflict and redundant definitions.

This prepares for subsequent changes in this change set that add
additional flags to the pinctrl driver which would otherwise trigger the
header conflict.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-26 14:32:53 +02:00
Andrzej Głąbek
fa609e5844 drivers: spi: nrfx: Clean up driver instantiation
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
  drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
  peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
  and enabled proper nrfx driver instance; instead, use one option per
  peripheral type and include the corresponding shim driver flavor into
  compilation basing on that option (not the one that enables the nrfx
  driver as it was incorrectly done so far in some cases)

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-07-25 13:41:51 +02:00
Carlo Caione
15e84cbfac dts: Move to 'zephyr,memory-attr'
Move to 'zephyr,memory-attr' and use the newly introduced helpers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-07-25 11:22:10 +02:00
Fabio Baltieri
e065e5c600 soc: silabs_exx32: define an empty pm_state_exit_post_ops
Some EFR32 build broke after 3d2194f11e with:

pm.c:152: undefined reference to `pm_state_exit_post_ops'

Add an extra empty function to make this one build again.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-07-25 10:43:33 +02:00
Wojciech Sipak
e9613856cb boards: arm: add efm32gg_sltb009a board
- Add Silabs SLTB009A board
- Add Silabs EFM32GG12B SoC

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-25 09:11:11 +02:00
Mathieu Anquetin
3e2765cc0d dts: arm: st: Add dts and soc additions for stm32f105xb
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.

Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
2023-07-24 14:15:42 +00:00
Peter van der Perk
6971865d01 soc: nxp_imx: rt11xx enable xbar driver
Add bindings to nxp,mcux-bar dirver

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2023-07-24 08:29:21 -05:00
Grant Ramsay
c0d144b3cd soc: arm64: add comments expanding the K3 acronym
This may be useful to users who do not know what K3 means

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-07-24 09:10:09 +00:00
Derek Snell
e44314aeee soc: nxp_imx: rt5xx: fix part numbers in WLCSP
Dropped R from part numbers to match MCUXpresso SDK

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2023-07-21 09:09:55 -05:00
Mulin Chao
f34fff91bc driver: flash: npcx: introduce npcx flash driver
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-07-20 16:22:47 +02:00
Mulin Chao
7411fbcb5b pinctrl: npcx: add DEV_CTLx configuration support
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-07-20 16:22:47 +02:00
Gerard Marull-Paretas
55f5a75c58 pm: remove unnecessary __weak from pm_state_set/pm_exit_post_ops
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas
3d2194f11e pm: introduce HAS_PM
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas
26bf349ab1 pm: drop HAS_NO_PM
Remove HAS_NO_PM option, in preparation for a new HAS_PM option
(inverted logic).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Wojciech Sipak
c811a4f430 drivers: adc: add ADC driver for EFM32
This adds a driver for ADCs available on EFM32

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-18 11:05:39 +00:00
Emilio Benavente
c6e3bac4f2 soc: arm: lpc55xxx: Updated clock init
Updated the clock init to reflect the sdk also
updated the clock frequencies to reflect the
respective soc clock values, this file originally
contained unexpected clock values, updated comments
to reflect changes and got rid of doxygen style
comments

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2023-07-17 13:05:44 -05:00
L Lakshmanan
71244acd22 board: ti_am62x_sk_m4: Added board files for TI AM62X SK
Added configuration and documentation files for the AM62x board
M4 core.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-16 07:33:34 -04:00
L Lakshmanan
0e97c9d14d soc: ti_k3: Added SoC files for Cortex M4F on ti_am62x_sk
Added SoC support files for the Cortex M4F core on the TI AM62X SK EVM.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-16 07:33:34 -04:00
Guillaume Gautier
8432081f51 soc: arm: st_stm32: stm32wba: Add LPTIM to Kconfig
For STM32WBA, enable LPTIM if Power management is enabled

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-12 11:48:10 +02:00
Guillaume Gautier
38722ce9d0 soc: arm: st_stm32: stm32wba: Add Power support
Add Power support

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-12 11:48:10 +02:00
Guillaume Gautier
3bd3f8d1c6 soc: arm: st_stm32: stm32wba: Add soc config for STM32WBA
Add soc config for STM32WBA SoC series

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-11 15:05:05 +02:00
Bill Waters
541482ff20 driver: i2c: infineon: Adding XMC4 I2C driver
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now

Signed-off-by: Bill Waters <bill.waters@infineon.com>
2023-07-11 09:43:19 +02:00
Florian Grandel
38e2eb8fe6 soc: ti: cc13/26xx: clean up include hierarchy
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-07 18:46:24 -04:00
Andrzej Kuros
abd90085ac soc: arm: nrf53: workaround pop lr after wfi crash
On nRF5340 net core it was observed that when `wfi` instruction was
followed by `pop {r0, lr}` in the `arch_cpu_idle` function,
the value of `lr` sometimes got read as 0 from memory despite
having correct value stored in the memory.

This commit inserts additional `nop` instruction after waking up
to delay access to the memory.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-07-07 14:32:27 +02:00
Marc Desvaux
4293835192 soc : arm: st_stm32: stm32h5: add linker for STM32H5X
add some modifications for linker

Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
2023-07-07 10:06:54 +00:00
Mulin Chao
2cf3caa11c driver: wdt: npcx: add WDT_OPT_PAUSE_HALTED_BY_DBG support.
This CL adds WDT_OPT_PAUSE_HALTED_BY_DBG support by enabling freeze mode.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-07-07 09:19:50 +02:00
Manuel Arguelles
405160ca62 boards: mr_canhubk3: enable LPUART serial driver
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.

Use the board's debug connector (P6 / LPUART2) as default console.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
00125a4d1e soc: nxp_s32: generalize pinctrl header for all family
Unify the pinctrl_soc.h header for all the NXP S32 family by using
the HAL macros that expose the features supported on specific
devices. This approach still need a different binding for each device to
expose in DT different properties and allowed values.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
8a47dd5ff8 soc: nxp: s32k3: enable clock control
Enable clock control by default on S32K344 SoCs and add clock
definitions.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
b22f1162f3 soc: nxp: s32k: support minimal power and reset
Introduce minimal power initialization for NXP S32 SoCs and allow to
reset the SoC through the sys_reboot() API.

Presently only S32K3 SoCs is supported but it can be extended later to
other NXP S32 SoCs, hence it's placed in a common directory.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
d2985f118a soc: arm: introduce support for NXP S32K344
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.

Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Benedikt Schmidt
42051fc2d4 dts: arm: st: add STM32L451
Add the MCU STM32L451.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2023-07-06 09:46:14 +00:00
Gerard Marull-Paretas
fcaa259e22 soc: arm: remove all unnecessary NMI_INIT() calls
NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove
the irq lock/unlock pattern as it was likely a cause of copy&paste when
NMI_INIT() was called.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-07-05 09:15:36 +02:00
Sumit Batra
0ae7010946 soc: rt10xx: fix the sequence of Enet2 ref clk enablement
This patch sets ENET2 ref clock to be generated by External OSC

ENET2 ref clock direction as output

ENET2 ref clk frequency to 50MHz

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-07-03 15:24:00 -05:00
Manimaran A
f6eeb9dc84 soc: MEC1701: Removed Microchip MEC1701
Removed MEC1701 SOC specific sources

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-07-01 12:38:07 +02:00
Manuel Argüelles
c651dfbb2b soc: nuvoton_numaker: add guard in defconfg
It must be guarded so the option selection doesn't appear at root level.

Fixes #59876

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-06-30 16:47:51 +02:00
cyliang tw
51d57f612d drivers: pinctrl: add pin group for NuMaker pinctrl
Update Nuvoton numaker series pinctrl, let support pin group.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-28 06:49:38 +00:00
Florian Grandel
b245012ca2 drivers: ieee802154: cc13/26xx_subg: R-to-P link workaround
A known issue exists that does not allow a CC13/26x2R device to
establish a link to a CC13/26x2P device unless the capacitor array is
tuned to a non-default value in the P device.

See SimpleLink(TM) cc13xx_cc26xx SDK 6.20+ Release Notes, Known Issues.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-06-23 09:20:55 +02:00
Florian Grandel
c6c93e394d soc: cc13x2_cc26x2 series: enable RTT support
All Cortex-M processors can support RTT by default. This change enables
RTT support for the cc13xx/cc26xx SoC series (tested in hardware on
CC1352R).

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-06-21 20:02:50 -04:00
Huifeng Zhang
c1ecb8faaa arch: arm: enable FPU and FPU sharing for v8r aarch32
This commit is to enable FPU and FPU_SHARING for v8r aarch32.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
cyliang tw
c448dceb57 drivers: reset: add support for NuMaker series reset
Add Nuvoton numaker series reset controller support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
cyliang tw
4ad399d54d drivers: clock_control: add support for Nuvoton numaker series CLK
Add Nuvoton numaker series clock controller support, including:
1.  Do system clock initialization in z_arm_platform_init().
2.  Support peripheral clock control API equivalent to BSP
    CLK_EnableModuleClock()/CLK_SetModuleClock().

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
cyliang tw
5879810137 drivers: pinctrl: add support for NuMaker series pinctrl
Add Nuvoton numaker series pinctrl support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00