soc: arm: atmel_sam: common: Add PMC API for clock management
Add functions to Atmel SAM SoC PMC API. This is an effort to hide most of the internal registers used in different SAM families. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit is contained in:
Pieter De Gendt
Fabio Baltieri
parent
04de43b1a1
commit
20f1f44120
1 changed files with 485 additions and 0 deletions
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@ -1,5 +1,7 @@
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/*
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* Copyright (c) 2016 Piotr Mienkowski
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* Copyright (c) 2023 Basalte bv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -11,7 +13,11 @@
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#ifndef _ATMEL_SAM_SOC_PMC_H_
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#define _ATMEL_SAM_SOC_PMC_H_
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#include <stdbool.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/types.h>
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#include <soc.h>
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/**
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* @brief Enable the clock of specified peripheral module.
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@ -35,4 +41,483 @@ void soc_pmc_peripheral_disable(uint32_t id);
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*/
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uint32_t soc_pmc_peripheral_is_enabled(uint32_t id);
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#if !defined(CONFIG_SOC_SERIES_SAM4L)
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enum soc_pmc_fast_rc_freq {
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#if defined(CKGR_MOR_MOSCRCF_4_MHz)
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SOC_PMC_FAST_RC_FREQ_4MHZ = CKGR_MOR_MOSCRCF_4_MHz,
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#endif
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#if defined(CKGR_MOR_MOSCRCF_8_MHz)
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SOC_PMC_FAST_RC_FREQ_8MHZ = CKGR_MOR_MOSCRCF_8_MHz,
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#endif
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#if defined(CKGR_MOR_MOSCRCF_12_MHz)
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SOC_PMC_FAST_RC_FREQ_12MHZ = CKGR_MOR_MOSCRCF_12_MHz,
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#endif
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};
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enum soc_pmc_mck_src {
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#if defined(PMC_MCKR_CSS_SLOW_CLK)
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SOC_PMC_MCK_SRC_SLOW_CLK = PMC_MCKR_CSS_SLOW_CLK,
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#endif
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#if defined(PMC_MCKR_CSS_MAIN_CLK)
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SOC_PMC_MCK_SRC_MAIN_CLK = PMC_MCKR_CSS_MAIN_CLK,
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#endif
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#if defined(PMC_MCKR_CSS_PLLA_CLK)
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SOC_PMC_MCK_SRC_PLLA_CLK = PMC_MCKR_CSS_PLLA_CLK,
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#endif
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#if defined(PMC_MCKR_CSS_PLLB_CLK)
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SOC_PMC_MCK_SRC_PLLB_CLK = PMC_MCKR_CSS_PLLB_CLK,
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#endif
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#if defined(PMC_MCKR_CSS_UPLL_CLK)
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SOC_PMC_MCK_SRC_UPLL_CLK = PMC_MCKR_CSS_UPLL_CLK,
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#endif
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};
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/**
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* @brief Set the prescaler of the Master clock.
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*
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* @param prescaler the prescaler value.
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*/
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static ALWAYS_INLINE void soc_pmc_mck_set_prescaler(uint32_t prescaler)
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{
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uint32_t reg_val;
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switch (prescaler) {
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case 1:
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reg_val = PMC_MCKR_PRES_CLK_1;
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break;
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case 2:
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reg_val = PMC_MCKR_PRES_CLK_2;
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break;
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case 4:
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reg_val = PMC_MCKR_PRES_CLK_4;
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break;
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case 8:
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reg_val = PMC_MCKR_PRES_CLK_8;
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break;
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case 16:
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reg_val = PMC_MCKR_PRES_CLK_16;
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break;
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case 32:
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reg_val = PMC_MCKR_PRES_CLK_32;
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break;
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case 64:
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reg_val = PMC_MCKR_PRES_CLK_64;
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break;
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case 3:
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reg_val = PMC_MCKR_PRES_CLK_3;
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break;
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default:
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__ASSERT(false, "Invalid MCK prescaler");
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reg_val = PMC_MCKR_PRES_CLK_1;
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break;
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}
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PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | reg_val;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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}
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}
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#if defined(CONFIG_SOC_SERIES_SAME70) || defined(CONFIG_SOC_SERIES_SAMV71)
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/**
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* @brief Set the divider of the Master clock.
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*
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* @param divider the divider value.
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*/
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static ALWAYS_INLINE void soc_pmc_mck_set_divider(uint32_t divider)
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{
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uint32_t reg_val;
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switch (divider) {
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case 1:
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reg_val = PMC_MCKR_MDIV_EQ_PCK;
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break;
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case 2:
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reg_val = PMC_MCKR_MDIV_PCK_DIV2;
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break;
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case 3:
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reg_val = PMC_MCKR_MDIV_PCK_DIV3;
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break;
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case 4:
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reg_val = PMC_MCKR_MDIV_PCK_DIV4;
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break;
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default:
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__ASSERT(false, "Invalid MCK divider");
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reg_val = PMC_MCKR_MDIV_EQ_PCK;
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break;
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}
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PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | reg_val;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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}
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}
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#endif /* CONFIG_SOC_SERIES_SAME70 || CONFIG_SOC_SERIES_SAMV71 */
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/**
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* @brief Set the source of the Master clock.
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*
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* @param source the source identifier.
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*/
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static ALWAYS_INLINE void soc_pmc_mck_set_source(enum soc_pmc_mck_src source)
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{
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PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | (uint32_t)source;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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}
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}
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/**
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* @brief Switch main clock source selection to internal fast RC.
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*
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* @param freq the internal fast RC desired frequency 4/8/12MHz.
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*/
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static ALWAYS_INLINE void soc_pmc_switch_mainck_to_fastrc(enum soc_pmc_fast_rc_freq freq)
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{
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/* Enable Fast RC oscillator but DO NOT switch to RC now */
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PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN;
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/* Wait for the Fast RC to stabilize */
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
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}
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/* Change Fast RC oscillator frequency */
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk)
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| CKGR_MOR_KEY_PASSWD
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| (uint32_t)freq;
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/* Wait for the Fast RC to stabilize */
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
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}
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/* Switch to Fast RC */
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL)
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| CKGR_MOR_KEY_PASSWD;
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}
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/**
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* @brief Enable internal fast RC oscillator.
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*
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* @param freq the internal fast RC desired frequency 4/8/12MHz.
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*/
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static ALWAYS_INLINE void soc_pmc_osc_enable_fastrc(enum soc_pmc_fast_rc_freq freq)
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{
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/* Enable Fast RC oscillator but DO NOT switch to RC */
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PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN;
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/* Wait for the Fast RC to stabilize */
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
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}
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/* Change Fast RC oscillator frequency */
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk)
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| CKGR_MOR_KEY_PASSWD
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| (uint32_t)freq;
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/* Wait for the Fast RC to stabilize */
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
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}
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}
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/**
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* @brief Disable internal fast RC oscillator.
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*/
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static ALWAYS_INLINE void soc_pmc_osc_disable_fastrc(void)
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{
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/* Disable Fast RC oscillator */
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & ~CKGR_MOR_MOSCRCF_Msk)
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| CKGR_MOR_KEY_PASSWD;
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}
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/**
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* @brief Check if the internal fast RC is ready.
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*
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* @return true if internal fast RC is ready, false otherwise
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*/
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static ALWAYS_INLINE bool soc_pmc_osc_is_ready_fastrc(void)
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{
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return (PMC->PMC_SR & PMC_SR_MOSCRCS);
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}
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/**
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* @brief Enable the external crystal oscillator.
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*
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* @param xtal_startup_time crystal start-up time, in number of slow clocks.
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*/
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static ALWAYS_INLINE void soc_pmc_osc_enable_main_xtal(uint32_t xtal_startup_time)
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{
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uint32_t mor = PMC->CKGR_MOR;
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mor &= ~(CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCXTEN);
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mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(xtal_startup_time);
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PMC->CKGR_MOR = mor;
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/* Wait the main Xtal to stabilize */
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
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}
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}
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/**
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* @brief Bypass the external crystal oscillator.
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*/
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static ALWAYS_INLINE void soc_pmc_osc_bypass_main_xtal(void)
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{
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uint32_t mor = PMC->CKGR_MOR;
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mor &= ~(CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCXTEN);
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mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
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/* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
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PMC->CKGR_MOR = mor;
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/* The MOSCXTS in PMC_SR is automatically set */
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}
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/**
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* @brief Disable the external crystal oscillator.
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*/
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static ALWAYS_INLINE void soc_pmc_osc_disable_main_xtal(void)
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{
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uint32_t mor = PMC->CKGR_MOR;
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mor &= ~(CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCXTEN);
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
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}
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/**
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* @brief Check if the external crystal oscillator is bypassed.
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*
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* @return true if external crystal oscillator is bypassed, false otherwise
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*/
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static ALWAYS_INLINE bool soc_pmc_osc_is_bypassed_main_xtal(void)
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{
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return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
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}
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/**
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* @brief Check if the external crystal oscillator is ready.
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*
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* @return true if external crystal oscillator is ready, false otherwise
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*/
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static ALWAYS_INLINE bool soc_pmc_osc_is_ready_main_xtal(void)
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{
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return (PMC->PMC_SR & PMC_SR_MOSCXTS);
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}
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/**
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* @brief Switch main clock source selection to external crystal oscillator.
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*
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* @param bypass select bypass or xtal
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* @param xtal_startup_time crystal start-up time, in number of slow clocks
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*/
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static ALWAYS_INLINE void soc_pmc_switch_mainck_to_xtal(bool bypass, uint32_t xtal_startup_time)
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{
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soc_pmc_osc_enable_main_xtal(xtal_startup_time);
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/* Enable Main Xtal oscillator */
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if (bypass) {
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN)
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| CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCXTBY
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| CKGR_MOR_MOSCSEL;
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} else {
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY)
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| CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCXTEN
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| CKGR_MOR_MOSCXTST(xtal_startup_time);
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/* Wait for the Xtal to stabilize */
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
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}
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PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
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}
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}
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/**
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* @brief Disable the external crystal oscillator.
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*
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* @param bypass select bypass or xtal
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*/
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static ALWAYS_INLINE void soc_pmc_osc_disable_xtal(bool bypass)
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{
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/* Disable xtal oscillator */
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if (bypass) {
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY)
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| CKGR_MOR_KEY_PASSWD;
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} else {
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN)
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| CKGR_MOR_KEY_PASSWD;
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}
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}
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/**
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* @brief Check if the main clock is ready. Depending on MOSCEL, main clock can be one
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* of external crystal, bypass or internal RC.
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*
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* @return true if main clock is ready, false otherwise
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*/
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static ALWAYS_INLINE bool soc_pmc_osc_is_ready_mainck(void)
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{
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return PMC->PMC_SR & PMC_SR_MOSCSELS;
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}
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/**
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* @brief Enable Wait Mode.
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*/
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static ALWAYS_INLINE void soc_pmc_enable_waitmode(void)
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{
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PMC->PMC_FSMR |= PMC_FSMR_LPM;
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}
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/**
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* @brief Enable Clock Failure Detector.
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*/
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static ALWAYS_INLINE void soc_pmc_enable_clock_failure_detector(void)
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{
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uint32_t mor = PMC->CKGR_MOR;
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | mor;
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}
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/**
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* @brief Disable Clock Failure Detector.
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*/
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static ALWAYS_INLINE void soc_pmc_disable_clock_failure_detector(void)
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{
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uint32_t mor = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
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}
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#if defined(PMC_MCKR_CSS_PLLA_CLK)
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/**
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* @brief Disable the PLLA clock.
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*/
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static ALWAYS_INLINE void soc_pmc_disable_pllack(void)
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{
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
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}
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/**
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* @brief Enable the PLLA clock.
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*
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* @param mula PLLA multiplier
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* @param pllacount PLLA lock counter, in number of slow clocks
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* @param diva PLLA Divider
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*/
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static ALWAYS_INLINE void soc_pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
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{
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__ASSERT(diva > 0, "Invalid PLLA divider");
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/* first disable the PLL to unlock the lock */
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soc_pmc_disable_pllack();
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
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| CKGR_PLLAR_DIVA(diva)
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| CKGR_PLLAR_PLLACOUNT(pllacount)
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| CKGR_PLLAR_MULA(mula);
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while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0) {
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}
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}
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/**
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* @brief Check if the PLLA is locked.
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*
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* @return true if PLLA is locked, false otherwise
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*/
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static ALWAYS_INLINE bool soc_pmc_is_locked_pllack(void)
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{
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return (PMC->PMC_SR & PMC_SR_LOCKA);
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}
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#endif /* PMC_MCKR_CSS_PLLA_CLK */
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#if defined(PMC_MCKR_CSS_PLLB_CLK)
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/**
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* @brief Disable the PLLB clock.
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*/
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static ALWAYS_INLINE void soc_pmc_disable_pllbck(void)
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{
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PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
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}
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/**
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* @brief Enable the PLLB clock.
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*
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* @param mulb PLLB multiplier
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* @param pllbcount PLLB lock counter, in number of slow clocks
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* @param divb PLLB Divider
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*/
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static ALWAYS_INLINE void soc_pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
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{
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__ASSERT(divb > 0, "Invalid PLLB divider");
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/* first disable the PLL to unlock the lock */
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soc_pmc_disable_pllbck();
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PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(divb)
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| CKGR_PLLBR_PLLBCOUNT(pllbcount)
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| CKGR_PLLBR_MULB(mulb);
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||||
while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the PLLB is locked.
|
||||
*
|
||||
* @return true if PLLB is locked, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_is_locked_pllbck(void)
|
||||
{
|
||||
return (PMC->PMC_SR & PMC_SR_LOCKB);
|
||||
}
|
||||
|
||||
#endif /* PMC_MCKR_CSS_PLLB_CLK */
|
||||
|
||||
#if defined(PMC_MCKR_CSS_UPLL_CLK)
|
||||
|
||||
/**
|
||||
* @brief Enable the UPLL clock.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_enable_upllck(uint32_t upllcount)
|
||||
{
|
||||
PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(upllcount)
|
||||
| CKGR_UCKR_UPLLEN;
|
||||
|
||||
/* Wait UTMI PLL Lock Status */
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKU)) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the UPLL clock.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_disable_upllck(void)
|
||||
{
|
||||
PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the UPLL is locked.
|
||||
*
|
||||
* @return true if UPLL is locked, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_is_locked_upllck(void)
|
||||
{
|
||||
return (PMC->PMC_SR & PMC_SR_LOCKU);
|
||||
}
|
||||
|
||||
#endif /* PMC_MCKR_CSS_UPLL_CLK */
|
||||
|
||||
#endif /* !CONFIG_SOC_SERIES_SAM4L */
|
||||
|
||||
#endif /* _ATMEL_SAM_SOC_PMC_H_ */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue