Commit graph

2576 commits

Author SHA1 Message Date
Manuel Argüelles
673f38f3d1 soc: arm: nxp_s32: s32k1: unselect CPU_HAS_xCACHE
Following changes in #64978, align CPU_HAS_xCACHE symbols with
the CMSIS feature definitions in the device headers so that
both have the same value.

Fixes #66147

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-12-05 13:18:23 +01:00
Wilfried Chauveau
af3a19106a soc: arm: fix missing configs & defines
Some SoC have missing feature selections in their Kconfig.
Some others are missing includes of CMSIS-Core headers.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-05 10:19:15 +00:00
Wilfried Chauveau
29ffaaa0b6 arch: arm: cortex_m: Remove CPU_HAS_*CACHE from CPU_CORTEX_M7
Caches are optional on cortex-m7, having CPU_HAS_*CACHE in CPU_CORTEX_M7
definition renders them mandatory.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-05 10:19:15 +00:00
Wilfried Chauveau
7226f985fc soc: arm: nxp_kinetis: remove unecessary includes
This changes remove extraneous includes causing issues with cycles in
includes subsequently having code requiring definitions from CMSIS
while it’s configuration hasn’t completed yet.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-05 10:19:15 +00:00
Wilfried Chauveau
8d91ba200f modules: cmsis: Move cortex_m default configuration to its own file
Kconfig parameters, header’s default & silicon vendor’s SDK configuration
for CMSIS Core, must be consistent. Depending on the inclusion order of
the headers, this is currently not always the case.

This change introduces consistency checks & enusers defaults match their
Kconfig settings.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-05 10:19:15 +00:00
Wilfried Chauveau
a00aa3bcfa arch: arm: cortex_m: add config for PMU
This adds kconfig entries for Performance Monitoring Unit (PMU).

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-05 10:19:15 +00:00
Manuel Argüelles
91293187d8 soc: nxp_s32: introduce support for S32K1 devices
Introduce support for NXP S32K1 family of 32-bit MCUs, and
particularly for S32K146 devices. S32K1 share a fair amount of
similarities with Kinetis family, so most of the peripheral drivers
can be reused.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-30 11:21:59 -05:00
Jamie McCrae
93f537552d soc: arm: nordic_nrf: Remove deprecated GPREGRET Kconfig option
Removes the Kconfig NRF_STORE_REBOOT_TYPE_GPREGRET which was
deprecated in zephyr 3.4

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-11-29 13:38:29 +01:00
Adam Wojasinski
38739368dd modules: hal_nordic: watchdog: Add Kconfig symbols for new WDT instances
This commit is a part of introduction of new WTD instances.
It adds new Kconfig symbols that can be used in WDT shim and
nrfx driver.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-11-29 13:12:42 +01:00
Declan Snyder
c8375659fb soc: nxp: rt10xx: Increase workqueue size for enet
Increase the size of the system workqueue stack if using
nxp ethernet driver

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-28 14:34:02 -06:00
Declan Snyder
0e935ea180 soc: rt10xx: enable phy clock with new driver
when using either old or new driver for nxp enet,
enable the phy clock

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-28 14:34:02 -06:00
Marek Pieta
00d8263a93 soc: arm: nrf52: Configurable EGU instance for anomaly 109 workaround
Change makes EGU instance used for anomaly 109 workaround configurable.
The default EGU instance (5) may be used for other purpose.

Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
2023-11-28 14:23:49 +00:00
Jun Lin
91fdef0783 soc: npcx: add support for npcx9mfp
Add new SoC npcx9mfp support for npcx9 series.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-11-28 09:13:23 +00:00
Dat Nguyen Duy
513ba04168 soc: nxp_s32: cmsis rtos v2 adaptation
There are symbols are both defined by the NXP S32 HAL and
the CMSIS RTOS V2 wrapper, to avoid interference between
them, redefine the symbols under an enum.

Also this is may a common issue for all NXP S32 platforms,
move to common place to be reused

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2023-11-27 19:58:57 +01:00
Aymeric Aillet
f2061a073a soc: arm: reneas: Add r8a779f0 support
r8a779f0 SoC is part of the Renesas R-Car Gen4 SoC series.

This SoC has a dual core lockstep Cortex-R52 CPU.

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2023-11-25 08:50:47 -05:00
Aymeric Aillet
6033db5360 drivers: pinctrl: rcar: Add r8a779f0 support
Enable PFC controller for r8a779f0 SoC.
Declare pin list for r8a779f0 SoC.

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2023-11-25 08:50:47 -05:00
Aymeric Aillet
1738543c5d drivers: pinctrl: Add R-Car Gen4 support
Renesas R-Car Gen4 is different from Gen3 regarding pinmux.

While Gen3 had only one base address to manage all pins,
Gen4 has one set of pinmux registers per GPIO banks.

We could expose one pinmux register per GPIO controllers,
but that would break potential compatibility with Linux
Device tree.

Instead create a reg_base array to parse all reg base from
device tree and identify proper base address based on the pin
definition.

This imply to add a pfc_base parameter to most of the pfc_rcar
function.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2023-11-25 08:50:47 -05:00
Jun Lin
3f9d24e4c0 mgmt: ec_host_cmd: shi_npcx: support the enhanced mode
The original SHI module only has one output FIFO buffer. It costs a lot
when the driver has to send/change the protocol control code because it
must fill out all 128 bytes of output FIFO. In npcx4, we introduce
another output buffer in 1-byte depth. These two buffers can switch back
and forth during the transaction. We can use the single-byte buffer
to send the control code and the 128-byte FIFO to send the data payload.
It helps improve the SHI driver's efficiency.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-11-24 11:45:13 +01:00
Jun Lin
74f07b04ff soc: npcx: shi: add new registers for npcx4
Add the SHI enhanced buffer mode register definition for npcx4.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-11-24 11:45:13 +01:00
Martin Gritzan
86cf5829a4 dts: arm: stm32: add stm32f303xb bindings
The STM32F303xB is very similar to the xC, the only difference being the
RAM and flash sizes.

Signed-off-by: Martin Gritzan <martin.gritzan@gmail.com>
2023-11-24 09:24:14 +01:00
Peter van der Perk
5edb7cbe41 soc: arm: nxp_imx: rt11xx: add support for CONFIG_ETH_MCUX_RMII_EXT_CLK
ENET_REF_CLK as an input during rt11xx clock initialization.

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2023-11-22 14:56:38 +00:00
Dawid Niedzwiecki
43ef398614 pm: add power management for stm32f4x
Add soc power management for the STM32F4x chips.

One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.

The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.

The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-21 08:46:17 +00:00
Abderrahmane Jarmouni
f8a9d95549 soc: arm: st_stm32: stm32u5: Add STM32U5A9 support
Add support for STM32U5A9XX SoC series

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2023-11-21 08:44:34 +00:00
Franciszek Zdobylak
6f91fd858c dts: arm: silabs: Configure hfxo in dtsi
This commit moves configuration of hfxo from headers defined on board level
to device trees of SoCs.

Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
2023-11-20 13:01:39 +01:00
Adam Wojasinski
4f1823c616 soc: arm: nordic_nrf: Add Kconfig symbol for new I2S instance
Add I2S 20 instance

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-11-20 09:24:05 +01:00
Natalia Pluta
d7d11ef09f soc: arm: nordic_nrf: Add Kconfig symbols for QDEC instances
Add QDEC instances 20, 21, 130, 131

Signed-off-by: Natalia Pluta <natalia.pluta@nordicsemi.no>
2023-11-20 09:19:45 +01:00
Manuel Argüelles
2c9255fbba soc: nxp_s32: include soc.h instead of individual headers
The SoC header already includes the necessary device headers for
all SoC variants supported.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-16 17:53:43 +01:00
Manuel Argüelles
927445325c soc: nxp_s32: s32ze: include device headers in soc.h
To simplify the inclusion of device headers in common code for
NXP S32 devices, make sure all SoCs are including their respective
device headers. This PR adds the missing headers for S32Z/E.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-16 17:53:43 +01:00
Cong Nguyen Huu
8dcd61e36e soc: nxp_s32: pinctrl: update to RTD 1.0.0
Add alias "FEATURE_SIUL2_MAX_NUMBER_OF_INPUT"
for compatibility with with previous RTD versions.

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
2023-11-16 09:28:16 +01:00
Mulin Chao
76b0aab6cc soc: arm: npcx: fix clock reference of APB4/FIU1 buses
This CL fixes the clock reference of APB4/FIU1 buses by introducing new
Kconfig options.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-11-16 06:50:57 +00:00
Manuel Argüelles
1a05cfc03a soc: nxp_s32: consolidate part number options
Currently, the NXP S32 SoCs have three redundant Kconfig hidden
options to define the part number. To streamline this, we will
retain `CONFIG_SOC_PART_NUMBER` to store the part number as a
string and `CONFIG_SOC_PART_NUMBER_<part>` that can be selected
by the boards.

Furthermore, for drivers requiring conditional code compilation
based on the target SoC, they should utilize the series or SoC
config option as applicable, instead of the part number config.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-15 10:25:43 -06:00
Manuel Argüelles
8ca4f5b4a1 soc: nxp_s32: s32k3: drop M7 suffix from options
The existing S32K3 Kconfig options employ the `M7` suffix, which is
redundant given that all cores in this series utilize an Arm Cortex-M7
core. Therefore, we should remove it.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-15 10:25:43 -06:00
Manuel Argüelles
589f3f435b soc: nxp_s32: rename s32k to s32k3 for series alignment
To accommodate support for S32K1 devices, it is necessary to rename
the existing `s32k` directory, which currently houses support for
the S32K3 series, to align with the respective series names. This
adjustment is necessary given the distinct differences in core
architecture, MPU, peripherals, and other key aspects between
the two series.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-15 10:25:43 -06:00
Sebastian Bøe
6348a973c3 soc: arm: Remove CPU_HAS_NRF_IDAU's dependencies
CPU_HAS_NRF_IDAU is depending on SOC_SERIES_NRF91X and
SOC_NRF5340_CPUAPP.

This makes it more difficult to have an out-of-tree nrf SOC.

It is also an unnecessary dependency. There is no prompt for
CPU_HAS_NRF_IDAU, so it will not show up in menuconfig and it won't be
possible to enable it from a users Kconfig fragment.

The only way to enable it is to select it, and those that select this
option can themselves make sure that they only do so when appropriate.

Also, move NRF_SPU options out to SOC Kconfig files to also make
out-of-tree SoCs possible. With the added benefit of not polluting the
common soc/arm/Kconfig.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2023-11-15 12:15:49 +01:00
Wojciech Sipak
9e44f59e9a drivers: pinctrl: add RZT2M driver
This adds a new driver for Renesas RZ/T2M.
The driver allows configuration of pin direction,
pull up/down resistors, drive strength and slew rate,
and selection of function for a pin.

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-11-15 11:41:35 +01:00
Wojciech Sipak
b1c83c0335 soc: Add support for RZ/T2M
This adds a new SoC: SOC_RENESAS_RZT2M
and a new board: rzt2m_startek_kit

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>
2023-11-15 11:41:35 +01:00
Jamie McCrae
b4ce96d161 soc: arm: nordic_nrf: Imply XIP instead of select
This allows XIP to be disabled for applications that execute in
RAM, which do not need XIP support from flash

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-11-15 10:03:24 +01:00
Charles Dias
63ceeb3bba soc: arm: st_stm32: add support for stm32h7b0xx and stm32h7b0xxQ
Add Kconfig SoC configurations.

Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
2023-11-15 10:02:06 +01:00
Daniel DeGrasse
5854821b65 drivers: mipi_dsi: add support for mipi_dsi_detach to dsi_mcux_2l
Add support for mipi_dsi_detach API to dsi_mcux_2l driver, and
update RT5xx SOC interface to enable halting clocks for the MIPI DPHY.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-14 09:22:59 +01:00
Manuel Argüelles
434a40470c drivers: mbox: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-13 12:18:34 -05:00
Manuel Argüelles
b3f950c648 drivers: mdio: nxp_s32_netc: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-13 09:49:26 +01:00
Declan Snyder
2d1fdb5586 soc: nxp: rt1xxx: Enable NXP FlexRAM
Enable NXP FlexRAM in DTS and SOC code.

Do not configure flexram at runtime if the code is in the RAM.

Fix RT1060 DT to be more accurate.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-13 09:42:28 +01:00
Daniel Schultz
a2f971795f soc: arm: ti_k3: am62x_m4: Lower Initialization level for init
Other drivers like the pinctrl_ti_k3 rely on a fully initialized system.
Move the am62x_init to an earlier stage than PRE_KERNEL_1 to keep both
PRE_KERNEL_{1,2} free for drivers.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2023-11-13 09:42:11 +01:00
Jason Kridner
26f30db8ad soc: arm: ti_simplelink: cc13x2x7_cc26x2x7: add caparray delta config
- Make caparray delta a Kconfig variable
- Set caparray delta for beagle_bcf at beagleconnect_freedom_defconfig

Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
2023-11-11 18:49:25 -05:00
Declan Snyder
fef0018cca soc: lpc55xxx: Support, enable, test NXP MRT
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-10 10:40:54 +01:00
Declan Snyder
93c59793c2 soc: rt6xx: Add NXP MRT
Add NXP MRT to RT6xx DT definition and add peripheral reset to soc.c

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-10 10:40:54 +01:00
Declan Snyder
ff83745c9a soc: rt5xx: Enable NXP MRT
Enable NXP MRT on RT5xx soc and MIMXRT595_EVK board

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-10 10:40:54 +01:00
Manuel Argüelles
595a9c11c8 counter: nxp_s32_sys_timer: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-09 18:21:19 +01:00
Declan Snyder
345f079e49 dts: bindings: Fix NXP USB bindings
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-09 15:34:39 +01:00
Mulin Chao
f9a4a3597b soc: arm: npcx: move soc-specific register definitions to soc.h
This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we
introduce a new chip series. Most of them are relevant to register
layouts in different npcx soc series. It moves soc-specific register
definitions from `reg_def.h` to its own soc.h file.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-11-09 10:20:39 +00:00
Manuel Argüelles
6744d6084d watchdog: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-09 10:20:27 +00:00
Manuel Argüelles
bda3b101d3 serial: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-08 10:06:46 +01:00
Dmitrii Golovanov
82ec6394a1 soc: arm: Fix cmake linker.ld warning for arduino_uno_r4_minima
Fix cmake depreciation warning on pre-defined linker.id
(soc/arm/renesas_ra/ra4m1/linker.ld) used for arduino_uno_r4_minima.

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
2023-11-07 09:53:57 +01:00
Daniel DeGrasse
883f604f12 soc: arm: nxp_imx: rt11xx: allow user to disable CONFIG_ADJUST_DCDC
Allow user to disable CONFIG_ADJUST_DCDC for their board, rather than
selecting it at the SOC level. The symbol still defaults to enabled,
preserving existing behavior unless a user explicitly chooses to disable
it.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-07 09:48:35 +01:00
Manuel Argüelles
237ec65ad3 intc: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.

Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-11-06 19:02:56 -05:00
Huifeng Zhang
abde709b5e arch: arm: cortex_a_r: introduce USE_SWITCH
This commit introduce 'USE_SWITCH' feature into cortex-A/R(aarch32)
architecture

For introducing USE_SWITCH, the exception entry and exit are unified via
`z_arm_cortex_ar_enter_exc` and `z_arm_cortex_ar_exit_exc`. All
exceptions including ISR are using this way to enter and exit exception
handler.

Differentiate exception depth and interrupt depth. Allow doing
context switch when exception depth greater than 1 but not allow doing
this when interrupt depth greater than 1.

Currently, USE_SWITCH doesn't support FPU_SHARING and USERSPACE.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-11-06 15:32:01 -06:00
Gerson Fernando Budke
3ed1c990dc soc: st: l010xb: Fix the number of IRQs
Change the NUM_IRQS value from 32 to 30 following the rm0451.

Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2023-11-06 10:14:10 +01:00
Gerson Fernando Budke
6e3bae727b soc: st: Add all missing stm32l010 SoCs
Add minimal SoC entries to enable the whole stm32l010 family.

Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2023-11-06 10:14:10 +01:00
Caspar Friedrich
8242ef0a37 soc: arm: st_stm32: stm32l0: Add support for STM32L081
Add support for the STM32L081xx soc series.

Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
2023-11-06 10:11:40 +01:00
Declan Snyder
4d654250a5 soc: lpc55xxx: Fix system hw clock cycle rate
Commit c6e3bac4f changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-06 10:11:25 +01:00
Grzegorz Swiderski
e4448ed498 soc: mimx8mm6_m4: Restore linker script
For this SoC, an additional section is conditionally included on top of
the default linker script for Cortex-M. Set `SOC_LINKER_SCRIPT` to the
local `linker.ld`.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2023-11-06 10:10:55 +01:00
Daniel DeGrasse
29ab2b13f6 drivers: ipm: Remove CONFIG_IPM_IMX_REV2
Remove CONFIG_IPM_IMX_REV2, as this Kconfig is no longer needed. The
driver can now be enabled with CONFIG_IPM_IMX.

Update NXP HAL to remove this Kconfig as well.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-06 10:09:59 +01:00
Daniel DeGrasse
8d5322b8ff drivers: ipm: remove nxp,imx-mu-rev2 compatible
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible

Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-11-06 10:09:59 +01:00
Torsten Rasmussen
4812884f84 cmake: arm: update arm SoC to use SOC_LINKER_SCRIPT variable
This commit updates all arm SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-03 11:01:23 +01:00
Torsten Rasmussen
3e82eb976e soc: move arm cortex_m common mpu code to arch/arm/core/mpu
Locate common mpu code together with other arm / nxp mpu code in the
arch folder where it logically belongs.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-02 09:45:18 +01:00
TOKITA Hiroshi
a9e49918cf drivers: interrupt_controller: Add icu driver for Renesas RA series
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
04b723e900 drivers: pinctrl: Add pinctrl driver for Renesas RA series
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
1741b3a356 drivers: clock_control: Add clock driver for Renesas RA series
Add initial support for Renesas RA clock generation circuit.

It returns a fixed value to simplify the first commit to get the UART
working now.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
TOKITA Hiroshi
5ccc0eb319 soc: arm: add support for Renesas RA4M1 series SoC
Add essential support for RA4M1 Series.
It only defines `r7fa4m1ab3cfm` currently.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2023-11-01 10:56:46 +00:00
Andriy Gelman
d0961756a6 drivers: watchdog: Add xmc4xxx support
Adds watchdog support for Infineon xmc4xxx MCUs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-10-27 12:58:07 -05:00
Mike J. Chen
ca19b40733 soc: arm: nxp_imx: rt5xx: make some clock init functions weak
Allows a board to provide their own functions if
they wish to init clocks differently.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2023-10-27 10:51:28 +02:00
Anas Nashif
51f6c4269b soc: microchip_mec: do not enable PM in soc
PM should not be enabled by default at the soc level. This is an
application decision and not a platform decision whether to enable or
disable PM features.

Enabling PM by default will result in descripencies and test scope and
failures in tests that do not account for PM being enabled.

Fixes #60359

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-10-26 12:28:18 -05:00
Erwan Gouriou
54fa6f30b8 soc: stm32: Enable Debug in stop mode when ZTEST is used
Force STM32_ENABLE_DEBUG_SLEEP_STOP option when running tests.
This option enables Debug in Sleep/stop states and disables it when
disabled (default state).

When disabled, it may be impossible to flash the device with runner
such as openocd. It's generally working using cubeprogrammer, but it might
fail as well with fault configuration.

Instead of fixing each test or breaking CI each time a new test is created
with CONFIG_PM=y, force this option to be enabled when ZTEST=y (as it was
already the case when DEBUG=y).

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-10-26 09:49:42 +02:00
Manuel Argüelles
a7bda08960 nxp: s32ze: take exceptions in Arm mode
Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM
code for Armv-8 Aarch32 is written for Arm mode only. This Soc
has a general purpose register that can set the core TEINIT signal
to change the mode exceptions are taken before booting up the core.
The debugger startup scripts or firmware booting up the core may
configure this bit to Thumb mode, as is the case of the NXP S32 debug
probe startup scripts for S32ZE.

Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value
is ignored and exceptions are always taken into Arm mode, compatible
with current Zephyr ASM code. At least until taking execeptions in Thumb
mode is supported in Zephyr.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-10-25 18:14:51 -07:00
Bjarki Arge Andreasen
9b21d4d366 soc: sam: Add poweroff implementation
This commit adds an implementation of poweroff, which first
uses SUPC to enable all defined wakeup sources (except for
sam4l), followed by entering backup mode.

Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
2023-10-24 11:35:43 +02:00
Bjarki Arge Andreasen
312c8b1930 soc: sam: Add SUPC driver and dts model
This commit adds a driver and dts model for the ATMEL SAM
SUPC component.

Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
2023-10-24 11:35:43 +02:00
Nikodem Kastelik
a4cbe9e9c6 soc: arm: nordic_nrf: align nrf_power calls to new scheme
Now the API to manage GPREGRET register is unified for all devices
having one or more GPREGRET entries.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2023-10-24 11:13:53 +02:00
Nikodem Kastelik
f3f2c113d1 soc: arm: nordic_nrf: nrf53: align nrf_regulators calls to new scheme
Now more generic regulators API is available.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2023-10-24 11:13:53 +02:00
Joakim Andersson
17fd1f8fba boards: Enable TF-M by default for nordic SoC NS boards
Enable TF-M by default for nordic nRF5340 and nrf9160 SoC boards.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2023-10-24 09:40:16 +02:00
Joakim Andersson
33a44d0ed8 tfm: nordic_nrf: Add generic SoC support for nordic SoCs
Add generic SoC support for the supported nordic SoCs:
- nrf5340
- nrf9160
- nrf9120

Add generic SoC support by taking board specific configurations from
zephyr devicetree and kconfig.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2023-10-24 09:40:16 +02:00
Alberto Escolar Piedras
9834fabe2d nrf53: Correct sync_rtc kconfig dependencies for simulation
Let's make the sync_rtc kconfig depend on the SOC_COMPATIBLE
options which are set both by the real and simulated targets,
so this code works in the same way for both.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-10-20 15:20:09 +02:00
Alberto Escolar Piedras
32d0c8d8e5 nrf53: Refactor sync RTC options to their own file
So they can be reused by the simulated board

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-10-20 15:20:09 +02:00
Jun Lin
e5e599c100 soc: npcx: add HAS_PM to npcx4
The Kconfig option HAS_PM, which must be needed for SoCs providing PM
hooks, is missing in npcx4.
This commit adds it to soc/arm/nuvoton_npcx/npcx4/Kconfig.series.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-10-20 15:11:14 +02:00
Adam Wojasinski
5685af0923 modules: hal_nordic: Add support for new TWIM instances
Add Kconfig and symbols for twim: 20-22, 30, 121, 130-137 instances

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-10-20 15:04:10 +02:00
Adam Wojasinski
5c1daef5ab drivers: spi: nrfx: Add SPIM Kconfig symbols for new instances
Add support for upcomming SPIM instances.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-10-20 15:03:17 +02:00
Niek Ilmer
9e6b1d5ba6 SOC: Smartbond: Add DA14695
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.

Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
2023-10-20 14:51:49 +02:00
Nazar Palamar
4d76e26f17 drivers: pinctrl: Update Infineon CAT1 pinctrl driver
- if we have input enable use CY_GPIO_DM_xxxx else
CY_GPIO_DM_xxx_IN_OFF;

- added bias_high_impedance option

- Updated HIGHZ drive mode, now it sets if:
--- we have bias_high_impedance
--- or if input_enable and no addition bias mode

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2023-10-12 15:17:35 +03:00
Andrzej Kuros
adec56bcee nrf5340: pretick decoupled from workaround anomaly 160
Coupling in code between workarounds for anomaly 160 and anomaly 165
(pretick) is decreased.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-10-11 11:09:29 +02:00
Andrzej Kuros
3eef769209 nrf53: fix RTC pretick for RTC rescheduling by other interrupts
It might happen that while some interrupt handler other than for RTC0
or RTC1 (e.g. for RADIO) is executed, the scheduled pretick CC triggers.
This starts pretick pulses due to the loop through IPC. The change
in pretick schedule did not stop the pretick pulses going through IPC
loop, what caused heavy increase in power consumption.

This commit fixes this behavior.
Added also clarifications for Kconfig option `SOC_NRF53_RTC_PRETICK`.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-10-11 11:09:29 +02:00
Andrzej Kuros
c4e53dabf7 nrf53: fix RTC pretick power usage for events on RTC0
For RTC0 events the RTC1 pretick event was not cleared what caused the
WDT to be not stopped. This resulted in increased power usage.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-10-11 11:09:29 +02:00
Flavio Ceolin
e7bd10ae71 random: Rename random header
rand32.h does not make much sense, since the random subsystem
provides more APIs than just getting a random 32 bits value.

Rename it to random.h and get consistently with other
subsystems.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-10-10 14:23:50 +03:00
Daniel DeGrasse
faf5593272 soc: arm: nxp_lpc: Only clock core from PLL1 when CONFIG_FLASH=n
Do not clock the LPC55xxx cores from PLL1 when CONFIG_FLASH is set. This
is required due to the following limitation of the flash controller
(documented in the reference manual):

Flash operations (erase, blank check, program) and reading a single word
can only be performed for CPU frequencies of up to 100 MHz. These
operations cannot be performed for frequencies above 100 MHz.

The PLL1 clock source will result in a core clock of 150MHz, which
violates this requirement.

Fixes #62963

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-10-08 11:25:02 +01:00
Yonatan Schachter
c461441cc5 soc: silabs: Added Kconfig to indicate the existence of a radio PHY
Added SOC_GECKO_HAS_RADIO symbol, to indicate that a SoC has a radio
phy, so that radio related code would only apply to devices with radio.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2023-10-04 10:30:00 +03:00
Andrzej Kuros
d44e96e486 nrf53: pretick with NRF_802154_RADIO_DRIVER
The `SOC_NRF53_RTC_PRETICK` option is now allowed to be used with
`NRF_802154_RADIO_DRIVER`.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Andrzej Kuros
e03d5d4c6d nrf53: RTC pretick allows user channels and require just one CC
The nrf53 pretick can be used with non-zero
`NRF_RTC_TIMER_USER_CHAN_COUNT` Kconfig option.

The nrf53 pretick requires just one RTC1 CC channel.

The nrf53 pretick handles also RTC1 and RTC0 both CCs and OVERFLOW
events by examination of events scheduled on them. The pretick is set
based on number of ticks to the closest event scheduled that can trigger
an interrupt.

Because the operation in `z_arm_on_enter_cpu_idle` hook would
take too much time with interrupts disabled, the
`z_arm_on_enter_cpu_idle_prepare` hook enabled by Kconfig option
`ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK` is used. It performs RTC0 and RTC1
examination, and sets pretick without interrupts being blocked.

The LDREX/STREX are leveraged to detect if exception took place
between start of `z_arm_on_enter_cpu_idle_prepare` and
`z_arm_on_enter_cpu_idle`. If exception has not been taken, the pretick
calculation can be trusted because source data could not changed and
too much time could not pass. Otherwise the sleep attempt is disallowed,
the idle will loop again and try later.

Prompt for `SOC_NRF53_RTC_PRETICK` Kconfig option allows to control
this option by an user and turn the feature off if necessary.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Krzysztof Chruściński
31eaffdf05 nrf53: Add RTC pretick
Add RTC pretick option that triggers HW activity one tick before and
RTC event that leads to the interrupt. Option is active only on nrf53
network core.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Guillaume Gautier
6f76e0dcf8 soc: arm: st_stm32: stm32u5: add stm32u5a5 soc
Add STM32U5A5 SOC

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-09-29 10:34:33 +02:00
Manuel Argüelles
d212e50eaf soc: nxp_s32: enable RTU.PIT timers for S32ZE
Each RTU includes one PIT instance that can be used by any
of the cores.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-29 09:47:35 +02:00
Dat Nguyen Duy
8185faa0cb drivers: dma_mcux_edma: add support dma driver for s32k344
On S32K344, the offset in memory map between each channel
is 0x4000 for most channels, but there is specific case is
between channel 11 and 12 which is 0x1D4000 instead. As a
consequence, 32 channels are divided to two parts: one
starts from channel 0 -> 11. The other is from channel 128
to 145. The channel gap is from 12 -> 127.

For user and data structures in shim driver, the channel's
value comes from 0 --> 31. Above constraint will be counted
when interact with the mcux sdk

Beside that, the DMAMUX register in this platform is very
specific, not in identical with DMAMUX channel, so shim
driver is updated to cover this case

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2023-09-27 14:02:09 -05:00
Flavio Ceolin
646a06c9fe random: Fix kconfig symbol name
s/CSPRING_ENABLED/CSPRNG_ENABLED/g

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-09-27 11:55:10 -05:00
Jeff Daly
83de11d9f3 Microchip MEC172X: Rework GPIO definitions to separate package types.
MEC172X has 2 package sizes with additional pins on the -LJ package.
This commit separates the package-specific parts into different files.
In addition, this patch removes unnecessary package-specific enums in
favor of calculated offsets into the desired registers.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
2023-09-26 16:53:29 +02:00
Yong Cong Sin
3300b31de8 boards: ti_k3: prevent header dependencies
These headers are using things like `uint32_t` & devicetree
macros, so they should include the `devicetree.h` & `types.h`.

Otherwise they depend on the parent file to have those headers
included before they are included.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-26 12:03:54 +02:00
Yong Cong Sin
b49d0addc5 soc: ti_k3: guard the soc header
Add macro guard to the soc header to prevent multiple inclusion

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-26 12:03:54 +02:00
Alberto Escolar Piedras
c7c3c82aa0 soc nordic_nrf: Select new compatible kconfig options
Select the newly introduced nrf53 compatible kconfig options.
These are common both for real HW and for simulated HW,
allowing SW to behave appropriately for both.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-09-25 16:42:45 +02:00
Daniel DeGrasse
9e5188353e soc: arm: nxp_imx: add support for SMARTDMA for RT5xx
Add support for SMARTDMA to RT5xx SOCs. SMARTDMA ram banks will be
powered up, so code can be programmed into this region for the SMARTDMA
engine.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-09-25 09:46:55 +02:00
Roland Lezuo
f4c901b82d soc: arm: st_stm32: add config to allow debugger attach in sleep/stop modes
Adds CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP to allow debugger attaching in
sleep/stop mode of STM32 parts. Mainly useful for debugging. Move DBGMCU
from part-sepcific power.c to common soc_config.c. CONFIG_USE_SEGGER_RTT
depends on this as well.

Signed-off-by: Roland Lezuo <roland.lezuo@embedded-solutions.at>
2023-09-22 15:31:47 +02:00
Aaron Ye
09e7e2db51 soc: arm: Add support for Ambiq Apollo4 Blue Plus.
Added devicetree and Kconfig for Apollo4 Blue Plus SoC.
They are needed for the apollo4p_blue_kxr_evb board.

Signed-off-by: Aaron Ye <aye@ambiq.com>
2023-09-22 08:29:29 -05:00
Declan Snyder
15bc6a2389 soc: lpc55s3x: Enable VREF
Add node for VREF0 peripheral to LPC55S3X SOC DT

Clock VREF peripheral if status = okay in DT

Enable VREF on lpcxpresso55s36

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-09-21 09:26:57 +02:00
Manuel Argüelles
7fca0aa8a6 nxp_s32: enable clock control for S32ZE
Enable clock control driver for NXP S32ZE SoCs and add clock sources
definitions for devicetree.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-20 17:25:44 +01:00
Gerard Marull-Paretas
49df14c08a dts: arm: nordic: fix cryptocell description
The ARM Cryptocell 310/312 IP is wrapped by Nordic specific registers.
It is organized as follows:

- Base address: Nordic wrapper
- Base address + 0x1000: ARM Cryptocell IP registers

Following more standard devicetree conventions, use a single node for
what is exposed as a single peripheral. The node contains 2 register
entries, one for the wrapper and a second one for the 3rd party IP.
Compatibles are used from more specific (nordic,cryptocell) to more
generic (arm,cryptocell-3xx).

Other minor fixes: peripheral is disabled by default (as it should be in
SoC dts files).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-20 13:54:38 +01:00
Jonas Otto
2baac8e769 soc: Add support for STM32F072X8
Adds support for the STM32F072X8 SOC, which is a variant of the
existing STM32F072XB with less flash.

Signed-off-by: Jonas Otto <jonas@jonasotto.com>
2023-09-19 15:25:09 +01:00
Filip Kokosinski
8131a67d6f soc/arm/silabs_exx32: select missing CONFIG_SOC_GECKO_SERIESx
This commit:
* adds the `CONFIG_SOC_GECKO_SERIES0` Kconfig option for Gecko Series 0
  SoCs
* selects the proper `CONFIG_SOC_GECKO_SERIESx` option where it's currently
  missing

Fixes #62806.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-09-19 09:32:55 -04:00
Gerard Marull-Paretas
efb8408ba2 soc: arm: nordic_nrf: nrf52: deprecate GPIO_AS_PINRESET
In favor of devicetree property in the UICR node.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-18 13:14:08 +02:00
Yonatan Schachter
fb140de04a soc: silabs_exx32: Select SOC_GECKO_SERIES1 for 1x devices
Select SOC_GECKO_SERIES1 for all Silabs devices of the series 1x.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2023-09-18 12:55:40 +02:00
Daniel DeGrasse
23264c4b3a soc: arm: nxp_imx: introduce ROM ramloader feature
The iMX RT bootrom allows the user to load images into RAM regions from
flash by providing a correctly configured boot header. In particular, if
the boot header contains a load address within RAM, the bootroom will
automatically copy the image to the load address before executing it

Introduce CONFIG_NXP_IMX_RT_ROM_RAMLOADER to enable this feature. This
Kconfig will shift the LMA of a image built to run in a RAM region to
reside in the default FlexSPI boot region, which allows the image to be
loaded to the FlexSPI region using west. This is intended to simplify
development of applications executing from RAM on iMX RT based systems.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-09-15 14:37:07 -05:00
Gerard Marull-Paretas
0762008586 soc: arm: nordic_nrf: deprecate CONFIG_NFCT_PINS_AS_GPIOS
In favor of the new UICR nfct-pins-as-gpios devicetree property.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 16:05:28 +02:00
Carlo Caione
e4a125b6a4 dt: Make zephyr,memory-attr a capabilities bitmask
This is the final step in making the `zephyr,memory-attr` property
actually useful.

The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.

With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.

The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).

For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_VOLATILE |
			       DT_MEM_NON_CACHEABLE |
			       DT_MEM_OOO )>;
   };

The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-region = "NOCACHE_REGION";
       zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
   };

See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).

The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
			       DT_MEM_SW_ALLOCATABLE )>;
   };

Or maybe we can leverage the property to specify some alignment
requirements for the region:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_CACHEABLE |
			       DT_MEM_SW_ALIGN(32) )>;
   };

The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).

When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`

Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory  region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-09-15 12:46:54 +02:00
Gerard Marull-Paretas
aaeb0a672e toolchain: only include <zephyr/toolchain.h>
It is wrong to use toolchain-specific header files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 09:27:30 +02:00
Marcin Niestroj
f15e7c5909 soc: arm: st: set SWO reference frequency based on 'rcc'
Configure SWO reference frequency to be the same as
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. This should make all ST boards ready to
be used with SWO, without configuring any other devicetree property.

Tested with NUCLEO-L476RG and NUCLEO-H563ZI.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2023-09-13 16:29:56 +02:00
Jordan Yates
1e06ba2328 soc: arm: nordic: handle nRF52832 anomaly 109
Enable workaround for anomaly 109 by default when affected peripherals
are enabled.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-09-13 12:05:27 +02:00
Paulo Santos
395395b266 soc: arm: efr32bg22: add missing GPIO flag
Add the missing SOC_GECKO_GPIO selection to the EFR32BG22 SoC Series.

Signed-off-by: Paulo Santos <pauloroberto.santos@edge.ufal.br>
2023-09-13 11:49:27 +02:00
Huifeng Zhang
2c22e83dfb include: arch: arm: Remove aarch32 directory
This commit follows the parent commit work.

This commit introduces the following major changes.

  1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
    to the 'include/zephyr/arch/arm' directory.

  2. Change the path string which is influenced by the changement 1.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-09-13 10:08:05 +01:00
Huifeng Zhang
df41deac1c arch: arm: Remove aarch32 directory
It doesn't make sense to keep the aarch32 directory in the
'arch/arm/core' directory as the aarch64 has been moved out.

This commit introduces the following major changes.

  1. Move all directories and files in 'arch/arm/core/aarch32' to
    'arch/arm/core' and remove the 'arch/arm/core/aarch32' directory.
  2. Move all directories and files in 'arch/include/aarch32' to
    'arch/include' and remove the 'arch/include/aarch32' directory.
  3. Remove the nested including in the 'arch/include/kernel_arch_func.h'
    and 'arch/include/offsets_short_arch.h' header files.
  4. Change the path string which is influenced by the changement 1
    and 2.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-09-13 10:08:05 +01:00
Albort Xue
2073dc9cdd boards: arm: lpcxpresso55s36: Added dac support for LPC55S36
Added dac support for the LPC55S36 board, updated lpc55xxx/soc.c to
enable clock and power for dac0.

Signed-off-by: Albort Xue <yao.xue@nxp.com>
2023-09-11 19:55:26 +02:00
Mulin Chao
eacdadf270 driver: adc: npcx: remove threshold-reg-offset DT property
Remove `threshold-reg-offset` DT property and implement them with static
inline functions in `reg_def.h`

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-09-08 14:43:37 +02:00
Mulin Chao
72ee4f75ef driver: adc: npcx: add multi-device support in npcx adc driver
Add multi-device support in npcx adc driver since there is more than one
adc module in npcx4 series. And each adc's reference voltage might be
different, this CL introduces the `vref-mv` prop. to select its own
reference voltage.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Kate Yen <htyen@nuvoton.com>
2023-09-08 14:43:37 +02:00
Piotr Dymacz
98e104fe3d soc: cc13x2_cc26x2: disable CCFG when building MCUboot chain-loaded images
The 'CCFG' (Customer Configuration) occupies 88 bytes in topmost flash
sector (8 KiB) and is by default always included in the final image.

This disables including CCFG part when building images for chain-loading
by the MCUboot bootloader.

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
2023-09-07 08:51:21 -05:00
Richard Wheatley
a92008c17d soc: arm: ambiq: apollo4: add simobuck init to apollo4 init
Adds comments and simobuck init function for low power.

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2023-09-06 09:33:06 +02:00
Warren Buffer
09577b0a0e soc: Added support for EFR32MG12P433F1024GM68
Added devicetree and Kconfig for EFR32MG12P433F1024GM68, needed for
the BRD4170A radio board by Silicon Labs.

Signed-off-by: Warren Buffer <warren.buffer78@gmail.com>
2023-09-05 16:16:30 +02:00
Gerard Marull-Paretas
35479cccac soc: arm: atmel_sam0: common: bossa: add missing init.h
Because modules uses SYS_INIT, from init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-05 12:19:04 +02:00
Vinayak Kariappa Chettimada
9ede8cd87e dts: nRF: Add missing headermask binding for NRF_CCM
Add missing headermask binding for NRF_CCM peripheral and
define HAS_HW_NRF_CCM_HEADERMASK Kconfig.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2023-09-05 10:04:57 +02:00
Gerard Marull-Paretas
4747218837 soc: arm: ti_simplelink: cc13x2_cc26x2: compile power.c if PM_DEVICE=y
power.c contains some struct definitions required by the HAL when using
PM_DEVICE.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-04 12:22:55 +02:00
Sreeram Tatapudi
09a07e42c0 drivers: cat1: Updates to support latest version of HAL/PDL
- Refactoring to support latest versions of HAL/PDL

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2023-09-01 09:52:25 +02:00
Gerard Marull-Paretas
c315c9b97c soc: arm: ti_simplelink: cc13x2_cc26x2: add support for sys_poweroff
Implement sys_poweroff() hooks, based on previous SOFT_OFF
implementation.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 14:42:26 +02:00
Rahul Arasikere
da55c26593 soc: arm: Add Kconfig option for SOC_STM32F765XX
Adds a new Kconfig menuchoice for the STM32F765xx series.

Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
2023-08-31 10:21:25 +02:00
Gerard Marull-Paretas
b459064ec1 soc: arm: st_stm32: wl: add support for sys_poweroff
Implement the hook for sys_poweroff based on the SOFT_OFF code. Note
that standby mode was a substate of SOFT_OFF, however, it was not
supported judging from defined DT states. It can be added later using
the STANDBY state.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
574360cba0 soc: arm: st_stm32: wba: remove redundant entry in pm_exit_post_ops
SOFT_OFF is not supported for this SoC, also, SOFT_OFF will never reach
the PM post ops.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
d7a0b4fa93 soc: arm: st_stm32: u5: add support for sys_poweroff
Add support for the sys_poweroff hook, re-using code from the SOFT_OFF
state.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
b97b17a4f5 soc: arm: st_stm32: wb: add support for sys_poweroff
Implement the sys_poweroff() hook. The hsem locking is not part of the
implementation, it doesn't seem necessary after
https://github.com/zephyrproject-rtos/zephyr/pull/42409 but I may be
wrong. Needs verification.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
643383b060 soc: arm: st_stm32: l4: add support for sys_poweroff
Convert SOFT_OFF handler to sys_poweroff hook.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
11242691cd soc: arm: st_stm32: l0: remove unsupported state
SOFT_OFF state (which translates to standby) doesn't seem to be
supported according to the L0 DT files. Also, by definition soft off
implies context loss, ie boot from scratch, but the implementation
expected a call to the PM exit hook.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
00ff421129 soc: arm: nxp_imx: rt10xx: s/device.h/init.h
File was not using any device.h API, but init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:53:50 +02:00
Gerard Marull-Paretas
b3b8a19e02 soc: arm: nuvoton_npcx: common: s/device.h/init.h
File was not using any device.h API, but init.h (SYS_INIT).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:53:35 +02:00
Tristen Pierson
1f2180e8ff drivers: adc: adc_sam0: fix c20 and c21 reference not setting
drivers: adc: adc_sam0: fix c20 and c21 reference not setting

On c20 and c21 variants, the adc_sam0 driver is failing to honor the
enable-protected status of the REFCTRL register when writing the channel
config's reference into it. This causes the reference to never be set
when adc_sam0_channel_setup is called since the ADC is not disabled
prior to the write. Fix it by adding the
ADC_SAM0_REFERENCE_ENABLE_PROTECTED definition to the c20 and c21 soc.h
files. This effectively disables the ADC during writes to the REFCTRL
register, thus honoring the enable-protected behavior of this register.
I'm assuming ADC_SAM0_REFERENCE_ENABLE_PROTECTED exists for this type
of situation and therefore this was the approach taken. After making
the change, I was able to verify proper ADC readings by measuring
voltage on an ADC pin and observing correct values. Reverting back prior
to this change, running the same test yields reading 0's.

Fixes: #61975

Signed-off-by: Tristen Pierson <tpierson@bitconcepts.tech>
2023-08-30 10:21:15 +02:00
Francois Ramu
66caf58265 soc: arm: stm32h7x mapping system memory region
System memory declared by the MPU as 'Strongly Ordered'
with region attributes which will inhibit the speculative fetch,
preventing the Flash RDSERR.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-08-30 10:17:39 +02:00
Gerard Marull-Paretas
f88d21cdb9 soc: arm: nordic_nrf: nrf53: sync_rtc: add missing init.h
File was using SYS_INIT, from init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-29 14:35:45 +01:00
Mulin Chao
f942b44c56 soc: arm: npcx: move workaround methods for npcx series to its soc.c
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-08-28 08:22:10 +01:00
Maximilian Deubel
4cde3ea70f soc: arm: nordic_nrf: nrf91: rename nRF9161 SICA to LACA
This patch corrects the name of the nRF9161,
which is LACA, not SICA.

Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
2023-08-25 13:48:17 +02:00
Maximilian Deubel
dc954977b7 soc: arm: nordic_nrf: nrf91: add nRF9131 LACA
This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.

Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
2023-08-25 11:56:12 +02:00
Mateusz Sierszulski
be149593c9 drivers: pinctrl: Add more config options for Ambiq Apollo4
This commits add more configuration options
for Ambiq Apollo4 pinctrl driver.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2023-08-25 10:31:58 +02:00