soc: arm: nxp_imx: rt5xx: clock DMIC0
Clock DMIC0 from the audio PLL when DMIC driver class is enabled. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
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@ -427,6 +427,19 @@ void __weak rt5xx_clock_init(void)
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RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay)
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/* Using the Audio PLL as input clock leads to better clock dividers
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* for typical PCM sample rates ({8,16,24,32,48,96} kHz.
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*/
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/* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ
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* Select Audio PLL as clock source. This should produce a bit clock
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* of 3.072MHZ
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*/
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CLOCK_AttachClk(kAUDIO_PLL_to_DMIC);
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CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 8);
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#endif
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/* Set SystemCoreClock variable. */
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SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
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