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soc: arm: nxp_imx: rt5xx: clock DMIC0

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Clock DMIC0 from the audio PLL when DMIC driver class is enabled.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This commit is contained in:
Daniel DeGrasse 2023-12-05 23:08:48 +00:00 • committed by Carles Cufí
commit 6d562f1750
1 changed files with 13 additions and 0 deletions
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13
soc/arm/nxp_imx/rt5xx/soc.c
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@ -427,6 +427,19 @@ void __weak rt5xx_clock_init(void)
RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn);
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay)
/* Using the Audio PLL as input clock leads to better clock dividers
* for typical PCM sample rates ({8,16,24,32,48,96} kHz.
*/
/* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ
* Select Audio PLL as clock source. This should produce a bit clock
* of 3.072MHZ
*/
CLOCK_AttachClk(kAUDIO_PLL_to_DMIC);
CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 8);
#endif
/* Set SystemCoreClock variable. */
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;