Commit graph

281 commits

Author SHA1 Message Date
Anas Nashif f2cb20c772 docs: fix misspelling across the tree
Found a few annoying typos and figured I better run script and
fix anything it can find, here are the results...

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-19 15:34:13 -05:00
Ioannis Glaropoulos fd97e44011 arch: remove unused tracing_arch.h
The API in tracing_arch.h is not used by the
kernel so we remove it.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-05-13 14:04:15 -07:00
Flavio Ceolin 4f99a38b06 arch: all: Remove not used struct _caller_saved
The struct _caller_saved is not used. Most architectures put
automatically the registers onto stack, in others architectures the
exception code does it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2019-04-18 12:24:56 -07:00
Flavio Ceolin d61c679d43 arch: all: Remove legacy code
The struct _kernel_ach exists only because ARC' s port needed it, in
all other ports this was defined as an empty struct. Turns out that
this struct is not required even for ARC anymore, this is a legacy
code from nanokernel time.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2019-04-18 12:24:56 -07:00
Anas Nashif 3ae52624ff license: cleanup: add SPDX Apache-2.0 license identifier
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier.  Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.

By default all files without license information are under the default
license of Zephyr, which is Apache version 2.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-07 08:45:22 -04:00
Andrew Boie 4e5c093e66 kernel: demote K_THREAD_STACK_BUFFER() to private
This macro is slated for complete removal, as it's not possible
on arches with an MPU stack guard to know the true buffer bounds
without also knowing the runtime state of its associated thread.

As removing this completely would be invasive to where we are
in the 1.14 release, demote to a private kernel Z_ API instead.
The current way that the macro is being used internally will
not cause any undue harm, we just don't want any external code
depending on it.

The final work to remove this (and overhaul stack specification in
general) will take place in 1.15 in the context of #14269

Fixes: #14766

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-04-05 16:10:02 -04:00
Patrik Flykt 7c0a245d32 arch: Rename reserved function names
Rename reserved function names in arch/ subdirectory. The Python
script gen_priv_stacks.py was updated to follow the 'z_' prefix
naming.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-04-03 17:31:00 -04:00
Patrik Flykt 97b3bd11a7 drivers: Rename reserved function names
Rename reserved function names in drivers/ subdirectory. Update
function macros concatenatenating function names with '##'. As
there is a conflict between the existing gpio_sch_manage_callback()
and _gpio_sch_manage_callback() names, leave the latter unmodified.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-04-03 17:31:00 -04:00
Ulf Magnusson 12ba9dfa52 scripts: Remove unused variables in all Python scripts
Discovered with pylint3.

Use the placeholder name '_' for unproblematic unused variables. It's
what I'm used to, and pylint knows not to flag it.

Python tip:

    for i in range(n):
        some_list.append(0)

can be replaced with

    some_list += n*[0]

Similarly, 3*'\t' gives '\t\t\t'.

(Relevant here because pylint flagged the loop index as unused.)

To do integer division in Python 3, use // instead of /.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-03-28 11:06:20 -05:00
Flavio Ceolin fdfb2109a2 arch: Use macro BIT for shift operations
BIT macro uses an unsigned int avoiding implementation-defined behavior
when shifting signed types.

MISRA-C rule 10.1

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2019-03-26 22:06:45 -04:00
Flavio Ceolin d410611180 arch: Use macro BIT for shift operations
BIT macro uses an unsigned int avoiding implementation-defined behavior
when shifting signed types.

MISRA-C rule 10.1

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2019-03-26 14:31:29 -04:00
Ulf Magnusson 5c8fd84d12 scripts: Remove extra trailing newlines from Python scripts
Fixing all instances so that it can be flagged in a pylint CI check
later.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-03-26 07:53:08 -05:00
Patrik Flykt 4344e27c26 all: Update reserved function names
Update reserved function names starting with one underscore, replacing
them as follows:
   '_k_' with 'z_'
   '_K_' with 'Z_'
   '_handler_' with 'z_handl_'
   '_Cstart' with 'z_cstart'
   '_Swap' with 'z_swap'

This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.

Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.

Various generator scripts have also been updated as well as perf,
linker and usb files. These are
   drivers/serial/uart_handlers.c
   include/linker/kobject-text.ld
   kernel/include/syscall_handler.h
   scripts/gen_kobject_list.py
   scripts/gen_syscall_header.py

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-11 13:48:42 -04:00
Daniel Leung 1e7025c2e7 boards: intel_s1000_crb: fix setting cache attributes
This reverts commit c9ace83c89 which
bypasses setting cache attributes.

The previous cache attributes actually set the text/data/etc.
sections to be inaccessible. So fix it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-15 16:21:50 -05:00
Daniel Leung c17d0dc2c5 esp32: fix build error regarding multiplt BIT() definitions
This partially reverts commit 5a47c60dbf.
The soc.h is now only included when _soc_irq_*() is being referred.

Fixes #11077.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-01-11 15:05:31 -08:00
Sebastian Bøe f42ed32dc5 Kconfig: Hide SMP and USE_SWITCH from unsupported platforms
Don't present USE_SWITCH and SMP to user applications that are
configuring for platforms that do not support SMP or USE_SWITCH.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-12-30 16:24:50 -05:00
Piotr Zięcik 717cfd4b09 arch: xtensa: Remove unused field from _thread_arch
This commit removes the custom_data field from _thread_arch
for xtensa platform as it is currently unused.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-12-11 15:33:07 -05:00
Flavio Ceolin 46715faa5c kernel: Remove _IntLibInit function
There were many platforms where this function was doing nothing. Just
merging its functionality with _PrepC function.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-11-28 14:59:10 -08:00
Patrik Flykt 66a4a11836 arch/xtensa: Use C style comments
Update comments to follow C style.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2018-11-15 17:38:25 -05:00
Patrik Flykt 8d769d5533 arch/xtensa: Remove identifier looking as mixed C/C++ comments
The identifier looks like a mixed C/C++ comment, which is against
MISRA-C rule 3.1. As the identifier is not used, remove it altogether.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2018-11-15 17:38:25 -05:00
Andy Ross 23159cedec xtensa legacy: Fix stale use of removed kconfigs
The old xtensa layer had an unused/untested facility where it would
apparently try to slave a timer tick to an arbitrary interrupt.  The
legacy headers were still checking the kconfigs used to enable that
even though nothing wants it and the new driver has removed them,
breaking builds on platforms like S1000 that still use the older
layer.

Don't try to finess this as these files are going away.  Just make
them local preprocessor symbols and set them to the default values
they always had.

(Note: the feature doesn't sound like it would have been so bad,
actually.  We should probably crib that idea of having an
"external_tick" driver, but there's no reason for it to have been
arch-specific.)

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-14 19:08:27 -05:00
Andy Ross d411514a5f xtensa: Don't call ISRs for disabled interrupts
Xtensa interrupts are handled generically, by testing a set of flagged
interrupts in the INTERRUPT register.  It's not possible to know
exactly which device "caused" an interrupt.

The entry code was dispatching correctly, but it was failing to test
the enable state in INTENABLE.  Such an interrupt will never "fire",
but it might still be flagged, and if we happen to end up handling an
interrupt of the same priority (due to some other device) the entry
handler would incorrectly invoke the disabled interrupt.

Found by dumb luck and a comedy of errors: the recent timer driver
change swapped the counter in use, which changed the interrupt number
to one shared with the I2C driver, whose early interrupts (odd that
this device is interrupting on boot when not in use, but whatever)
would then discover the OTHER timer counter had been flagged and try
to invoke an ISR for that other counter, which was the _irq_spurious()
spurious interrupt handler.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-14 19:08:27 -05:00
Andy Ross 0670ba6c92 xtensa: Disable interrupts on entry to _Cstart
Zephyr isn't ready to handle interrupts yet, until the
threading/scheduler are set up and we make our first context switch.
This was a semi-hidden bug: only the timer interrupt would actually
get unmasked before the system was ready, and obviously would never
have time to fire a tick before the system completed initialization.
But a combination of system load and a new version of Qemu (which
seems to be more sensitive to non-deterministic timing glitchery) has
made this visible.  About 2-3% of the time when run under a full
sanitycheck, the qemu process will get swapped away for long enough
that the tick timer expires before _Cstart() has reached
enable_multithreading().

It looks like the original code was cut and pasted from another
implementation, which was expected to call into an "application"
main() routine that wanted interrupts ready.

Fixes #11182

(Note also that this code is not used for ESP-32, which has its own
startup path)

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-12 13:51:20 -05:00
Andrew Boie 47d30d087b xtensa: add _arch_irq_connect_dynamic()
Implements dynamic interrupts.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Daniel Leung 5a47c60dbf arch: xtensa: include soc.h to fix build errors
There are places where soc.h must be included. So include it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-11-03 12:40:33 -04:00
Leandro Pereira aa442d13e7 arch: xtensa: Do not generate unused handle_irq label unless needed
This was causing a `label handle_irq defined but not used` warning
during build.

Fixes #10801.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-27 21:25:57 -04:00
Leandro Pereira a71c365180 arch: xtensa: Reduce size of interrupt handling routines
This patch reduces the size of ISRs by changing the script to generate
the dispatcher per level to, instead of generating an indirect call per
mask match, do that just once at the function end.

For ESP32, this provides ~380bytes of savings in a (very) hot path
(text, just for the matcher functions generated by xtensa_intgen.py,
drop from 2197 bytes to 1817 bytes).

The generated code also uses the BIT() macro, which shifts 1UL instead
of 1.  Shifting a signed integer is UB in C.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-22 13:38:29 -07:00
Daniel Leung ecfc1b4ec1 xtensa: specify which SR to store pointer to _kernel.cpu struct
This allows Kconfig to specify which special register is being
used to store the pointer to the _kernel.cpu struct.
Since the SoC itself is highly configurable, sometimes MISC0 is not
available. So this adds the ability to use other special registers.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 17:52:45 -04:00
Adithya Baglody e9cb0ae72a arch: kernel_arch_func.h: Fix MISRA violation
Always compare unsigned interger type with another unsigned
integer type. Currently in nios2, posix, riscv32, x86 and xtensa
we were comparing the _kernel.nested variable with a signed
interger type. Fixed this violation.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-10-17 12:17:58 -04:00
Flavio Ceolin 78f27a81f5 kernel: Using the same paramenters names in a specific function
MISRA-C requires that all declarations of a specific function, or
object, use the same names and type qualifiers.

MISRA-C rule 8.3

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-28 07:58:19 +05:30
Krzysztof Chruscinski 27459a13e4 arch: Add LOG_PANIC to fault handlers
Added LOG_PANIC to fault handlers to ensure that log is flush and
logger processes messages in a blocking way in fault handler.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2018-09-27 13:11:26 +05:30
Flavio Ceolin 4a211ec241 include: Add missing headers guard
Add missing headers guard

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Flavio Ceolin 67ca176754 headers: Fix headers across the project
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Flavio Ceolin da49f2e440 coccicnelle: Ignore return of memset
The return of memset is never checked. This patch explicitly ignore
the return to avoid MISRA-C violations.

The only directory excluded directory was ext/* since it contains
only imported code.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
Anas Nashif abcf2ad5a8 kconfig: move soc selection to ZEPHYR_BASE/soc/
Rather than do that for each architecture, source SoC Kconfigs where the
code is maintained, under ZEPHYR_BASE/soc.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif cea0b3a9c2 xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Sathish Kuttan c5f04d7c24 arch: xtensa: remove extra #endif
Remove extra #endif that should have been removed when the
corresponding #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP was
removed in commit a2248782a2

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-09-04 14:27:33 -04:00
Anas Nashif 3298905bfe xtensa: removed obsolete headers
Went in by mistake in a bad rebase, fixes #9753.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-01 13:58:46 -04:00
Anas Nashif 483910ab4b systemview: add support natively using tracing hooks
Add needed hooks as a subsystem that can be enabled in any application.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Anas Nashif a2248782a2 kernel: event_logger: remove kernel_event_logger
Move to more generic tracing hooks that can be implemented in different
ways and do not interfere with the kernel.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Adithya Baglody bb918d85f8 tests: benchmarks: timing_info: Enable benchmarks for xtensa.
This patch provides support needed to get timing related
information from xtensa based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Sathish Kuttan 824bcaca52 xtensa: intel_s1000: Add SoC level SYS_INIT
Added a SYS_INIT for SoC level initialization of Intel S1000
Added routines for setting up resource ownership for
    DMA, I2S
Added routine to setup power gating and clock configuration

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-08-19 11:06:09 -07:00
Ulf Magnusson 17f1b0adec Kconfig: Switch to improved globbing statements
A design flaw of 'gsource' is that there's no way to require at least
one file to match the glob pattern. This could lead to silent errors.

Switch to a new design, where a plain 'source' is globbing and requires
at least one file to match. A separate 'osource' (optional source)
statement is available for cases where it's okay for a pattern (or plain
filename) to not match any files.

'orsource' combines 'osource' and 'rsource' (relative source).

This commit search-replaces 'gsource' with 'source', but backwards
compatibility with 'gsource' is still maintained by making it an alias
for 'osource' (and by making 'grsource' an alias for 'orsource').

The three Kconfig files arch/{nios2,posix,xtensa}/Kconfig source
arch/{nios2,posix,xtensa}/soc/*/Kconfig, which doesn't match any files.
Use 'osource' for those. The soc/*/Kconfig files seem to be for
additional SoC-specific symbols, only none exist yet on those ARCHes.

Also use 'osource' for the source of $ENV_VAR_BOARD_DIR/Kconfig in
boards/Kconfig, which doesn't exist for all boards.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-15 04:07:44 -07:00
Ulf Magnusson ec3eff57e0 Kconfig: Use the first default with a satisfied condition
Up until now, Zephyr has patched Kconfig to use the last 'default' with
a satisfied condition, instead of the first one. I'm not sure why the
patch was added (it predates Kconfiglib), but I suspect it's related to
Kconfig.defconfig files.

There are at least three problems with the patch:

  1. It's inconsistent with how Kconfig works in other projects, which
     might confuse newcomers.

  2. Due to oversights, earlier 'range' properties are still preferred,
     as well as earlier 'default' properties on choices.

     In addition to being inconsistent, this makes it impossible to
     override 'range' properties and choice 'default' properties if the
     base definition of the symbol/choice already has 'range'/'default'
     properties.

     I've seen errors caused by the inconsistency, and I suspect there
     are more.

  3. A fork of Kconfiglib that adds the patch needs to be maintained.

Get rid of the patch and go back to standard Kconfig behavior, as
follows:

  1. Include the Kconfig.defconfig files first instead of last in
     Kconfig.zephyr.

  2. Include boards/Kconfig and arch/<arch>/Kconfig first instead of
     last in arch/Kconfig.

  3. Include arch/<arch>/soc/*/Kconfig first instead of last in
     arch/<arch>/Kconfig.

  4. Swap a few other 'source's to preserve behavior for some scattered
     symbols with multiple definitions.

     Swap 'source's in some no-op cases too, where it might match the
     intent.

  5. Reverse the defaults on symbol definitions that have more than one
     default.

     Skip defaults that are mutually exclusive, e.g. where each default
     has an 'if <some board>' condition. They are already safe.

  6. Remove the prefer-later-defaults patch from Kconfiglib.

Testing was done with a Python script that lists all Kconfig
symbols/choices with multiple defaults, along with a whitelist of fixed
symbols. The script also verifies that there are no "unreachable"
defaults hidden by defaults without conditions

As an additional test, zephyr/.config was generated before and after the
change for several samples and checked to be identical (after sorting).

This commit includes some default-related cleanups as well:

  - Simplify some symbol definitions, e.g. where a default has 'if FOO'
    when the symbol already has 'depends on FOO'.

  - Remove some redundant 'default ""' for string symbols. This is the
    implicit default.

Piggyback fixes for swapped ranges on BT_L2CAP_RX_MTU and
BT_L2CAP_TX_MTU (caused by confusing inconsistency).

Piggyback some fixes for style nits too, e.g. unindented help texts.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-10 12:38:28 -07:00
Anas Nashif 942ab7ed35 esp32: include register headers in soc.h
This fixes a build issue on esp32 that was introduced recently with the
merge of an old PR.

Include the register headers in soc.h rather than soc.c and make them
available to other code via soc.h

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-16 19:00:32 -04:00
Vitor Massaru Iha f8718758e5 include: drivers: gpio: Turn functions generic - esp32
On 'drivers/i2c_esp32.c' there are functions useful for other
drivers. Functions and struct went moved to:

 * arch/xtensa/soc/esp32/peripheral.h
 * arch/xtensa/soc/esp32/soc.h
 * include/drivers/gpio/gpio_esp32.h

Signed-off-by: Vitor Massaru Iha <vitor@massaru.org>
2018-07-15 16:13:36 -04:00
Sebastian Bøe 347f9a0a2d cmake: LD: Specify the entry point in the linker scripts
The entry point can and therefore should be set by linker
scripts. Whenever possible one should express things in the source
language, be it .c or .ld, and not in code generators or in the build
system.

This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's
command line and replaces it with the linker script command

ENTRY(CONFIG_KERNEL_ENTRY)

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-07-03 17:18:14 -04:00
Ulf Magnusson 8cb6fb7223 arch: xtensa: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Alex Tereschenko 3c1a78ea0d cmake: replace PROJECT_SOURCE_DIR with ZEPHYR_BASE
Both variables were used (with the same value) interchangeably
throughout CMake files and per the discussion in GH issue,
ZEPHYR_BASE is preferred.

Also add a comment with explanation of one vs. the other.

Tested by building hello_world for several boards ensuring no errors.

Fixes #7173.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2018-06-18 15:25:55 -04:00
Yasushi SHOJI 2e0af08e55 build: remove unused CMakeLists.txt
lib/libc/minimal/source/CMakeLists.txt and
lib/libc/minimal/source/stdout/CMakeLists.txt was introduced in
12f8f7616 but it is not used by the build system.  CMakeLists.txt in
the parent dir lib/libc/minimal/CMakeLists.txt adds C files to the
target with the lines like:

    ${CMAKE_CURRENT_SOURCE_DIR}/source/stdlib/atoi.c
    ${CMAKE_CURRENT_SOURCE_DIR}/source/stdlib/strtol.c

To make other empty CMakeLists.txt explicit, this commit adds a
comment line to them.

Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
2018-06-14 15:02:02 -04:00
Gautier Seidel 77643677a1 esp32: update to ESP-IDF v3.0-dev-2648-gb2ff235b
Recent ESP-IDF provides OS-agnostic wifi binary, needed by #3723

Closes #8240

Signed-off-by: Gautier Seidel <gautier.seidel@tado.com>
2018-06-13 18:53:43 -04:00
Rajavardhan Gundi 4ec773f276 DTS: intel_s1000: Clean up I2C and UART stuff from soc.h
Clean up some remnant stuff related to I2C and UART from soc.h
and put it in dts.fixup

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-06-11 17:27:58 -04:00
Rajavardhan Gundi e5b0e9ac07 DTS: interrupt controller: Define IRQ priorities for CAVS & DW ICTL
IRQ priorities for CAVS and DW were previously defined in Kconfig.
They are now defined via DTS and removed from Kconfig.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-06-11 17:27:58 -04:00
Andrew Boie 2dd91eca0e kernel: move thread monitor init to common code
The original implementation of CONFIG_THREAD_MONITOR would
try to leverage a thread's initial stack layout to provide
the entry function with arguments for any given thread.

This is problematic:

- Some arches do not have a initial stack layout suitable for
this
- Some arches never enabled this at all (riscv32, nios2)
- Some arches did not enable this properly
- Dropping to user mode would erase or provide incorrect
information.

Just spend a few extra bytes to store this stuff directly
in the k_thread struct and get rid of all the arch-specific
code for this.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-06-06 14:26:45 -04:00
Sathish Kuttan 9f4702b3b4 arch: soc: intel_s1000: set M/N divider ownership
Add bit definitions and set M/N divider ownership in
i2s_initialize.
Changes to comply with coding guidelines
Changes to address review comments

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-06-01 08:59:01 -04:00
Sathish Kuttan ed33f43e48 arch: xtensa: intel_s1000: Reference clock API
Added a function to obtain the reference clock frequency value based on
SoC's bootstraps.
Added M/N divider base address in SoC header file

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-06-01 08:59:01 -04:00
Andy Ross 1fe6c36730 esp32: Add some "logging" voodoo to SMP initialization
At least one of my WROOM boards has trouble getting the APPCPU
started, that was magically getting better when I started adding
printk's to debug.  It turns out that UART output (and NOT simply idle
cycles of delay) was the magic dust to fix things.  As this SMP
implementation is reverse engineered voodoo to begin with, this hack
should be acceptable in the medium term.

See in-file comments on smp_log() for details.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-05-31 14:02:03 -04:00
Ulf Magnusson 3ac3216d89 soc: defconfig: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Andy Ross 3a0cb2d35d kernel: Remove legacy preemption checking
The metairq feature exposed the fact that all of our arch code (and a
few mistaken spots in the scheduler too) was trying to interpret
"preemptible" threads independently.

As of the scheduler rewrite, that logic is entirely within sched.c and
doing it externally is redundant.  And now that "cooperative" threads
can be preempted, it's wrong and produces test failures when used with
metairq threads.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-05-25 09:40:55 -07:00
Sebastian Bøe cde6bef778 kconfig: Drop support for CONFIG_TOOLCHAIN_VARIANT
The Kconfig option TOOLCHAIN_VARIANT (not to be confused with
ZEPHYR_TOOLCHAIN_VARIANT) is a legacy configuration option that has
very few use-cases and can easily be dropped.

It's functionality is easily covered by CONFIG_X86_IAMCU and
ZEPHYR_TOOLCHAIN_VARIANT.

This commit removes all references of it from Zephyr.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-05-22 11:15:36 -04:00
Savinay Dharmappa 2ebb6a1fee dts: intel_s1000: use dts to set i2c0 priority.
patch removes Kconfig used i2c0 priority, instead use the
macro generated from dts.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-22 09:30:14 -04:00
Savinay Dharmappa 6701d44967 dts: xtensa: Fix build error due to dts changes for ns16550 driver.
patch add clock frequency and interrupt property to uart
node in intel_s1000.dtsi. Include soc.h after types.h to
prevent build error.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-22 08:51:59 -04:00
Tomasz Bursztyka 61ef30d10e drivers/uart: Use dts to set uart options for ns16550 driver
Fix the ns16550 uart driver and relevant SoCs accordingly.
All generic settings are now DTS based.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Andrew Boie 0daf69bb57 xtensa: fix CONFIG_INIT_STACKS for IRQ stack
The interrupt stack area wasn't being set to a repeating
0xAA pattern at boot as it should be. This is now done in
kernel_arch_init(), which runs before interrupts are
enabled for the first time.

Fixes #7327

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-16 12:06:31 -07:00
Savinay Dharmappa 48e2dba28f dts: xtensa: fix build error.
patch fix the build error due to wrong assignment of macro in
the dts.fixup file

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-16 10:25:19 -05:00
Ulf Magnusson 547ed9b563 kconfig: Make 'source' non-globbing and use 'gsource'
Until now, Zephyr has used a patched Kconfiglib that turns 'source' into
a globbing source (by replacing 'source' with 'gsource' at the token
level). There's two problems with this:

  - The patch needs to be maintained separately

  - Misspelled filenames are silently ignored, as they look like glob
    patterns that don't match anything

Fix it as follows:

  1. Replace all 'source' statements that use wildcards with 'gsource'

  2. Remove the custom Kconfiglib patch so that 'source' no longer globs

The sed pattern '/source.*[*?]/s/source/gsource/' was run over all
Kconfig* files to do the replacement.

source's that use environment variables that might contain glob patterns
were manually changed to gsource.

Building the docs in doc/ is a good test, as doc/Makefile deliberately
sets the environment variables to glob up as many Kconfig files as
possible.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2018-05-08 11:14:12 +02:00
Savinay Dharmappa 7be3236ca4 dts: interrupt_controller: Add dts support for DesignWare controller
Add dts support for multilevel DW interrupt controller

Change-Id: Ia16d6870bd3a46fca933c906aedc6ba78ed5131a
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa 9ee4929d56 dts: i2c: Add dts support for i2c
Change-Id: I9104f5230a4efbf1b6979e146e7ea73a76891947
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa 97f721d928 dts: xtensa: Add device tree support for xtensa
Change-Id: I309bc50c6b575caa84fbc7ab98cc9890771b4274
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa 5060f4bd14 driver: usb: enable usb2.0 on intel_s1000
Change-Id: I59091c465e84f1d6ba64433b7320182d83ff9589
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi 5b6f02442b drivers: i2s: introduce CAVS I2S
Implements the driver for Intel CAVS I2S. Only Playback
is currently supported.

Change-Id: I7b816f9736dc35e79a81d3664d6405dc0aac15b4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi cea1c75e2b boards: intel_s1000_crb: enable DMA
Enable the CAVS DMA on intel_s1000. Also, introduce a test to
validate the DMA.

Change-Id: I2ff233c45cfd8aea55e254d905350a666aa649a0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi bd0d5133e4 drivers: dma: introduce Intel CAVS DMA
Introduce the Intel CAVS DMA. This is based out of the DesignWare
DMA IP but the register offset and bits have been changed in some
cases. However, the fundamental definition for the register field
has not been changed. Hence the registers begin with "DW_" to
indicate the Designware origin.

This driver currently supports the single block mode and linked list
multi-block mode. Scatter-Gather is not supported.

Change-Id: I33a8ed5141d9236167de50e14d3d407e95d6f553
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi dadf9e7a81 xtensa: intel_s1000: implement interrupt mechanism
intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.

Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi 9cc381c07a intel_s1000: i2c: enable I2C for intel_s1000
intel_s1000 makes use of DesignWare IP for I2C.

Change-Id: Ie091318c5959b95e1febeb5cefa440f35a6d144b
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi 63d50e158e intel_s1000: gpio: enable GPIO handling
Enable GPIO handling for intel_s1000. It uses a DesignWare IP.

Change-Id: I522534935e4ef3a56d93aca669f6de961d927481
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi 9ed55af2f8 arch: xtensa: set __start as entry point for Xtensa.
__start is deemed the entry point for all architectures in Zephyr.
Accordingly, Xtensa code had to be modified a bit to fall in line
with this convention.

Change-Id: If3ed344721c9f2735378b866662a68d8d5795324
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi 47ff96593f intel_s1000: uart: configure UART for intel_s1000
intel_s1000 uses DesignWare IP for UART. National Semiconductor
16550 (UART) component specification is followed in this IP.

Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi c9ace83c89 xtensa: reset-vector.S hack for booting intel_s1000 [REVERTME]
Setting CACHEATTR from _memmap_cacheattr_reset is making
the intel_s1000 SoC get into some unknown state. Removing
it for intel_s1000_crb for now.

Change-Id: Ib44638ef75de6200ef5c2aad55f093a633da864a
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi 02736e5935 intel_s1000: add intel_s1000_crb board
intel_s1000_crb board makes use of the intel_s1000 SoC. It has
a built-in ROM which gets executed upon applying power. It then
executes the secondary bootloader followed by the FW (like zephyr).

Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi 1fcd39b624 intel_s1000: define memctl_default.S and memerror-vector.S files
Define memctl_default.S and memerror-vector.S files. A reference
could be found in the Xtensa toolchain directories. These are
required for using cavs21_LX6HiFi3_RF3_WB16 Xtensa CPU mainly in
simulator. On boards which have ROM, these would have been already
defined in the ROM. Hence, the contents of these files will be
developed at a later time if required.

Change-Id: Idf52397bb6880c136525e69f47e09defcba7f036
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi f14d1be67f intel_s1000: Add intel_s1000 SoC
intel_s1000 is an SoC having cavs21_LX6HiFi3_RF3_WB16 as the CPU which
belongs to Xtensa family. This is being used in intel_s1000_crb.

Change-Id: Ic424aa77557bf31024ddbf3f1d76b72a4adb8f66
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Andy Ross 9d367eeb0a xtensa, kernel/sched: Move next switch_handle selection to the scheduler
The xtensa asm2 layer had a function to select the next switch handle
to return into following an exception.  There is no arch-specific code
there, it's just scheduler logic.  Move it to the scheduler where it
belongs.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-18 16:58:12 -04:00
Andy Ross 285c5b26dd xtensa/asm2: Save shift/loop registers on exception entry
This was a little embarassing.  The swap code got this right, and the
interrupt exit path got it right, but on entry we weren't ever saving
the shift and loop registers for the interrupted context.

This almost always worked anyway as the loop registers aren't ever
used in any Zephyr code (gcc won't generate this style of loop AFAICT)
and the SAR shift amount register is generally used only in two pairs
of adjacent instructions making the chance of hitting that exact cycle
quite low in general.

But of course we have shift-happy crypto code in our tests, so this
got caught, thankfully.

See https://github.com/zephyrproject-rtos/zephyr/issues/6470

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-06 14:13:56 -08:00
Leandro Pereira 02bc5fa8e0 soc: esp32: Enable building with newer ESP-IDF
ESP-IDF commit cb31222e added the dependency on a file named
"sdkconfig.h", which is equivalent to "autoconf.h" generated by kbuild
used in Zephyr.  It does not depend on anything from that file, though,
so just provide an empty file to keep the compiler from complaining.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-03-05 19:49:06 -05:00
Andy Ross bdac8d070f xtensa/asm2: Fix stack pointer during preemption spills
When returning into a different thread than we interrupted, we
obviously need to spill all the existing register windows to make sure
all their values are in the old thread's stack.  But the code to do
this forgot to reset the current stack pointer to the value it had at
interrupt time (it was still pointing to the saved context below
that), so the caller of the interrupted function was spilling to the
wrong spot.

This wouldn't show up as an instant failure, it would only happen when
switching BACK to the improperly-spilled thread.  And even then it
would be a noop if the original interrupt handler was deep enough to
have spilled that function naturally.

In practice, this happened only in some instances on ESP-32 (which has
more windowed registers than qemu) when interrupting the idle thread
(which is very shallow) with a (very simple) timer interrupt.  Trivial
to see, hard to find.

See https://github.com/zephyrproject-rtos/zephyr/issues/6346 for more
detail.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-05 19:06:07 -05:00
David B. Kinder 3673698df1 doc: fix misspellings in XTENSA Kconfig
regular scan for spelling issues

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-02-22 15:28:04 -05:00
Leandro Pereira 3beb481bab soc: esp32: Fix compile warnings when redefining BIT() macro
Include `soc.h` first, which will include the ESP-IDF headers -- which
will define the `BIT()` macro without checking if they're already
defined, like the Zephyr headers do.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-02-20 16:23:53 -05:00
Andy Ross 60fd06830e xtensa: Make _arch_curr_cpu() work outside SMP
The xtensa headers use this for simplicity when SMP is not enabled.
It should still build on older platforms that don't include the
asm2-style CPU pointer scheme.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 392b3b5aa6 xtensa/asm2: Don't needlessly build asm2 sources
Non-asm2 devices without a generated SoC interrupt file will see a
compile failure due to the missing header.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 57f30bd8cc esp32: Move hard firmware function addresses to the linker script
This matches the way other firmware-provided functions are done.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 0244d01fda xtensa/asm2: Don't return into dead threads
It's not impossible that something we just handled (e.g. a machine
exception) called k_thread_abort() on our current thread.  Don't try
to return into it, check the DEAD state.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 3f5027f835 xtensa: Fix noreturn attribute on error handlers in asm2
In asm2, the machine exception handler runs in interrupt context (this
is good: it allows us to defer the test against exception type until
after we have done the stack switch and dispatched any true
interrupts), but that means that the user error handler needs to be
invoked and then return through the interrupt exit code.

So the __attribute__(__noreturn__) that it was being decorated with
was incorrect.  And actually fatal, as with gcc xtensa will crash
trying to return from a noreturn call.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 245b54ed56 kernel/include: Missed nano_internal.h -> kernel_internal.h spots
Update heading naming given recent rename

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 53eceffb7f esp32: Set CPU pointer on app cpu at startup
It's not enough to wait for a switch, lots of things need this early.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross b0b9b3d16a xtensa: Report CPU number in exceptions
In SMP contexts it's good to know which CPU blew up.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross e694656345 kernel: Move per-cpu _kernel_t fields into separate struct
When in SMP mode, the nested/irq_stack/current fields are specific to
the current CPU and not to the kernel as a whole, so we need an array
of these.  Place them in a _cpu_t struct and implement a
_arch_curr_cpu() function to retrieve the pointer.

When not in SMP mode, the first CPU's fields are defined as a unioned
with the first _cpu_t record.  This permits compatibility with legacy
assembly on other platforms.  Long term, all users, including
uniprocessor architectures, should be updated to use the new scheme.

Fundamentally this is just renaming: the structure layout and runtime
code do not change on any existing platforms and won't until someone
defines a second CPU.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 9c62cc677d kernel: Add kswap.h header to unbreak cycles
The xtensa-asm2 work included a patch that added nano_internal.h
includes in lots of places that needed to have _Swap defined, because
it had to break a cycle and this no longer got pulled in from the arch
headers.

Unfortunately those new includes created new and more amusing cycles
elsewhere which led to breakage on other platforms.

Break out the _Swap definition (only) into a separate header and use
that instead.  Cleaner.  Seems not to have any more hidden gotchas.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross d3376f2781 kernel, esp32: Add SMP kconfig flag and MP_NUM_CPUS variable
Simply define the Kconfig variables in this patch so they can be used
in later patches.  Define MP_NUM_CPUS correctly on esp32.  No code
changes.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross e717267abf kernel, esp32: Add _arch_start_cpu API
This is a mostly-internal API to start a secondary system CPU, with an
implementation for the ESP-32 "APP" cpu.  Exposed in kernel.h because
it's plausibly useful for asymmetric MP code managed by an app.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00