boards: intel_s1000_crb: fix setting cache attributes
This reverts commit c9ace83c89
which
bypasses setting cache attributes.
The previous cache attributes actually set the text/data/etc.
sections to be inaccessible. So fix it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
parent
5f4683db34
commit
1e7025c2e7
2 changed files with 21 additions and 7 deletions
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@ -433,16 +433,10 @@ _xtos_mpu_attribs:
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#elif XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR \
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|| XCHAL_HAVE_XLT_CACHEATTR \
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|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
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/* FixMe: Setting CACHEATTR from _memmap_cacheattr_reset is making the
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* Intel_S1000 SoC get into some unknown state. Removing them only for
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* Intel_S1000_CRB
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*/
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#ifndef CONFIG_BOARD_INTEL_S1000_CRB
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/* note: absolute symbol, not a ptr */
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movi a2, _memmap_cacheattr_reset
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/* set CACHEATTR from a2 (clobbers a3-a8) */
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cacheattr_set
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#endif
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#endif
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/* Now that caches are initialized, cache coherency can be enabled. */
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@ -155,7 +155,27 @@ _memmap_cacheattr_bp_strict = 0x22F22FFF;
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_memmap_cacheattr_wb_allvalid = 0x44224222;
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_memmap_cacheattr_wt_allvalid = 0x11221222;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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_memmap_cacheattr_intel_s1000 = 0xf2ff4242;
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/*
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* Cache attributes for memory addresses:
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* (Each 4 bits correspond to 512MB of memory)
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*
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* 0x00000000 - 0x1FFFFFFF (bit 0 - 3) : Bypass cache
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* (region for hardware registers)
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* 0x20000000 - 0x3FFFFFFF (bit 4 - 7) : No access
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* 0x40000000 - 0x5FFFFFFF (bit 8 - 11) : No access
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* 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access
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* 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache
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* 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back
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* 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache
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* 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-back
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*
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* Note that this is both for instruction and data caches,
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* as cacheattr_set macro sets them both to the same set of
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* attributes.
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*/
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_memmap_cacheattr_intel_s1000 = 0x4242fff2;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);
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SECTIONS
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{
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