xtensa: reset-vector.S hack for booting intel_s1000 [REVERTME]
Setting CACHEATTR from _memmap_cacheattr_reset is making the intel_s1000 SoC get into some unknown state. Removing it for intel_s1000_crb for now. Change-Id: Ib44638ef75de6200ef5c2aad55f093a633da864a Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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@ -433,10 +433,16 @@ _xtos_mpu_attribs:
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#elif XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR \
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|| XCHAL_HAVE_XLT_CACHEATTR \
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|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
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/* FixMe: Setting CACHEATTR from _memmap_cacheattr_reset is making the
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* Intel_S1000 SoC get into some unknown state. Removing them only for
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* Intel_S1000_CRB
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*/
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#ifndef CONFIG_BOARD_INTEL_S1000_CRB
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/* note: absolute symbol, not a ptr */
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movi a2, _memmap_cacheattr_reset
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/* set CACHEATTR from a2 (clobbers a3-a8) */
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cacheattr_set
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#endif
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#endif
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/* Now that caches are initialized, cache coherency can be enabled. */
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