xtensa/asm2: Save shift/loop registers on exception entry

This was a little embarassing.  The swap code got this right, and the
interrupt exit path got it right, but on entry we weren't ever saving
the shift and loop registers for the interrupted context.

This almost always worked anyway as the loop registers aren't ever
used in any Zephyr code (gcc won't generate this style of loop AFAICT)
and the SAR shift amount register is generally used only in two pairs
of adjacent instructions making the chance of hitting that exact cycle
quite low in general.

But of course we have shift-happy crypto code in our tests, so this
got caught, thankfully.

See https://github.com/zephyrproject-rtos/zephyr/issues/6470

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>

arch/xtensa/include/xtensa-asm2-s.h

@@ -226,6 +226,7 @@ _xstack_returned_\@:
 	 */
 	s32i a2, a1, BSA_SCRATCH_OFF
 
+	ODD_REG_SAVE
 	call0 xtensa_save_high_regs
 
 	l32i a2, a1, 0