intel_s1000: Add intel_s1000 SoC
intel_s1000 is an SoC having cavs21_LX6HiFi3_RF3_WB16 as the CPU which belongs to Xtensa family. This is being used in intel_s1000_crb. Change-Id: Ic424aa77557bf31024ddbf3f1d76b72a4adb8f66 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
parent
9fbdab528e
commit
f14d1be67f
4 changed files with 562 additions and 0 deletions
0
arch/xtensa/soc/intel_s1000/CMakeLists.txt
Normal file
0
arch/xtensa/soc/intel_s1000/CMakeLists.txt
Normal file
19
arch/xtensa/soc/intel_s1000/Kconfig.defconfig
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19
arch/xtensa/soc/intel_s1000/Kconfig.defconfig
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# Kconfig - XTENSA board configuration
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#
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_INTEL_S1000
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config SOC
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string
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default intel_s1000
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config IRQ_OFFLOAD_INTNUM
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default 0
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config TOOLCHAIN_VARIANT
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string
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default RF-2015.3-linux
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endif
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6
arch/xtensa/soc/intel_s1000/Kconfig.soc
Normal file
6
arch/xtensa/soc/intel_s1000/Kconfig.soc
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_INTEL_S1000
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bool "intel_s1000"
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537
arch/xtensa/soc/intel_s1000/linker.ld
Normal file
537
arch/xtensa/soc/intel_s1000/linker.ld
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/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Xtensa platform.
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*/
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#define _LINKER
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#define _ASMLANGUAGE
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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#define RAMABLE_REGION sram0_seg :sram0_phdr
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#define ROMABLE_REGION srom1_seg :srom1_phdr
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MEMORY
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{
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sram0_seg : org = 0x80000000, len = 0x3EFE0000
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srom0_seg : org = 0xBEFE0000, len = 0x300
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srom1_seg : org = 0xBEFE0300, len = 0x100
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srom2_seg : org = 0xBEFE0400, len = 0x180
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srom4_seg : org = 0xBEFE0800, len = 0x178
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srom5_seg : org = 0xBEFE0978, len = 0x8
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srom6_seg : org = 0xBEFE0980, len = 0x38
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srom7_seg : org = 0xBEFE09B8, len = 0x8
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srom8_seg : org = 0xBEFE09C0, len = 0x38
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srom9_seg : org = 0xBEFE09F8, len = 0x8
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srom10_seg : org = 0xBEFE0A00, len = 0x38
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srom11_seg : org = 0xBEFE0A38, len = 0x8
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srom12_seg : org = 0xBEFE0A40, len = 0x38
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srom13_seg : org = 0xBEFE0A78, len = 0x8
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srom14_seg : org = 0xBEFE0A80, len = 0x38
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srom15_seg : org = 0xBEFE0AB8, len = 0x8
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srom16_seg : org = 0xBEFE0AC0, len = 0x38
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srom17_seg : org = 0xBEFE0AF8, len = 0x8
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srom18_seg : org = 0xBEFE0B00, len = 0x38
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srom19_seg : org = 0xBEFE0B38, len = 0x8
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srom20_seg : org = 0xBEFE0B40, len = 0x38
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srom21_seg : org = 0xBEFE0B78, len = 0x48
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srom22_seg : org = 0xBEFE0BC0, len = 0x40
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srom23_seg : org = 0xBEFE0C00, len = 0x1D400
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xBEFFE000, len = 0x2000
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#endif
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}
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PHDRS
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{
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sram0_phdr PT_LOAD;
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sram0_bss_phdr PT_LOAD;
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srom0_phdr PT_LOAD;
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srom1_phdr PT_LOAD;
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srom2_phdr PT_LOAD;
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srom3_phdr PT_LOAD;
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srom4_phdr PT_LOAD;
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srom5_phdr PT_LOAD;
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srom6_phdr PT_LOAD;
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srom7_phdr PT_LOAD;
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srom8_phdr PT_LOAD;
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srom9_phdr PT_LOAD;
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srom10_phdr PT_LOAD;
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srom11_phdr PT_LOAD;
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srom12_phdr PT_LOAD;
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srom13_phdr PT_LOAD;
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srom14_phdr PT_LOAD;
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srom15_phdr PT_LOAD;
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srom16_phdr PT_LOAD;
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srom17_phdr PT_LOAD;
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srom18_phdr PT_LOAD;
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srom19_phdr PT_LOAD;
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srom20_phdr PT_LOAD;
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srom21_phdr PT_LOAD;
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srom22_phdr PT_LOAD;
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srom23_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(_ResetVector)
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/* Memory boundary addresses: */
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_memmap_mem_sram_start = 0x80000000;
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_memmap_mem_sram_end = 0xbefe0000;
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_memmap_mem_srom_start = 0xbefe0000;
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_memmap_mem_srom_end = 0xbf000000;
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/* Memory segment boundary addresses: */
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_memmap_seg_sram0_start = 0x80000000;
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_memmap_seg_sram0_max = 0xbefe0000;
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_memmap_seg_srom0_start = 0xbefe0000;
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_memmap_seg_srom0_max = 0xbefe0300;
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_memmap_seg_srom1_start = 0xbefe0300;
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_memmap_seg_srom1_max = 0xbefe0400;
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_memmap_seg_srom2_start = 0xbefe0400;
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_memmap_seg_srom2_max = 0xbefe0580;
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_memmap_seg_srom4_start = 0xbefe0800;
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_memmap_seg_srom4_max = 0xbefe0978;
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_memmap_seg_srom5_start = 0xbefe0978;
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_memmap_seg_srom5_max = 0xbefe0980;
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_memmap_seg_srom6_start = 0xbefe0980;
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_memmap_seg_srom6_max = 0xbefe09b8;
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_memmap_seg_srom7_start = 0xbefe09b8;
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_memmap_seg_srom7_max = 0xbefe09c0;
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_memmap_seg_srom8_start = 0xbefe09c0;
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_memmap_seg_srom8_max = 0xbefe09f8;
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_memmap_seg_srom9_start = 0xbefe09f8;
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_memmap_seg_srom9_max = 0xbefe0a00;
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_memmap_seg_srom10_start = 0xbefe0a00;
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_memmap_seg_srom10_max = 0xbefe0a38;
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_memmap_seg_srom11_start = 0xbefe0a38;
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_memmap_seg_srom11_max = 0xbefe0a40;
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_memmap_seg_srom12_start = 0xbefe0a40;
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_memmap_seg_srom12_max = 0xbefe0a78;
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_memmap_seg_srom13_start = 0xbefe0a78;
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_memmap_seg_srom13_max = 0xbefe0a80;
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_memmap_seg_srom14_start = 0xbefe0a80;
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_memmap_seg_srom14_max = 0xbefe0ab8;
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_memmap_seg_srom15_start = 0xbefe0ab8;
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_memmap_seg_srom15_max = 0xbefe0ac0;
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_memmap_seg_srom16_start = 0xbefe0ac0;
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_memmap_seg_srom16_max = 0xbefe0af8;
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_memmap_seg_srom17_start = 0xbefe0af8;
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_memmap_seg_srom17_max = 0xbefe0b00;
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_memmap_seg_srom18_start = 0xbefe0b00;
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_memmap_seg_srom18_max = 0xbefe0b38;
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_memmap_seg_srom19_start = 0xbefe0b38;
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_memmap_seg_srom19_max = 0xbefe0b40;
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_memmap_seg_srom20_start = 0xbefe0b40;
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_memmap_seg_srom20_max = 0xbefe0b78;
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_memmap_seg_srom21_start = 0xbefe0b78;
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_memmap_seg_srom21_max = 0xbefe0bc0;
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_memmap_seg_srom22_start = 0xbefe0bc0;
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_memmap_seg_srom22_max = 0xbefe0c00;
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_memmap_seg_srom23_start = 0xbefe0c00;
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_memmap_seg_srom23_max = 0xbf000000;
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_rom_store_table = 0;
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PROVIDE(_memmap_vecbase_reset = 0xbefe0800);
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PROVIDE(_memmap_reset_vector = 0xbefe0000);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x00440000;
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_memmap_cacheattr_wt_base = 0x00110000;
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_memmap_cacheattr_bp_base = 0x00220000;
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_memmap_cacheattr_unused_mask = 0xFF00FFFF;
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_memmap_cacheattr_wb_trapnull = 0x2244222F;
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_memmap_cacheattr_wba_trapnull = 0x2244222F;
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_memmap_cacheattr_wbna_trapnull = 0x2255222F;
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_memmap_cacheattr_wt_trapnull = 0x2211222F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0xFF44FFFF;
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_memmap_cacheattr_wt_strict = 0xFF11FFFF;
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_memmap_cacheattr_bp_strict = 0xFF22FFFF;
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_memmap_cacheattr_wb_allvalid = 0x22442222;
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_memmap_cacheattr_wt_allvalid = 0x22112222;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
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SECTIONS
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{
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.sram.rodata : ALIGN(4)
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{
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_image_ram_start = ABSOLUTE(.);
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_sram_rodata_start = ABSOLUTE(.);
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*(.sram.rodata)
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_sram_rodata_end = ABSOLUTE(.);
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} >sram0_seg :sram0_phdr
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#include <linker/common-rom.ld>
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.rodata : ALIGN(4)
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
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KEEP (*(.xt_except_table))
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KEEP (*(.gcc_except_table))
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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KEEP (*(.eh_frame))
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/* C++ constructor and destructor tables, properly ordered: */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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. = ALIGN(4); /* this table MUST be 4-byte aligned */
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_bss_table_start = ABSOLUTE(.);
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LONG(_bss_start)
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LONG(_bss_end)
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_bss_table_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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} >sram0_seg :sram0_phdr
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.sram.text : ALIGN(4)
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{
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_sram_text_start = ABSOLUTE(.);
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*(.sram.literal .sram.text)
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_sram_text_end = ABSOLUTE(.);
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} >sram0_seg :sram0_phdr
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_image_text_start = ALIGN(4);
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.text : ALIGN(4)
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{
|
||||
_stext = .;
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||||
_text_start = ABSOLUTE(.);
|
||||
*(.entry.text)
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||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >sram0_seg :sram0_phdr
|
||||
_image_text_end = .;
|
||||
|
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.sram.data : ALIGN(4)
|
||||
{
|
||||
_sram_data_start = ABSOLUTE(.);
|
||||
*(.sram.data)
|
||||
_sram_data_end = ABSOLUTE(.);
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
.noinit : ALIGN(4)
|
||||
{
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
KEEP(*(SW_ISR_TABLE))
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_data_end = ABSOLUTE(.);
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
#include <linker/common-ram.ld>
|
||||
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
*(.sram.bss)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
_end = ALIGN(0x8);
|
||||
_image_ram_end = ABSOLUTE(.);
|
||||
PROVIDE(end = ALIGN(0x8));
|
||||
_stack_sentry = ALIGN(0x8);
|
||||
_memmap_seg_sram0_end = ALIGN(0x8);
|
||||
} >sram0_seg :sram0_bss_phdr
|
||||
__stack = 0xbefe0000;
|
||||
_heap_sentry = 0xbefe0000;
|
||||
|
||||
.ResetVector.text : ALIGN(4)
|
||||
{
|
||||
_ResetVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
_ResetVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom0_end = ALIGN(0x8);
|
||||
} >srom0_seg :srom0_phdr
|
||||
|
||||
.MemoryExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_MemoryExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.MemoryExceptionVector.literal)
|
||||
_MemoryExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom1_end = ALIGN(0x8);
|
||||
} >srom1_seg :srom1_phdr
|
||||
|
||||
.MemoryExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_MemoryExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.MemoryExceptionVector.text))
|
||||
_MemoryExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom2_end = ALIGN(0x8);
|
||||
} >srom2_seg :srom2_phdr
|
||||
|
||||
.WindowVectors.text : ALIGN(4)
|
||||
{
|
||||
_WindowVectors_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.WindowVectors.text))
|
||||
_WindowVectors_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom4_end = ALIGN(0x8);
|
||||
} >srom4_seg :srom4_phdr
|
||||
|
||||
.Level2InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level2InterruptVector.literal)
|
||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom5_end = ALIGN(0x8);
|
||||
} >srom5_seg :srom5_phdr
|
||||
|
||||
.Level2InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level2InterruptVector.text))
|
||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom6_end = ALIGN(0x8);
|
||||
} >srom6_seg :srom6_phdr
|
||||
|
||||
.Level3InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level3InterruptVector.literal)
|
||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom7_end = ALIGN(0x8);
|
||||
} >srom7_seg :srom7_phdr
|
||||
|
||||
.Level3InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level3InterruptVector.text))
|
||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom8_end = ALIGN(0x8);
|
||||
} >srom8_seg :srom8_phdr
|
||||
|
||||
.Level4InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level4InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level4InterruptVector.literal)
|
||||
_Level4InterruptVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom9_end = ALIGN(0x8);
|
||||
} >srom9_seg :srom9_phdr
|
||||
|
||||
.Level4InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level4InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level4InterruptVector.text))
|
||||
_Level4InterruptVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom10_end = ALIGN(0x8);
|
||||
} >srom10_seg :srom10_phdr
|
||||
|
||||
.Level5InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level5InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level5InterruptVector.literal)
|
||||
_Level5InterruptVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom11_end = ALIGN(0x8);
|
||||
} >srom11_seg :srom11_phdr
|
||||
|
||||
.Level5InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level5InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level5InterruptVector.text))
|
||||
_Level5InterruptVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom12_end = ALIGN(0x8);
|
||||
} >srom12_seg :srom12_phdr
|
||||
|
||||
.DebugExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DebugExceptionVector.literal)
|
||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom13_end = ALIGN(0x8);
|
||||
} >srom13_seg :srom13_phdr
|
||||
|
||||
.DebugExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DebugExceptionVector.text))
|
||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom14_end = ALIGN(0x8);
|
||||
} >srom14_seg :srom14_phdr
|
||||
|
||||
.NMIExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.NMIExceptionVector.literal)
|
||||
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom15_end = ALIGN(0x8);
|
||||
} >srom15_seg :srom15_phdr
|
||||
|
||||
.NMIExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.NMIExceptionVector.text))
|
||||
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom16_end = ALIGN(0x8);
|
||||
} >srom16_seg :srom16_phdr
|
||||
|
||||
.KernelExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.KernelExceptionVector.literal)
|
||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom17_end = ALIGN(0x8);
|
||||
} >srom17_seg :srom17_phdr
|
||||
|
||||
.KernelExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.KernelExceptionVector.text))
|
||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom18_end = ALIGN(0x8);
|
||||
} >srom18_seg :srom18_phdr
|
||||
|
||||
.UserExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.UserExceptionVector.literal)
|
||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom19_end = ALIGN(0x8);
|
||||
} >srom19_seg :srom19_phdr
|
||||
|
||||
.UserExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.UserExceptionVector.text))
|
||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom20_end = ALIGN(0x8);
|
||||
} >srom20_seg :srom20_phdr
|
||||
|
||||
.DoubleExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DoubleExceptionVector.literal)
|
||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom21_end = ALIGN(0x8);
|
||||
} >srom21_seg :srom21_phdr
|
||||
|
||||
.DoubleExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DoubleExceptionVector.text))
|
||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom22_end = ALIGN(0x8);
|
||||
} >srom22_seg :srom22_phdr
|
||||
|
||||
.srom.rodata : ALIGN(4)
|
||||
{
|
||||
_srom_rodata_start = ABSOLUTE(.);
|
||||
*(.srom.rodata)
|
||||
_srom_rodata_end = ABSOLUTE(.);
|
||||
} >srom23_seg :srom23_phdr
|
||||
|
||||
.srom.text : ALIGN(4)
|
||||
{
|
||||
_srom_text_start = ABSOLUTE(.);
|
||||
*(.srom.literal .srom.text)
|
||||
_srom_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom23_end = ALIGN(0x8);
|
||||
} >srom23_seg :srom23_phdr
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.debug.xt.callgraph 0 :
|
||||
{
|
||||
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
|
||||
}
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <linker/intlist.ld>
|
||||
#endif
|
||||
}
|
||||
|
Loading…
Add table
Add a link
Reference in a new issue