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intel_s1000: gpio: enable GPIO handling

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Enable GPIO handling for intel_s1000. It uses a DesignWare IP.

Change-Id: I522534935e4ef3a56d93aca669f6de961d927481
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Rajavardhan Gundi 2017-10-08 08:44:24 +05:30 • committed by Anas Nashif
commit 63d50e158e
3 changed files with 19 additions and 5 deletions
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15
arch/xtensa/soc/intel_s1000/soc.h
View file

@ -6,10 +6,15 @@
#ifndef __INC_SOC_H
#define __INC_SOC_H
/*
* UART - UART0
*/
#define UART_NS16550_PORT_0_BASE_ADDR 0x00080800
#define UART_NS16550_PORT_0_CLK_FREQ 38400000
/* GPIO */
#define GPIO_DW_0_BASE_ADDR 0x00080C00
#define GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0
#define GPIO_DW_0_IRQ_FLAGS 0
#define GPIO_DW_0_IRQ 20
/* UART - UART0 */
#define UART_NS16550_PORT_0_BASE_ADDR 0x00080800
#define UART_NS16550_PORT_0_CLK_FREQ 38400000
#endif /* __INC_SOC_H */

5
boards/xtensa/intel_s1000_crb/Kconfig.defconfig
View file

@ -10,6 +10,11 @@ config BOARD
config BOARD_XTENSA
def_bool y
config GPIO_DW_0_NAME
default "GPIO_PORTA"
config GPIO_DW_0_IRQ_PRI
default 1
if UART_NS16550
config UART_NS16550_PORT_0

4
boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
View file

@ -14,6 +14,10 @@ CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_XTENSA_RESET_VECTOR=y
CONFIG_XTENSA_USE_CORE_CRT1=y
CONFIG_GPIO=y
CONFIG_GPIO_DW=y
CONFIG_GPIO_DW_0=y
CONFIG_CONSOLE=y
CONFIG_SERIAL_HAS_DRIVER=y
CONFIG_SERIAL=y