tests: benchmarks: timing_info: Enable benchmarks for xtensa.

This patch provides support needed to get timing related
information from xtensa based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This commit is contained in:
Adithya Baglody 2018-07-23 13:49:26 +05:30 committed by Anas Nashif
commit bb918d85f8
6 changed files with 46 additions and 7 deletions

View file

@ -19,6 +19,9 @@ u64_t __end_drop_to_usermode_time;
u32_t __read_swap_end_time_value;
u64_t __common_var_swap_end_time;
#if CONFIG_ARM
#include <arch/arm/cortex_m/cmsis.h>
#endif
#ifdef CONFIG_NRF_RTC_TIMER
/* To get current count of timer, first 1 need to be written into
@ -47,14 +50,26 @@ u64_t __common_var_swap_end_time;
#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
#define TIMING_INFO_GET_TIMER_VALUE() (_arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT))
#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
#elif CONFIG_XTENSA
#include <xtensa_timer.h>
#define TIMING_INFO_PRE_READ()
#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
#define TIMING_INFO_GET_TIMER_VALUE() (k_cycle_get_32())
#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
#else
/* Default case */
#error "Benchmarks have not been implemented for this architecture"
#endif /* CONFIG_NRF_RTC_TIMER */
#if defined(CONFIG_ARM) || defined(CONFIG_ARC)
void read_timer_start_of_swap(void)
{
TIMING_INFO_PRE_READ();
__start_swap_time = (u32_t) TIMING_INFO_OS_GET_TIME();
if (__read_swap_end_time_value == 1) {
TIMING_INFO_PRE_READ();
__start_swap_time = (u32_t) TIMING_INFO_OS_GET_TIME();
}
}
void read_timer_end_of_swap(void)
@ -62,7 +77,7 @@ void read_timer_end_of_swap(void)
if (__read_swap_end_time_value == 1) {
TIMING_INFO_PRE_READ();
__read_swap_end_time_value = 2;
__common_var_swap_end_time = TIMING_INFO_OS_GET_TIME();
__common_var_swap_end_time = (u64_t)TIMING_INFO_OS_GET_TIME();
}
}
@ -98,5 +113,3 @@ void read_timer_end_of_userspace_enter(void)
TIMING_INFO_PRE_READ();
__end_drop_to_usermode_time = (u32_t) TIMING_INFO_GET_TIMER_VALUE();
}
#endif /* CONFIG_ARM */

View file

@ -220,6 +220,10 @@ xtensa_switch:
* sanity.
*/
l32i a1, a2, BSA_A2_OFF
#ifdef CONFIG_EXECUTION_BENCHMARKING
call4 read_timer_end_of_swap
#endif
j _restore_context
_switch_restore_pc:
retw

View file

@ -489,6 +489,11 @@ void _timer_int_handler(void *params)
{
ARG_UNUSED(params);
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_tick_handler(void);
read_timer_start_of_tick_handler();
#endif
#ifdef CONFIG_XTENSA_ASM2
/* FIXME: the legacy xtensa code did this in the assembly
* hook, and was a little more sophisticated. We should track
@ -536,6 +541,11 @@ void _timer_int_handler(void *params)
/* Announce the tick event to the kernel. */
_sys_clock_final_tick_announce();
#endif /* CONFIG_TICKLESS_KERNEL */
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_end_of_tick_handler(void);
read_timer_end_of_tick_handler();
#endif
}

View file

@ -46,6 +46,11 @@ static inline unsigned int _Swap(unsigned int key)
struct k_thread *new_thread, *old_thread;
int ret = 0;
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_swap(void);
read_timer_start_of_swap();
#endif
old_thread = _current;
_check_stack_sentinel();

View file

@ -61,6 +61,13 @@
#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
#define TIMING_INFO_GET_TIMER_VALUE() (_arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT))
#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
#elif CONFIG_XTENSA
#define TIMING_INFO_PRE_READ()
#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
#define TIMING_INFO_GET_TIMER_VALUE() (k_cycle_get_32())
#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
#endif /* CONFIG_NRF_RTC_TIMER */
/******************************************************************************/

View file

@ -1,6 +1,6 @@
tests:
benchmark.timing.default_kernel:
arch_whitelist: x86 arm arc
arch_whitelist: x86 arm arc xtensa
tags: benchmark
benchmark.timing.userspace:
filter: CONFIG_ARCH_HAS_USERSPACE