DTS: interrupt controller: Define IRQ priorities for CAVS & DW ICTL
IRQ priorities for CAVS and DW were previously defined in Kconfig. They are now defined via DTS and removed from Kconfig. Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
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7 changed files with 36 additions and 63 deletions
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@ -11,22 +11,38 @@
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#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY
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#define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
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#define CAVS_ICTL_BASE_ADDR INTEL_CAVS_INTC_78800_BASE_ADDRESS
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#define CAVS_ICTL_0_IRQ INTEL_CAVS_INTC_78800_IRQ_0
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#define CONFIG_CAVS_ICTL_0_IRQ_PRI INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
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#define CAVS_ICTL_0_IRQ_FLAGS INTEL_CAVS_INTC_78800_IRQ_0_SENSE
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#define CAVS_ICTL_1_IRQ INTEL_CAVS_INTC_78810_IRQ_0
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#define CONFIG_CAVS_ICTL_1_IRQ_PRI INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
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#define CAVS_ICTL_1_IRQ_FLAGS INTEL_CAVS_INTC_78810_IRQ_0_SENSE
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#define CAVS_ICTL_2_IRQ INTEL_CAVS_INTC_78820_IRQ_0
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#define CONFIG_CAVS_ICTL_2_IRQ_PRI INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
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#define CAVS_ICTL_2_IRQ_FLAGS INTEL_CAVS_INTC_78820_IRQ_0_SENSE
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#define CAVS_ICTL_3_IRQ INTEL_CAVS_INTC_78830_IRQ_0
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#define CONFIG_CAVS_ICTL_3_IRQ_PRI INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
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#define CAVS_ICTL_3_IRQ_FLAGS INTEL_CAVS_INTC_78830_IRQ_0_SENSE
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#define DW_ICTL_BASE_ADDR SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
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#define DW_ICTL_IRQ ((SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define CONFIG_DW_ICTL_IRQ_PRI SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
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#define DW_ICTL_IRQ_FLAGS SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
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#define CONFIG_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS
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#define CONFIG_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY
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#define CONFIG_I2C_0_NAME SNPS_DESIGNWARE_I2C_80400_LABEL
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#define CONFIG_I2C_0_IRQ (SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
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(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(INTEL_CAVS_INTC_78800_IRQ_0 << 0)
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#define CONFIG_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
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#define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY
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/* End of SoC Level DTS fixup file */
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@ -28,28 +28,12 @@
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#define INTR_CNTL_IRQ_NUM(_irq) \
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(((_irq >> INTR_CNTL_IRQ_NUM_SHIFT) & INTR_CNTL_IRQ_NUM_MASK) - 1)
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/* CAVS interrupt logic */
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#define CAVS_ICTL_BASE_ADDR 0x00078800
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#define CAVS_ICTL_0_IRQ 0x00000006
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#define CAVS_ICTL_0_IRQ_FLAGS 0
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#define CAVS_ICTL_1_IRQ 0x0000000A
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#define CAVS_ICTL_1_IRQ_FLAGS 0
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#define CAVS_ICTL_2_IRQ 0x0000000D
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#define CAVS_ICTL_2_IRQ_FLAGS 0
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#define CAVS_ICTL_3_IRQ 0x00000010
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#define CAVS_ICTL_3_IRQ_FLAGS 0
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#define IOAPIC_EDGE 0
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#define IOAPIC_HIGH 0
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/* DW interrupt controller */
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#define DW_ICTL_IRQ 0x00000706
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#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DW_ICTL_IRQ)
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#define DW_ICTL_NUM_IRQS 9
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#define DW_ICTL_IRQ_FLAGS 0
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/* GPIO */
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#define GPIO_DW_0_BASE_ADDR 0x00080C00
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@ -148,13 +148,6 @@ config DW_ICTL_OFFSET
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help
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Parent interrupt number to which DW_ICTL maps
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config DW_ICTL_IRQ_PRI
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int "DW ICTL IRQ priority"
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depends on DW_ICTL
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default 0
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help
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IRQ priority of DW ICTL interrupt
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config DW_ISR_TBL_OFFSET
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int "Offset in the SW ISR Table"
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default 0
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@ -25,13 +25,6 @@ config CAVS_ICTL_0_NAME
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depends on CAVS_ICTL
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default "CAVS_0"
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config CAVS_ICTL_0_IRQ_PRI
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int "CAVS 0 IRQ priority"
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depends on CAVS_ICTL
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default 0
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help
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IRQ priority of CAVS 0 interrupt
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config CAVS_ICTL_0_OFFSET
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hex "Parent interrupt number to which CAVS_0 maps"
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default 0x00
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@ -42,13 +35,6 @@ config CAVS_ICTL_1_NAME
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depends on CAVS_ICTL
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default "CAVS_1"
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config CAVS_ICTL_1_IRQ_PRI
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int "CAVS 1 IRQ priority"
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depends on CAVS_ICTL
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default 0
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help
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IRQ priority of CAVS 1 interrupt
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config CAVS_ICTL_1_OFFSET
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hex "Parent interrupt number to which CAVS_1 maps"
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default 0x00
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@ -59,13 +45,6 @@ config CAVS_ICTL_2_NAME
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depends on CAVS_ICTL
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default "CAVS_2"
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config CAVS_ICTL_2_IRQ_PRI
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int "CAVS 2 IRQ priority"
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depends on CAVS_ICTL
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default 0
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help
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IRQ priority of CAVS 2 interrupt
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config CAVS_ICTL_2_OFFSET
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hex "Parent interrupt number to which CAVS_2 maps"
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default 0x00
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@ -76,13 +55,6 @@ config CAVS_ICTL_3_NAME
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depends on CAVS_ICTL
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default "CAVS_3"
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config CAVS_ICTL_3_IRQ_PRI
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int "CAVS 3 IRQ priority"
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depends on CAVS_ICTL
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default 0
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help
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IRQ priority of CAVS 3 interrupt
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config CAVS_ICTL_3_OFFSET
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hex "Parent interrupt number to which CAVS_3 maps"
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default 0x00
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@ -35,4 +35,5 @@ cell_string: IRQ
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"#cells":
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- irq
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- sense
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- priority
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...
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@ -29,4 +29,5 @@ cell_string: IRQ
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"#cells":
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- irq
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- sense
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- priority
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...
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@ -24,7 +24,7 @@
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compatible = "xtensa,core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#interrupt-cells = <3>;
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};
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};
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@ -45,8 +45,8 @@
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compatible = "intel,cavs-intc";
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reg = <0x78800 0x10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <6 0>;
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#interrupt-cells = <3>;
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interrupts = <6 0 0>;
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interrupt-parent = <&core_intc>;
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};
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@ -54,21 +54,27 @@
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compatible = "intel,cavs-intc";
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reg = <0x78810 0x10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#interrupt-cells = <3>;
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interrupts = <0xA 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs2: cavs@78820 {
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compatible = "intel,cavs-intc";
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reg = <0x78820 0x10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#interrupt-cells = <3>;
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interrupts = <0XD 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs3: cavs@78830 {
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compatible = "intel,cavs-intc";
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reg = <0x78830 0x10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#interrupt-cells = <3>;
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interrupts = <0x10 0 0>;
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interrupt-parent = <&core_intc>;
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};
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dw_intc: intc@81800 {
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reg = <0x00081800 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <7 0>;
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interrupts = <7 0 0>;
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interrupt-parent = <&cavs0>;
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};
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