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DTS: interrupt controller: Define IRQ priorities for CAVS & DW ICTL

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IRQ priorities for CAVS and DW were previously defined in Kconfig.
They are now defined via DTS and removed from Kconfig.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
This commit is contained in:
Rajavardhan Gundi 2018-05-27 23:11:57 +05:30 • committed by Anas Nashif
commit e5b0e9ac07
7 changed files with 36 additions and 63 deletions
Download patch file Download diff file Expand all files Collapse all files

26
arch/xtensa/soc/intel_s1000/dts.fixup
View file

@ -11,22 +11,38 @@
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY
#define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
#define CAVS_ICTL_BASE_ADDR INTEL_CAVS_INTC_78800_BASE_ADDRESS
#define CAVS_ICTL_0_IRQ INTEL_CAVS_INTC_78800_IRQ_0
#define CONFIG_CAVS_ICTL_0_IRQ_PRI INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
#define CAVS_ICTL_0_IRQ_FLAGS INTEL_CAVS_INTC_78800_IRQ_0_SENSE
#define CAVS_ICTL_1_IRQ INTEL_CAVS_INTC_78810_IRQ_0
#define CONFIG_CAVS_ICTL_1_IRQ_PRI INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
#define CAVS_ICTL_1_IRQ_FLAGS INTEL_CAVS_INTC_78810_IRQ_0_SENSE
#define CAVS_ICTL_2_IRQ INTEL_CAVS_INTC_78820_IRQ_0
#define CONFIG_CAVS_ICTL_2_IRQ_PRI INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
#define CAVS_ICTL_2_IRQ_FLAGS INTEL_CAVS_INTC_78820_IRQ_0_SENSE
#define CAVS_ICTL_3_IRQ INTEL_CAVS_INTC_78830_IRQ_0
#define CONFIG_CAVS_ICTL_3_IRQ_PRI INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
#define CAVS_ICTL_3_IRQ_FLAGS INTEL_CAVS_INTC_78830_IRQ_0_SENSE
#define DW_ICTL_BASE_ADDR SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
#define DW_ICTL_IRQ ((SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
#define CONFIG_DW_ICTL_IRQ_PRI SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
#define DW_ICTL_IRQ_FLAGS SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
#define CONFIG_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS
#define CONFIG_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY
#define CONFIG_I2C_0_NAME SNPS_DESIGNWARE_I2C_80400_LABEL
#define CONFIG_I2C_0_IRQ (SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
(INTEL_CAVS_INTC_78800_IRQ_0 << 0)
#define CONFIG_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
#define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY
/* End of SoC Level DTS fixup file */

16
arch/xtensa/soc/intel_s1000/soc.h
View file

@ -28,28 +28,12 @@
#define INTR_CNTL_IRQ_NUM(_irq) \
(((_irq >> INTR_CNTL_IRQ_NUM_SHIFT) & INTR_CNTL_IRQ_NUM_MASK) - 1)
/* CAVS interrupt logic */
#define CAVS_ICTL_BASE_ADDR 0x00078800
#define CAVS_ICTL_0_IRQ 0x00000006
#define CAVS_ICTL_0_IRQ_FLAGS 0
#define CAVS_ICTL_1_IRQ 0x0000000A
#define CAVS_ICTL_1_IRQ_FLAGS 0
#define CAVS_ICTL_2_IRQ 0x0000000D
#define CAVS_ICTL_2_IRQ_FLAGS 0
#define CAVS_ICTL_3_IRQ 0x00000010
#define CAVS_ICTL_3_IRQ_FLAGS 0
#define IOAPIC_EDGE 0
#define IOAPIC_HIGH 0
/* DW interrupt controller */
#define DW_ICTL_IRQ 0x00000706
#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DW_ICTL_IRQ)
#define DW_ICTL_NUM_IRQS 9
#define DW_ICTL_IRQ_FLAGS 0
/* GPIO */
#define GPIO_DW_0_BASE_ADDR 0x00080C00

7
drivers/interrupt_controller/Kconfig
View file

@ -148,13 +148,6 @@ config DW_ICTL_OFFSET
help
Parent interrupt number to which DW_ICTL maps
config DW_ICTL_IRQ_PRI
int "DW ICTL IRQ priority"
depends on DW_ICTL
default 0
help
IRQ priority of DW ICTL interrupt
config DW_ISR_TBL_OFFSET
int "Offset in the SW ISR Table"
default 0

28
drivers/interrupt_controller/Kconfig.s1000
View file

@ -25,13 +25,6 @@ config CAVS_ICTL_0_NAME
depends on CAVS_ICTL
default "CAVS_0"
config CAVS_ICTL_0_IRQ_PRI
int "CAVS 0 IRQ priority"
depends on CAVS_ICTL
default 0
help
IRQ priority of CAVS 0 interrupt
config CAVS_ICTL_0_OFFSET
hex "Parent interrupt number to which CAVS_0 maps"
default 0x00
@ -42,13 +35,6 @@ config CAVS_ICTL_1_NAME
depends on CAVS_ICTL
default "CAVS_1"
config CAVS_ICTL_1_IRQ_PRI
int "CAVS 1 IRQ priority"
depends on CAVS_ICTL
default 0
help
IRQ priority of CAVS 1 interrupt
config CAVS_ICTL_1_OFFSET
hex "Parent interrupt number to which CAVS_1 maps"
default 0x00
@ -59,13 +45,6 @@ config CAVS_ICTL_2_NAME
depends on CAVS_ICTL
default "CAVS_2"
config CAVS_ICTL_2_IRQ_PRI
int "CAVS 2 IRQ priority"
depends on CAVS_ICTL
default 0
help
IRQ priority of CAVS 2 interrupt
config CAVS_ICTL_2_OFFSET
hex "Parent interrupt number to which CAVS_2 maps"
default 0x00
@ -76,13 +55,6 @@ config CAVS_ICTL_3_NAME
depends on CAVS_ICTL
default "CAVS_3"
config CAVS_ICTL_3_IRQ_PRI
int "CAVS 3 IRQ priority"
depends on CAVS_ICTL
default 0
help
IRQ priority of CAVS 3 interrupt
config CAVS_ICTL_3_OFFSET
hex "Parent interrupt number to which CAVS_3 maps"
default 0x00

1
dts/bindings/interrupt-controller/intel,cavs-intc.yaml
View file

@ -35,4 +35,5 @@ cell_string: IRQ
"#cells":
- irq
- sense
- priority
...

1
dts/bindings/interrupt-controller/xtensa,intc.yaml
View file

@ -29,4 +29,5 @@ cell_string: IRQ
"#cells":
- irq
- sense
- priority
...

20
dts/xtensa/intel_s1000.dtsi
View file

@ -24,7 +24,7 @@
compatible = "xtensa,core-intc";
reg = <0x00 0x400>;
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <3>;
};
};
@ -45,8 +45,8 @@
compatible = "intel,cavs-intc";
reg = <0x78800 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <6 0>;
#interrupt-cells = <3>;
interrupts = <6 0 0>;
interrupt-parent = <&core_intc>;
};
@ -54,21 +54,27 @@
compatible = "intel,cavs-intc";
reg = <0x78810 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <3>;
interrupts = <0xA 0 0>;
interrupt-parent = <&core_intc>;
};
cavs2: cavs@78820 {
compatible = "intel,cavs-intc";
reg = <0x78820 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <3>;
interrupts = <0XD 0 0>;
interrupt-parent = <&core_intc>;
};
cavs3: cavs@78830 {
compatible = "intel,cavs-intc";
reg = <0x78830 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <3>;
interrupts = <0x10 0 0>;
interrupt-parent = <&core_intc>;
};
dw_intc: intc@81800 {
@ -76,7 +82,7 @@
reg = <0x00081800 0x400>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <7 0>;
interrupts = <7 0 0>;
interrupt-parent = <&cavs0>;
};